Trait SynthesizableClosure

Source

pub trait SynthesizableClosure {
    // Provided method
    fn synthesizable_closure_violations(
        &self,
    ) -> Vec<SynthesizableClosureViolation> { ... }
}

Expand description

Documented constraints for closures that may enter the synthesizable hardware path (FR74 / Cap-R-48…50 / AD-18).

A legal synthesizable closure is:

pure (no side effects / I/O / threads) — Cap-R-50
no heap (Box / software Vec / String / …) — Cap-R-48
no runtime capture state (non-const captures; Wire/Reg still → E0142) — Cap-R-49
dissolved to ordinary HIR before freeze — never a Rust closure object in tick / FIRRTL / Chisel (NFR36 / Cap-R-58)

Comb inline (Story 28.2 / Cap-R-55): call [ElaborateSession::inline_comb_fn] after Cap-R-60 check. Seq inline (Story 28.3 / Cap-R-56): [ElaborateSession::inline_seq_fn] with Cap-R-70 ownership checks. Automatic rustc capture analysis is out of scope — macros / ATDD / typed surfaces pass violation tokens to [ElaborateSession::check_synthesizable_closure] / [ElaborateSession::check_seq_ownership].

Empty / simple stand-ins (LegalEmptyClosure, LegalSimpleClosure) implement this marker with no violations.