Struct ElaborateSession 

pub struct ElaborateSession { /* private fields */ }

Session token holding the unfrozen circuit (AD-13).

Implementations

impl ElaborateSession

pub fn new(circuit_name: impl Into<String>) -> Self

pub fn begin_module(&mut self, name: impl Into<String>, span: Span)

pub fn bind_domain(&mut self, name: impl Into<String>, domain: u32)

Bind a phantom clock-domain id to a signal (AD-22).

pub fn mark_cdc_bridge(&mut self, name: impl Into<String>)

Mark a CDC bridge signal that may legally cross domains.

pub fn add_input(&mut self, name: impl Into<String>, ty: GroundType, span: Span)

pub fn add_output( &mut self, name: impl Into<String>, ty: GroundType, span: Span, )

pub fn add_inout(&mut self, name: impl Into<String>, ty: GroundType, span: Span)

Top-level InOut / Analog IO (FR27). Non-top uses are rejected at freeze.

pub fn declare_wire( &mut self, name: impl Into<String>, ty: GroundType, span: Span, )

pub fn declare_reg( &mut self, name: impl Into<String>, ty: GroundType, span: Span, )

pub fn declare_reg_ex( &mut self, name: impl Into<String>, ty: GroundType, async_reset: bool, has_enable: bool, span: Span, )

Declare a register with optional async reset / clock enable (AD-23).

pub fn declare_sync_read_mem( &mut self, name: impl Into<String>, depth: u32, width: u32, span: Span, )

Declare SyncReadMem (CHIRRTL-friendly; sync_read=true).

pub fn declare_mem( &mut self, name: impl Into<String>, depth: u32, width: u32, span: Span, )

Declare Mem (async-read / reg-file style; sync_read=false).

pub fn check_add(&mut self, lhs: &str, rhs: &str, span: Span) -> Option<u32>

Same-width binary add. Returns Err diagnostic via session if widths differ.

pub fn check_connect(&mut self, lhs: &str, rhs: &str, span: Span) -> Option<u32>

pub fn pad_to( &mut self, src: &str, to_width: u32, dest: impl Into<String>, span: Span, ) -> bool

Explicit zero-extend / sign-pad to a wider width; records result as a temp wire name.

pub fn trunc_to( &mut self, src: &str, to_width: u32, dest: impl Into<String>, span: Span, ) -> bool

pub fn begin_combinational(&mut self, span: Span)

pub fn begin_sequential(&mut self, span: Span)

pub fn begin_then(&mut self, span: Span)

Start an if-branch inside a combinational process (latch analysis).

pub fn begin_else(&mut self, span: Span)

pub fn end_if(&mut self, span: Span)

pub fn assign_add( &mut self, dst: impl Into<String>, lhs: impl Into<String>, rhs: impl Into<String>, span: Span, )

Combinational assign dst = lhs + rhs (same-width required).

pub fn assign_net( &mut self, name: impl Into<String>, from: impl Into<String>, span: Span, )

Assign a combinational net / output / wire from from.

pub fn assign_reg_d_inc(&mut self, name: impl Into<String>, span: Span)

Assign Reg.d next-state as name + 1 (wrapping).

pub fn assign_reg_d_from( &mut self, name: impl Into<String>, from: impl Into<String>, span: Span, )

Assign Reg.d from another signal.

pub fn assign_mem_write( &mut self, mem: impl Into<String>, addr: impl Into<String>, data: impl Into<String>, span: Span, )

Sequential SyncReadMem / Mem write: mem[addr] <= data.

pub fn assign_reg_d_mem_read( &mut self, reg: impl Into<String>, mem: impl Into<String>, addr: impl Into<String>, span: Span, )

Sequential SyncReadMem read into a register (latency 1 on tick).

pub fn end_process(&mut self)

pub fn end_module(&mut self)

pub fn finish(self) -> Result<FrozenHir, Diagnostics>

pub fn reject_unsynthesizable(&mut self, construct: &str, span: Span)

Record a synthesizable-path violation (heap, threads, f64, …) as a structured diagnostic.

pub fn add_instance( &mut self, name: impl Into<String>, module: impl Into<String>, connects: Vec<(String, String)>, params: Vec<(String, u32)>, span: Span, )

Hierarchical instance (Story 2.2); not flattened at elaborate.

pub fn add_dangling_input( &mut self, instance: &str, child_port: impl Into<String>, span: Span, )