ComponentTypeVerifyCompute

axiom_query::verify_compute::types

Struct ComponentTypeVerifyCompute 

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pub struct ComponentTypeVerifyCompute;
Expand description

Identifier for the component type of Verify Compute Circuit

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impl ComponentType<Fr> for ComponentTypeVerifyCompute

Verify Compute has no virtual table as output

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type InputValue = LogicalEmpty<Fr>

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type InputWitness = LogicalEmpty<AssignedValue<Fr>>

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type OutputValue = LogicalEmpty<Fr>

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type OutputWitness = LogicalEmpty<AssignedValue<Fr>>

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type LogicalInput = LogicalEmpty<Fr>

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fn get_type_id() -> ComponentTypeId

Get ComponentTypeId of this component type.
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fn logical_result_to_virtual_rows_impl( _ins: &LogicalResult<Fr, Self>, ) -> Vec<(Self::InputValue, Self::OutputValue)>

Convert a logical result to 1 or multiple virtual rows.
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fn logical_input_to_virtual_rows_impl( _li: &Self::LogicalInput, ) -> Vec<Self::InputValue>

Real implementation to convert a logical input to virtual rows.
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type Commiter = BasicComponentCommiter<F>

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fn get_type_name() -> &'static str

Get ComponentTypeName for logging/debugging.
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fn logical_result_to_virtual_rows( ins: &LogicalResult<F, Self>, ) -> Vec<(Self::InputValue, Self::OutputValue)>

Wrap logical_result_to_virtual_rows_impl with sanity check.
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fn logical_input_to_virtual_rows( li: &Self::LogicalInput, ) -> Vec<Self::InputValue>

Wrap logical_input_to_virtual_rows_impl with sanity check. TODO: we are not using this.
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fn rlc_virtual_rows( _: (&mut Context<F>, &mut Context<F>), range_chip: &RangeChip<F>, rlc_chip: &RlcChip<F>, inputs: &[(Self::InputWitness, Self::OutputWitness)], ) -> Vec<AssignedValue<F>>

RLC virtual rows. A logical input might take multiple virtual rows. The default implementation is for the fixed length case.

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