Expand description
ax-page-table-entry
Page table entry definition for various hardware architectures
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§Introduction
ax-page-table-entry provides Page table entry definition for various hardware architectures. It is maintained as part of the TGOSKits component set and is intended for Rust projects that integrate with ArceOS, AxVisor, or related low-level systems software.
ax-page-table-entry was derived from https://github.com/arceos-org/page_table_multiarch
§Quick Start
§Installation
Add this crate to your Cargo.toml:
[dependencies]
ax-page-table-entry = "0.8.1"§Run Check and Test
# Enter the crate directory
cd components/page_table_multiarch/page_table_entry
# Format code
cargo fmt --all
# Run clippy
cargo clippy --all-targets --all-features
# Run tests
cargo test --all-features
# Build documentation
cargo doc --no-deps§Integration
§Example
use ax_page_table_entry as _;
fn main() {
// Integrate `ax-page-table-entry` into your project here.
}§Documentation
Generate and view API documentation:
cargo doc --no-deps --openOnline documentation: docs.rs/ax-page-table-entry
§Contributing
- Fork the repository and create a branch
- Run local format and checks
- Run local tests relevant to this crate
- Submit a PR and ensure CI passes
§License
Licensed under the Apache License, Version 2.0. See LICENSE for details.
Modules§
- aarch64
AArch64 - AArch64 VMSAv8-64 translation table format descriptors.
- arm
ARM - ARMv7-A Short-descriptor translation table format.
- loongarch64
LoongArch64 - loongarch64 page table entries.
- riscv
RISC-V RV32 or RISC-V RV64 - RISC-V page table entries.
- x86_64
x86-64 - x86 page table entries on 64-bit paging.
Structs§
- Mapping
Flags - Generic page table entry flags that indicate the corresponding mapped memory region permissions and attributes.
Traits§
- GenericPTE
- A generic page table entry.