Expand description
Wrapper functions for assembly instructions.
Functions§
- clean_
dcache_ range_ to_ pou - Cleans a data cache range to the point of unification.
- dcache_
line_ size_ from_ ctr - Reads the data cache line size from
CTR_EL0and returns it in bytes. - disable_
irqs - Makes the current CPU to ignore interrupts.
- enable_
fp - Enable FP/SIMD instructions by setting the
FPENfield inCPACR_EL1. - enable_
irqs - Allows the current CPU to respond to interrupts.
- flush_
dcache_ line - Cleans and invalidates the data cache line that covers the given address.
- flush_
icache_ all - Flushes the entire instruction cache.
- flush_
tlb - Flushes the TLB.
- halt
- Halt the current CPU.
- icache_
line_ size_ from_ ctr - Reads the instruction cache line size from
CTR_EL0and returns it in bytes. - irqs_
enabled - Returns whether the current CPU is allowed to respond to interrupts.
- read_
kernel_ page_ table - Reads the current page table root register for kernel space (
TTBR1_EL1). - read_
thread_ pointer - Reads the thread pointer of the current CPU (
TPIDR_EL0). - read_
user_ page_ table - Reads the current page table root register for user space (
TTBR0_EL1). - user_
copy ⚠uspace - Copies data from source to destination, where addresses may be in user space. Equivalent to memcpy.
- wait_
for_ irqs - Relaxes the current CPU and waits for interrupts.
- write_
exception_ ⚠vector_ base - Writes exception vector base address register (
VBAR_EL1). - write_
kernel_ ⚠page_ table - Writes the register to update the current page table root for kernel space
(
TTBR1_EL1). - write_
thread_ ⚠pointer - Writes the thread pointer of the current CPU (
TPIDR_EL0). - write_
user_ ⚠page_ table - Writes the register to update the current page table root for user space
(
TTBR1_EL0). When the “arm-el2” feature is enabled, for user-mode programs, virtualization is completely transparent to them, so there is no need to modify