Enum Msr 

#[repr(u32)]
pub enum Msr {
    Ia32FeatureControl = 58,
    Ia32SysenterCs = 372,
    Ia32SysenterEsp = 373,
    Ia32SysenterEip = 374,
    Ia32Pat = 631,
    Ia32VmxBasic = 1_152,
    Ia32VmxPinbasedCtls = 1_153,
    Ia32VmxProcbasedCtls = 1_154,
    Ia32VmxExitCtls = 1_155,
    Ia32VmxEntryCtls = 1_156,
    Ia32VmxMisc = 1_157,
    Ia32VmxCr0Fixed0 = 1_158,
    Ia32VmxCr0Fixed1 = 1_159,
    Ia32VmxCr4Fixed0 = 1_160,
    Ia32VmxCr4Fixed1 = 1_161,
    Ia32VmxProcbasedCtls2 = 1_163,
    Ia32VmxEptVpidCap = 1_164,
    Ia32VmxTruePinbasedCtls = 1_165,
    Ia32VmxTrueProcbasedCtls = 1_166,
    Ia32VmxTrueExitCtls = 1_167,
    Ia32VmxTrueEntryCtls = 1_168,
    Ia32Xss = 3_488,
    Ia32Efer = 3_221_225_600,
    Ia32Star = 3_221_225_601,
    Ia32Lstar = 3_221_225_602,
    Ia32Cstar = 3_221_225_603,
    Ia32Fmask = 3_221_225_604,
    Ia32FsBase = 3_221_225_728,
    Ia32GsBase = 3_221_225_729,
    Ia32KernelGsbase = 3_221_225_730,
    VmCr = 3_221_291_284,
    Ignne = 3_221_291_285,
    VmHsavePa = 3_221_291_287,
    PerfEvtSel0 = 3_221_291_520,
    PerfEvtSel1 = 3_221_291_522,
    PerfEvtSel2 = 3_221_291_524,
    PerfEvtSel3 = 3_221_291_526,
    PerfEvtSel4 = 3_221_291_528,
    PerfEvtSel5 = 3_221_291_530,
}

Architectural and vendor MSR identifiers used by CPU and VM control owners.

Variants

Ia32FeatureControl = 58

IA32_FEATURE_CONTROL (Intel SDM / AMD APM register identifier).

Ia32SysenterCs = 372

IA32_SYSENTER_CS (Intel SDM / AMD APM register identifier).

Ia32SysenterEsp = 373

IA32_SYSENTER_ESP (Intel SDM / AMD APM register identifier).

Ia32SysenterEip = 374

IA32_SYSENTER_EIP (Intel SDM / AMD APM register identifier).

Ia32Pat = 631

IA32_PAT (Intel SDM / AMD APM register identifier).

Ia32VmxBasic = 1_152

IA32_VMX_BASIC (Intel SDM / AMD APM register identifier).

Ia32VmxPinbasedCtls = 1_153

IA32_VMX_PINBASED_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxProcbasedCtls = 1_154

IA32_VMX_PROCBASED_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxExitCtls = 1_155

IA32_VMX_EXIT_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxEntryCtls = 1_156

IA32_VMX_ENTRY_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxMisc = 1_157

IA32_VMX_MISC (Intel SDM / AMD APM register identifier).

Ia32VmxCr0Fixed0 = 1_158

IA32_VMX_CR0_FIXED0 (Intel SDM / AMD APM register identifier).

Ia32VmxCr0Fixed1 = 1_159

IA32_VMX_CR0_FIXED1 (Intel SDM / AMD APM register identifier).

Ia32VmxCr4Fixed0 = 1_160

IA32_VMX_CR4_FIXED0 (Intel SDM / AMD APM register identifier).

Ia32VmxCr4Fixed1 = 1_161

IA32_VMX_CR4_FIXED1 (Intel SDM / AMD APM register identifier).

Ia32VmxProcbasedCtls2 = 1_163

IA32_VMX_PROCBASED_CTLS2 (Intel SDM / AMD APM register identifier).

Ia32VmxEptVpidCap = 1_164

IA32_VMX_EPT_VPID_CAP (Intel SDM / AMD APM register identifier).

Ia32VmxTruePinbasedCtls = 1_165

IA32_VMX_TRUE_PINBASED_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxTrueProcbasedCtls = 1_166

IA32_VMX_TRUE_PROCBASED_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxTrueExitCtls = 1_167

IA32_VMX_TRUE_EXIT_CTLS (Intel SDM / AMD APM register identifier).

Ia32VmxTrueEntryCtls = 1_168

IA32_VMX_TRUE_ENTRY_CTLS (Intel SDM / AMD APM register identifier).

Ia32Xss = 3_488

IA32_XSS (Intel SDM / AMD APM register identifier).

Ia32Efer = 3_221_225_600

IA32_EFER (Intel SDM / AMD APM register identifier).

Ia32Star = 3_221_225_601

IA32_STAR (Intel SDM / AMD APM register identifier).

Ia32Lstar = 3_221_225_602

IA32_LSTAR (Intel SDM / AMD APM register identifier).

Ia32Cstar = 3_221_225_603

IA32_CSTAR (Intel SDM / AMD APM register identifier).

Ia32Fmask = 3_221_225_604

IA32_FMASK (Intel SDM / AMD APM register identifier).

Ia32FsBase = 3_221_225_728

IA32_FS_BASE (Intel SDM / AMD APM register identifier).

Ia32GsBase = 3_221_225_729

IA32_GS_BASE (Intel SDM / AMD APM register identifier).

Ia32KernelGsbase = 3_221_225_730

IA32_KERNEL_GSBASE (Intel SDM / AMD APM register identifier).

VmCr = 3_221_291_284

VM_CR (Intel SDM / AMD APM register identifier).

Ignne = 3_221_291_285

IGNNE (Intel SDM / AMD APM register identifier).

VmHsavePa = 3_221_291_287

VM_HSAVE_PA (Intel SDM / AMD APM register identifier).

PerfEvtSel0 = 3_221_291_520

PERF_EVT_SEL0 (Intel SDM / AMD APM register identifier).

PerfEvtSel1 = 3_221_291_522

PERF_EVT_SEL1 (Intel SDM / AMD APM register identifier).

PerfEvtSel2 = 3_221_291_524

PERF_EVT_SEL2 (Intel SDM / AMD APM register identifier).

PerfEvtSel3 = 3_221_291_526

PERF_EVT_SEL3 (Intel SDM / AMD APM register identifier).

PerfEvtSel4 = 3_221_291_528

PERF_EVT_SEL4 (Intel SDM / AMD APM register identifier).

PerfEvtSel5 = 3_221_291_530

PERF_EVT_SEL5 (Intel SDM / AMD APM register identifier).

Implementations

impl Msr

pub unsafe fn read(self) -> u64

Reads the complete register value.

Safety

Execute at ring 0 on a CPU implementing this register with access permitted by any higher virtualization layer.

pub unsafe fn write(self, value: u64)

Writes a validated register value.

Safety

The caller must own this register’s machine-state transition, establish its availability and reserved-bit rules, and retain referenced memory and execution state for as long as the hardware can use the value.

Trait Implementations

impl Clone for Msr

fn clone(&self) -> Msr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Msr

impl Debug for Msr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for Msr

impl PartialEq for Msr

fn eq(&self, other: &Msr) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for Msr