Struct El2 

pub struct El2;

Available on AArch64 only.

Non-VHE EL2 stage-one translation and native exception registers. Guest stage-two translation is a separate VTTBR/VTCR capability.

Implementations

impl El2

pub unsafe fn init_trap()

Installs native non-VHE EL2 vectors without modifying a guest EL1 bank.

Safety

Execute at non-VHE EL2 with IRQs masked and a valid kernel stack and CPU anchor installed. The mapped CPU vector text must remain executable.

impl El2

pub unsafe fn init_boot_trap()

Installs the early vector using the boot owner’s exception policy.

Safety

Execute at the corresponding EL with a valid stack and IRQs masked. The vector and boot handler must remain mapped and callable; runtime TLS and CPU-local services need not be initialized.

pub fn vector_base() -> VirtAddr

Reads the currently installed vector base for this exception level.

impl El2

pub unsafe fn enter(entry: VirtAddr, stack: VirtAddr, argument: usize) -> !

Transfers from EL3 to a non-secure AArch64 EL2 boot entry with IRQs masked.

Safety

Execute at EL3 with exclusive ownership of the lower exception registers. Entry and its 16-byte-aligned exclusive stack must be accessible at EL2; entry accepts its argument in x0. No live stack resource needs destruction.

impl El2

pub fn flush_tlb(address: Option<VirtAddr>)

Invalidates a non-VHE EL2 stage-one translation on this CPU. This does not invalidate guest stage-two translations.

impl El2

pub fn read_kernel_page_table() -> PhysAddr

Returns the non-VHE EL2 kernel’s TTBR0 base.

pub unsafe fn write_kernel_page_table(root: PhysAddr)

Replaces the non-VHE EL2 stage-one root without invalidation.

Safety

The caller must retain the tables and all active EL2 code, stack and data mappings and perform required translation synchronization.

pub const fn address_space_tag_capacity() -> u32

Non-VHE EL2 native translations have no userspace ASID allocation.

pub fn flush_tlb_range(start: VirtAddr, size: usize)

Invalidates all non-VHE EL2 translations intersecting a local byte range.

impl El2

pub unsafe fn configure_stage1(mair: u64)

Programs the existing four-level, 4-KiB stage-one geometry and MAIR.

Safety

The caller must own this CPU with IRQs masked before enabling this translation regime. Existing translations must not depend on the old configuration. MAIR slots must agree with every installed descriptor.

impl El2

pub fn is_mmu_enabled() -> bool

Returns whether this translation regime’s MMU is enabled.

pub unsafe fn enable_mmu_and_caches()

Enables translation and native cache access for this regime.

Safety

Valid roots, MAIR and geometry must be installed. The new mappings must retain current code, stack and data until the owner’s next handoff.

impl El2

pub fn flush_tlb_inner_shareable(address: Option<VirtAddr>)

Invalidates stage-one translations throughout the inner-shareable domain.

Trait Implementations

impl Clone for El2

fn clone(&self) -> El2

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for El2

impl Debug for El2

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for El2

fn default() -> El2

Returns the “default value” for a type.

impl Stage1Regime for El2

const EL2: bool = true

Available on AArch64 only.

Whether the descriptor belongs to the non-VHE EL2 regime.