Struct El1 

pub struct El1;

Available on AArch64 only.

EL1 stage-one translation and native exception registers.

Implementations

impl El1

pub unsafe fn init_trap()

Installs native EL1 vectors and removes the boot lower-address mapping.

Safety

Execute at EL1 with IRQs masked, a valid kernel stack and kernel CPU anchor installed. No live mapping may depend on the boot TTBR0_EL1 root.

impl El1

pub unsafe fn init_boot_trap()

Installs the early vector using the boot owner’s exception policy.

Safety

Execute at the corresponding EL with a valid stack and IRQs masked. The vector and boot handler must remain mapped and callable; runtime TLS and CPU-local services need not be initialized.

pub fn vector_base() -> VirtAddr

Reads the currently installed vector base for this exception level.

impl El1

pub unsafe fn enter(entry: VirtAddr, stack: VirtAddr, argument: usize) -> !

Transfers from EL2 or EL3 to a non-secure AArch64 EL1 boot entry. Physical timer access is enabled and the virtual counter offset is zero.

Safety

Execute at EL2/EL3 before admitting other owners of the lower register banks. Entry and its 16-byte-aligned exclusive stack must be accessible at EL1 with the currently installed translation state. Entry accepts its sole argument in x0. No live resource may need destruction on this stack.

impl El1

pub fn flush_tlb(address: Option<VirtAddr>)

Invalidates an EL1 stage-one translation on this CPU, across all ASIDs.

impl El1

pub fn read_kernel_page_table() -> PhysAddr

Returns the EL1 kernel’s TTBR1 base, excluding its ASID field.

pub unsafe fn write_kernel_page_table(root: PhysAddr)

Replaces the EL1 kernel root without invalidating cached translations.

Safety

The caller must retain the new tables and all current code, stack and data mappings at EL1, and perform required translation synchronization.

pub fn address_space_tag_capacity() -> u32

Returns the configured EL1 ASID capacity.

pub fn flush_tlb_range(start: VirtAddr, size: usize)

Invalidates all EL1 translations intersecting a local byte range.

impl El1

pub unsafe fn configure_stage1(mair: u64)

Programs the existing four-level, 4-KiB stage-one geometry and MAIR.

Safety

The caller must own this CPU with IRQs masked before enabling this translation regime. Existing translations must not depend on the old configuration. MAIR slots must agree with every installed descriptor.

impl El1

pub fn is_mmu_enabled() -> bool

Returns whether this translation regime’s MMU is enabled.

pub unsafe fn enable_mmu_and_caches()

Enables translation and native cache access for this regime.

Safety

Valid roots, MAIR and geometry must be installed. The new mappings must retain current code, stack and data until the owner’s next handoff.

impl El1

pub fn flush_tlb_inner_shareable(address: Option<VirtAddr>)

Invalidates stage-one translations throughout the inner-shareable domain.

impl El1

pub fn read_kernel_address_space() -> HardwareAddressSpace

Reads the kernel TTBR1 base and ASID together.

pub fn read_user_address_space() -> HardwareAddressSpace

Reads the lower-address TTBR0 base and ASID together.

pub unsafe fn write_kernel_address_space(space: HardwareAddressSpace)

Installs a kernel TTBR1 root and ASID without implicit invalidation.

Safety

The aligned root and supported ASID must remain owned while active. Current mappings must survive the write; the owner arranges TLB ordering.

pub unsafe fn write_user_address_space(space: HardwareAddressSpace)

Installs a lower-address TTBR0 root and ASID without implicit invalidation.

Safety

The aligned root and supported ASID must remain owned while active. No in-flight lower-address access may use the retired mapping.

Trait Implementations

impl Clone for El1

fn clone(&self) -> El1

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for El1

impl Debug for El1

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for El1

fn default() -> El1

Returns the “default value” for a type.

impl Stage1Regime for El1

const EL2: bool = false

Available on AArch64 only.

Whether the descriptor belongs to the non-VHE EL2 regime.