Struct aw_soc::phy::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 41 fields
pub pir: RW<u32>,
pub pwrctl: RW<u32>,
pub mrctrl0: RW<u32>,
pub clken: RW<u32>,
pub pgsr: [RW<u32>; 2],
pub statr: RW<u32>,
pub lp3mr11: RW<u32>,
pub mr: [RW<u32>; 4],
pub ptr: [RW<u32>; 5],
pub dramtmg: [RW<u32>; 9],
pub odtcfg: RW<u32>,
pub pitmg: [RW<u32>; 2],
pub lptpr: RW<u32>,
pub rfshctl0: RW<u32>,
pub rfshtmg: RW<u32>,
pub rfshctl1: RW<u32>,
pub pwrtmg: RW<u32>,
pub asrc: RW<u32>,
pub asrtc: RW<u32>,
pub vtfcr: RW<u32>,
pub dqsgmr: RW<u32>,
pub dtcr: RW<u32>,
pub dtar0: RW<u32>,
pub pgcr: [RW<u32>; 4],
pub iovcr0: RW<u32>,
pub iovcr1: RW<u32>,
pub dxccr: RW<u32>,
pub odtmap: RW<u32>,
pub zqctl: [RW<u32>; 2],
pub zqcr: RW<u32>,
pub zqsr: RW<u32>,
pub zqdr: [RW<u32>; 3],
pub sched: RW<u32>,
pub perfhpr: [RW<u32>; 2],
pub perflpr: [RW<u32>; 2],
pub perfwr: [RW<u32>; 2],
pub acmdlr: RW<u32>,
pub acldlr: RW<u32>,
pub aciocr0: RW<u32>,
pub datx: [Datx8; 4],
pub upd2: RW<u32>,
/* private fields */
}Expand description
Physical layer peripheral.
Fields§
§pir: RW<u32>PHY initialization register
pwrctl: RW<u32>§mrctrl0: RW<u32>§clken: RW<u32>§pgsr: [RW<u32>; 2]PHY general status registers
statr: RW<u32>§lp3mr11: RW<u32>§mr: [RW<u32>; 4]mode registers
ptr: [RW<u32>; 5]PHY timing registers
dramtmg: [RW<u32>; 9]DRAM timing registers
odtcfg: RW<u32>§pitmg: [RW<u32>; 2]PHY interface timing registers
lptpr: RW<u32>§rfshctl0: RW<u32>§rfshtmg: RW<u32>refresh timing
rfshctl1: RW<u32>§pwrtmg: RW<u32>§asrc: RW<u32>§asrtc: RW<u32>§vtfcr: RW<u32>§dqsgmr: RW<u32>§dtcr: RW<u32>§dtar0: RW<u32>§pgcr: [RW<u32>; 4]PHY general configuration registers
iovcr0: RW<u32>§iovcr1: RW<u32>§dxccr: RW<u32>§odtmap: RW<u32>§zqctl: [RW<u32>; 2]§zqcr: RW<u32>ZQ control register
zqsr: RW<u32>ZQ status register
zqdr: [RW<u32>; 3]ZQ data registers
sched: RW<u32>§perfhpr: [RW<u32>; 2]§perflpr: [RW<u32>; 2]§perfwr: [RW<u32>; 2]§acmdlr: RW<u32>§acldlr: RW<u32>§aciocr0: RW<u32>§datx: [Datx8; 4]§upd2: RW<u32>