Struct atsaml21e16b::tcc0::evctrl::W
source · pub struct W(_);
Expand description
Register EVCTRL
writer
Implementations§
source§impl W
impl W
sourcepub fn mcei0(&mut self) -> MCEI0_W<'_, 16>
pub fn mcei0(&mut self) -> MCEI0_W<'_, 16>
Bit 16 - Match or Capture Channel 0 Event Input Enable
sourcepub fn mcei1(&mut self) -> MCEI1_W<'_, 17>
pub fn mcei1(&mut self) -> MCEI1_W<'_, 17>
Bit 17 - Match or Capture Channel 1 Event Input Enable
sourcepub fn mcei2(&mut self) -> MCEI2_W<'_, 18>
pub fn mcei2(&mut self) -> MCEI2_W<'_, 18>
Bit 18 - Match or Capture Channel 2 Event Input Enable
sourcepub fn mcei3(&mut self) -> MCEI3_W<'_, 19>
pub fn mcei3(&mut self) -> MCEI3_W<'_, 19>
Bit 19 - Match or Capture Channel 3 Event Input Enable
sourcepub fn mceo0(&mut self) -> MCEO0_W<'_, 24>
pub fn mceo0(&mut self) -> MCEO0_W<'_, 24>
Bit 24 - Match or Capture Channel 0 Event Output Enable
sourcepub fn mceo1(&mut self) -> MCEO1_W<'_, 25>
pub fn mceo1(&mut self) -> MCEO1_W<'_, 25>
Bit 25 - Match or Capture Channel 1 Event Output Enable
sourcepub fn mceo2(&mut self) -> MCEO2_W<'_, 26>
pub fn mceo2(&mut self) -> MCEO2_W<'_, 26>
Bit 26 - Match or Capture Channel 2 Event Output Enable
Methods from Deref<Target = W<EVCTRL_SPEC>>§
sourcepub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self
Writes raw bits to the register.
Safety
Read datasheet or reference manual to find what values are allowed to pass.
Examples found in repository?
More examples
Additional examples can be found in:
- src/ac/scaler.rs
- src/ac/winctrl.rs
- src/adc/avgctrl.rs
- src/adc/ctrla.rs
- src/adc/ctrlb.rs
- src/adc/dbgctrl.rs
- src/adc/evctrl.rs
- src/adc/intenclr.rs
- src/adc/intenset.rs
- src/adc/intflag.rs
- src/adc/refctrl.rs
- src/adc/sampctrl.rs
- src/adc/swtrig.rs
- src/aes/ctrlb.rs
- src/aes/databufptr.rs
- src/aes/dbgctrl.rs
- src/aes/intenclr.rs
- src/aes/intenset.rs
- src/aes/intflag.rs
- src/ccl/ctrl.rs
- src/ccl/seqctrl.rs
- src/dac/ctrla.rs
- src/dac/ctrlb.rs
- src/dac/dbgctrl.rs
- src/dac/evctrl.rs
- src/dac/intenclr.rs
- src/dac/intenset.rs
- src/dac/intflag.rs
- src/dmac/chctrla.rs
- src/dmac/chid.rs
- src/dmac/chintenclr.rs
- src/dmac/chintenset.rs
- src/dmac/chintflag.rs
- src/dmac/crcstatus.rs
- src/dmac/dbgctrl.rs
- src/dmac/qosctrl.rs
- src/dsu/ctrl.rs
- src/dsu/statusa.rs
- src/eic/ctrla.rs
- src/eic/nmictrl.rs
- src/evsys/ctrla.rs
- src/gclk/ctrla.rs
- src/mclk/bupdiv.rs
- src/mclk/cpudiv.rs
- src/mclk/ctrla.rs
- src/mclk/intenclr.rs
- src/mclk/intenset.rs
- src/mclk/intflag.rs
- src/mclk/lpdiv.rs
- src/nvmctrl/intenclr.rs
- src/nvmctrl/intenset.rs
- src/nvmctrl/intflag.rs
- src/opamp/ctrla.rs
- src/oscctrl/dfllsync.rs
- src/oscctrl/dpllctrla.rs
- src/oscctrl/dpllpresc.rs
- src/oscctrl/osc16mctrl.rs
- src/pac/evctrl.rs
- src/pac/intenclr.rs
- src/pac/intenset.rs
- src/pm/ctrla.rs
- src/pm/intenclr.rs
- src/pm/intenset.rs
- src/pm/intflag.rs
- src/pm/plcfg.rs
- src/pm/pwsakdly.rs
- src/pm/sleepcfg.rs
- src/port/pincfg0_.rs
- src/port/pmux0_.rs
- src/rstc/wkdbconf.rs
- src/rtc/mode0/dbgctrl.rs
- src/rtc/mode0/freqcorr.rs
- src/rtc/mode1/dbgctrl.rs
- src/rtc/mode1/freqcorr.rs
- src/rtc/mode2/dbgctrl.rs
- src/rtc/mode2/freqcorr.rs
- src/rtc/mode2/mask.rs
- src/sercom0/i2cm/data.rs
- src/sercom0/i2cm/dbgctrl.rs
- src/sercom0/i2cm/intenclr.rs
- src/sercom0/i2cm/intenset.rs
- src/sercom0/i2cm/intflag.rs
- src/sercom0/i2cs/data.rs
- src/sercom0/i2cs/intenclr.rs
- src/sercom0/i2cs/intenset.rs
- src/sercom0/i2cs/intflag.rs
- src/sercom0/spi/baud.rs
- src/sercom0/spi/dbgctrl.rs
- src/sercom0/spi/intenclr.rs
- src/sercom0/spi/intenset.rs
- src/sercom0/spi/intflag.rs
- src/sercom0/usart/dbgctrl.rs
- src/sercom0/usart/intenclr.rs
- src/sercom0/usart/intenset.rs
- src/sercom0/usart/intflag.rs
- src/sercom0/usart/rxpl.rs
- src/tc0/count16/ctrlbclr.rs
- src/tc0/count16/ctrlbset.rs
- src/tc0/count16/dbgctrl.rs
- src/tc0/count16/drvctrl.rs
- src/tc0/count16/intenclr.rs
- src/tc0/count16/intenset.rs
- src/tc0/count16/intflag.rs
- src/tc0/count16/status.rs
- src/tc0/count16/wave.rs
- src/tc0/count32/ctrlbclr.rs
- src/tc0/count32/ctrlbset.rs
- src/tc0/count32/dbgctrl.rs
- src/tc0/count32/drvctrl.rs
- src/tc0/count32/intenclr.rs
- src/tc0/count32/intenset.rs
- src/tc0/count32/intflag.rs
- src/tc0/count32/status.rs
- src/tc0/count32/wave.rs
- src/tc0/count8/cc.rs
- src/tc0/count8/ccbuf.rs
- src/tc0/count8/count.rs
- src/tc0/count8/ctrlbclr.rs
- src/tc0/count8/ctrlbset.rs
- src/tc0/count8/dbgctrl.rs
- src/tc0/count8/drvctrl.rs
- src/tc0/count8/intenclr.rs
- src/tc0/count8/intenset.rs
- src/tc0/count8/intflag.rs
- src/tc0/count8/per.rs
- src/tc0/count8/perbuf.rs
- src/tc0/count8/status.rs
- src/tc0/count8/wave.rs
- src/tcc0/ctrlbclr.rs
- src/tcc0/ctrlbset.rs
- src/tcc0/dbgctrl.rs
- src/trng/ctrla.rs
- src/trng/evctrl.rs
- src/trng/intenclr.rs
- src/trng/intenset.rs
- src/trng/intflag.rs
- src/usb/device/ctrla.rs
- src/usb/device/dadd.rs
- src/usb/device/epcfg.rs
- src/usb/device/epintenclr.rs
- src/usb/device/epintenset.rs
- src/usb/device/epintflag.rs
- src/usb/device/epstatusclr.rs
- src/usb/device/epstatusset.rs
- src/usb/device/qosctrl.rs
- src/usb/host/binterval.rs
- src/usb/host/ctrla.rs
- src/usb/host/hsofc.rs
- src/usb/host/pcfg.rs
- src/usb/host/pintenclr.rs
- src/usb/host/pintenset.rs
- src/usb/host/pintflag.rs
- src/usb/host/pstatusclr.rs
- src/usb/host/pstatusset.rs
- src/usb/host/qosctrl.rs
- src/usb/host/status.rs
- src/wdt/clear.rs
- src/wdt/config.rs
- src/wdt/ctrla.rs
- src/wdt/ewctrl.rs
- src/wdt/intenclr.rs
- src/wdt/intenset.rs
- src/wdt/intflag.rs
- src/ac/compctrl.rs
- src/ac/evctrl.rs
- src/adc/calib.rs
- src/adc/ctrlc.rs
- src/adc/gaincorr.rs
- src/adc/inputctrl.rs
- src/adc/offsetcorr.rs
- src/adc/seqctrl.rs
- src/adc/winlt.rs
- src/adc/winut.rs
- src/aes/ciplen.rs
- src/aes/ctrla.rs
- src/aes/ghash.rs
- src/aes/hashkey.rs
- src/aes/indata.rs
- src/aes/intvectv.rs
- src/aes/keyword.rs
- src/aes/randseed.rs
- src/ccl/lutctrl.rs
- src/dac/dacctrl.rs
- src/dac/data.rs
- src/dac/databuf.rs
- src/dmac/baseaddr.rs
- src/dmac/chctrlb.rs
- src/dmac/crcchksum.rs
- src/dmac/crcctrl.rs
- src/dmac/crcdatain.rs
- src/dmac/ctrl.rs
- src/dmac/intpend.rs
- src/dmac/prictrl0.rs
- src/dmac/swtrigctrl.rs
- src/dmac/wrbaddr.rs
- src/dsu/addr.rs
- src/dsu/data.rs
- src/dsu/dcc.rs
- src/dsu/dcfg.rs
- src/dsu/length.rs
- src/eic/asynch.rs
- src/eic/config.rs
- src/eic/evctrl.rs
- src/eic/intenclr.rs
- src/eic/intenset.rs
- src/eic/intflag.rs
- src/eic/nmiflag.rs
- src/evsys/channel.rs
- src/evsys/intenclr.rs
- src/evsys/intenset.rs
- src/evsys/intflag.rs
- src/evsys/swevt.rs
- src/evsys/user.rs
- src/gclk/genctrl.rs
- src/gclk/pchctrl.rs
- src/mclk/ahbmask.rs
- src/mclk/apbamask.rs
- src/mclk/apbbmask.rs
- src/mclk/apbcmask.rs
- src/mclk/apbdmask.rs
- src/mclk/apbemask.rs
- src/mtb/claimclr.rs
- src/mtb/claimset.rs
- src/mtb/flow.rs
- src/mtb/itctrl.rs
- src/mtb/lockaccess.rs
- src/mtb/master.rs
- src/mtb/position.rs
- src/nvmctrl/addr.rs
- src/nvmctrl/ctrla.rs
- src/nvmctrl/ctrlb.rs
- src/nvmctrl/lock.rs
- src/nvmctrl/param.rs
- src/nvmctrl/status.rs
- src/opamp/opampctrl.rs
- src/osc32kctrl/intenclr.rs
- src/osc32kctrl/intenset.rs
- src/osc32kctrl/intflag.rs
- src/osc32kctrl/osc32k.rs
- src/osc32kctrl/osculp32k.rs
- src/osc32kctrl/rtcctrl.rs
- src/osc32kctrl/xosc32k.rs
- src/oscctrl/dfllctrl.rs
- src/oscctrl/dfllmul.rs
- src/oscctrl/dfllval.rs
- src/oscctrl/dpllctrlb.rs
- src/oscctrl/dpllratio.rs
- src/oscctrl/intenclr.rs
- src/oscctrl/intenset.rs
- src/oscctrl/intflag.rs
- src/oscctrl/xoscctrl.rs
- src/pac/intflaga.rs
- src/pac/intflagahb.rs
- src/pac/intflagb.rs
- src/pac/intflagc.rs
- src/pac/intflagd.rs
- src/pac/intflage.rs
- src/pac/wrctrl.rs
- src/pm/stdbycfg.rs
- src/port/ctrl.rs
- src/port/dir.rs
- src/port/dirclr.rs
- src/port/dirset.rs
- src/port/dirtgl.rs
- src/port/evctrl.rs
- src/port/out.rs
- src/port/outclr.rs
- src/port/outset.rs
- src/port/outtgl.rs
- src/port/wrconfig.rs
- src/rstc/wkcause.rs
- src/rstc/wken.rs
- src/rstc/wkpol.rs
- src/rtc/mode0/comp.rs
- src/rtc/mode0/count.rs
- src/rtc/mode0/ctrla.rs
- src/rtc/mode0/evctrl.rs
- src/rtc/mode0/gp.rs
- src/rtc/mode0/intenclr.rs
- src/rtc/mode0/intenset.rs
- src/rtc/mode0/intflag.rs
- src/rtc/mode1/comp.rs
- src/rtc/mode1/count.rs
- src/rtc/mode1/ctrla.rs
- src/rtc/mode1/evctrl.rs
- src/rtc/mode1/gp.rs
- src/rtc/mode1/intenclr.rs
- src/rtc/mode1/intenset.rs
- src/rtc/mode1/intflag.rs
- src/rtc/mode1/per.rs
- src/rtc/mode2/alarm.rs
- src/rtc/mode2/clock.rs
- src/rtc/mode2/ctrla.rs
- src/rtc/mode2/evctrl.rs
- src/rtc/mode2/gp.rs
- src/rtc/mode2/intenclr.rs
- src/rtc/mode2/intenset.rs
- src/rtc/mode2/intflag.rs
- src/sercom0/i2cm/addr.rs
- src/sercom0/i2cm/baud.rs
- src/sercom0/i2cm/ctrla.rs
- src/sercom0/i2cm/ctrlb.rs
- src/sercom0/i2cm/status.rs
- src/sercom0/i2cs/addr.rs
- src/sercom0/i2cs/ctrla.rs
- src/sercom0/i2cs/ctrlb.rs
- src/sercom0/i2cs/status.rs
- src/sercom0/spi/addr.rs
- src/sercom0/spi/ctrla.rs
- src/sercom0/spi/ctrlb.rs
- src/sercom0/spi/data.rs
- src/sercom0/spi/status.rs
- src/sercom0/usart/baud.rs
- src/sercom0/usart/baud_frac_mode.rs
- src/sercom0/usart/baud_fracfp_mode.rs
- src/sercom0/usart/baud_usartfp_mode.rs
- src/sercom0/usart/ctrla.rs
- src/sercom0/usart/ctrlb.rs
- src/sercom0/usart/data.rs
- src/sercom0/usart/status.rs
- src/supc/bbps.rs
- src/supc/bkout.rs
- src/supc/bod12.rs
- src/supc/bod33.rs
- src/supc/intenclr.rs
- src/supc/intenset.rs
- src/supc/intflag.rs
- src/supc/vref.rs
- src/supc/vreg.rs
- src/tc0/count16/cc.rs
- src/tc0/count16/ccbuf.rs
- src/tc0/count16/count.rs
- src/tc0/count16/ctrla.rs
- src/tc0/count16/evctrl.rs
- src/tc0/count32/cc.rs
- src/tc0/count32/ccbuf.rs
- src/tc0/count32/count.rs
- src/tc0/count32/ctrla.rs
- src/tc0/count32/evctrl.rs
- src/tc0/count8/ctrla.rs
- src/tc0/count8/evctrl.rs
- src/tcc0/cc.rs
- src/tcc0/cc_dith4.rs
- src/tcc0/cc_dith5.rs
- src/tcc0/cc_dith6.rs
- src/tcc0/ccbuf.rs
- src/tcc0/ccbuf_dith4.rs
- src/tcc0/ccbuf_dith5.rs
- src/tcc0/ccbuf_dith6.rs
- src/tcc0/count.rs
- src/tcc0/count_dith4.rs
- src/tcc0/count_dith5.rs
- src/tcc0/count_dith6.rs
- src/tcc0/ctrla.rs
- src/tcc0/drvctrl.rs
- src/tcc0/evctrl.rs
- src/tcc0/fctrla.rs
- src/tcc0/fctrlb.rs
- src/tcc0/intenclr.rs
- src/tcc0/intenset.rs
- src/tcc0/intflag.rs
- src/tcc0/patt.rs
- src/tcc0/pattbuf.rs
- src/tcc0/per.rs
- src/tcc0/per_dith4.rs
- src/tcc0/per_dith5.rs
- src/tcc0/per_dith6.rs
- src/tcc0/perbuf.rs
- src/tcc0/perbuf_dith4.rs
- src/tcc0/perbuf_dith5.rs
- src/tcc0/perbuf_dith6.rs
- src/tcc0/status.rs
- src/tcc0/wave.rs
- src/tcc0/wexctrl.rs
- src/usb/device/ctrlb.rs
- src/usb/device/descadd.rs
- src/usb/device/intenclr.rs
- src/usb/device/intenset.rs
- src/usb/device/intflag.rs
- src/usb/device/padcal.rs
- src/usb/host/ctrlb.rs
- src/usb/host/descadd.rs
- src/usb/host/fnum.rs
- src/usb/host/intenclr.rs
- src/usb/host/intenset.rs
- src/usb/host/intflag.rs
- src/usb/host/padcal.rs