pub struct RegisterBlock {Show 25 fields
pub isi_cfg1: Reg<ISI_CFG1_SPEC>,
pub isi_cfg2: Reg<ISI_CFG2_SPEC>,
pub isi_psize: Reg<ISI_PSIZE_SPEC>,
pub isi_pdecf: Reg<ISI_PDECF_SPEC>,
pub isi_y2r_set0: Reg<ISI_Y2R_SET0_SPEC>,
pub isi_y2r_set1: Reg<ISI_Y2R_SET1_SPEC>,
pub isi_r2y_set0: Reg<ISI_R2Y_SET0_SPEC>,
pub isi_r2y_set1: Reg<ISI_R2Y_SET1_SPEC>,
pub isi_r2y_set2: Reg<ISI_R2Y_SET2_SPEC>,
pub isi_cr: Reg<ISI_CR_SPEC>,
pub isi_sr: Reg<ISI_SR_SPEC>,
pub isi_ier: Reg<ISI_IER_SPEC>,
pub isi_idr: Reg<ISI_IDR_SPEC>,
pub isi_imr: Reg<ISI_IMR_SPEC>,
pub isi_dma_cher: Reg<ISI_DMA_CHER_SPEC>,
pub isi_dma_chdr: Reg<ISI_DMA_CHDR_SPEC>,
pub isi_dma_chsr: Reg<ISI_DMA_CHSR_SPEC>,
pub isi_dma_p_addr: Reg<ISI_DMA_P_ADDR_SPEC>,
pub isi_dma_p_ctrl: Reg<ISI_DMA_P_CTRL_SPEC>,
pub isi_dma_p_dscr: Reg<ISI_DMA_P_DSCR_SPEC>,
pub isi_dma_c_addr: Reg<ISI_DMA_C_ADDR_SPEC>,
pub isi_dma_c_ctrl: Reg<ISI_DMA_C_CTRL_SPEC>,
pub isi_dma_c_dscr: Reg<ISI_DMA_C_DSCR_SPEC>,
pub isi_wpmr: Reg<ISI_WPMR_SPEC>,
pub isi_wpsr: Reg<ISI_WPSR_SPEC>,
/* private fields */
}Expand description
Register block
Fields§
§isi_cfg1: Reg<ISI_CFG1_SPEC>0x00 - ISI Configuration 1 Register
isi_cfg2: Reg<ISI_CFG2_SPEC>0x04 - ISI Configuration 2 Register
isi_psize: Reg<ISI_PSIZE_SPEC>0x08 - ISI Preview Size Register
isi_pdecf: Reg<ISI_PDECF_SPEC>0x0c - ISI Preview Decimation Factor Register
isi_y2r_set0: Reg<ISI_Y2R_SET0_SPEC>0x10 - ISI Color Space Conversion YCrCb To RGB Set 0 Register
isi_y2r_set1: Reg<ISI_Y2R_SET1_SPEC>0x14 - ISI Color Space Conversion YCrCb To RGB Set 1 Register
isi_r2y_set0: Reg<ISI_R2Y_SET0_SPEC>0x18 - ISI Color Space Conversion RGB To YCrCb Set 0 Register
isi_r2y_set1: Reg<ISI_R2Y_SET1_SPEC>0x1c - ISI Color Space Conversion RGB To YCrCb Set 1 Register
isi_r2y_set2: Reg<ISI_R2Y_SET2_SPEC>0x20 - ISI Color Space Conversion RGB To YCrCb Set 2 Register
isi_cr: Reg<ISI_CR_SPEC>0x24 - ISI Control Register
isi_sr: Reg<ISI_SR_SPEC>0x28 - ISI Status Register
isi_ier: Reg<ISI_IER_SPEC>0x2c - ISI Interrupt Enable Register
isi_idr: Reg<ISI_IDR_SPEC>0x30 - ISI Interrupt Disable Register
isi_imr: Reg<ISI_IMR_SPEC>0x34 - ISI Interrupt Mask Register
isi_dma_cher: Reg<ISI_DMA_CHER_SPEC>0x38 - DMA Channel Enable Register
isi_dma_chdr: Reg<ISI_DMA_CHDR_SPEC>0x3c - DMA Channel Disable Register
isi_dma_chsr: Reg<ISI_DMA_CHSR_SPEC>0x40 - DMA Channel Status Register
isi_dma_p_addr: Reg<ISI_DMA_P_ADDR_SPEC>0x44 - DMA Preview Base Address Register
isi_dma_p_ctrl: Reg<ISI_DMA_P_CTRL_SPEC>0x48 - DMA Preview Control Register
isi_dma_p_dscr: Reg<ISI_DMA_P_DSCR_SPEC>0x4c - DMA Preview Descriptor Address Register
isi_dma_c_addr: Reg<ISI_DMA_C_ADDR_SPEC>0x50 - DMA Codec Base Address Register
isi_dma_c_ctrl: Reg<ISI_DMA_C_CTRL_SPEC>0x54 - DMA Codec Control Register
isi_dma_c_dscr: Reg<ISI_DMA_C_DSCR_SPEC>0x58 - DMA Codec Descriptor Address Register
isi_wpmr: Reg<ISI_WPMR_SPEC>0xe4 - Write Protection Mode Register
isi_wpsr: Reg<ISI_WPSR_SPEC>0xe8 - Write Protection Status Register