Struct atsame70n21_pac::usbhs::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 43 fields
pub devctrl: Reg<DEVCTRL_SPEC>,
pub devisr: Reg<DEVISR_SPEC>,
pub devicr: Reg<DEVICR_SPEC>,
pub devifr: Reg<DEVIFR_SPEC>,
pub devimr: Reg<DEVIMR_SPEC>,
pub devidr: Reg<DEVIDR_SPEC>,
pub devier: Reg<DEVIER_SPEC>,
pub devept: Reg<DEVEPT_SPEC>,
pub devfnum: Reg<DEVFNUM_SPEC>,
pub deveptcfg: [Reg<DEVEPTCFG_SPEC>; 10],
pub deveptisr: [Reg<DEVEPTISR_SPEC>; 10],
pub devepticr: [Reg<DEVEPTICR_SPEC>; 10],
pub deveptifr: [Reg<DEVEPTIFR_SPEC>; 10],
pub deveptimr: [Reg<DEVEPTIMR_SPEC>; 10],
pub deveptier: [Reg<DEVEPTIER_SPEC>; 10],
pub deveptidr: [Reg<DEVEPTIDR_SPEC>; 10],
pub usbhs_devdma: [USBHS_DEVDMA; 7],
pub hstctrl: Reg<HSTCTRL_SPEC>,
pub hstisr: Reg<HSTISR_SPEC>,
pub hsticr: Reg<HSTICR_SPEC>,
pub hstifr: Reg<HSTIFR_SPEC>,
pub hstimr: Reg<HSTIMR_SPEC>,
pub hstidr: Reg<HSTIDR_SPEC>,
pub hstier: Reg<HSTIER_SPEC>,
pub hstpip: Reg<HSTPIP_SPEC>,
pub hstfnum: Reg<HSTFNUM_SPEC>,
pub hstaddr1: Reg<HSTADDR1_SPEC>,
pub hstaddr2: Reg<HSTADDR2_SPEC>,
pub hstaddr3: Reg<HSTADDR3_SPEC>,
pub hstpipcfg: [Reg<HSTPIPCFG_SPEC>; 10],
pub hstpipisr: [Reg<HSTPIPISR_SPEC>; 10],
pub hstpipicr: [Reg<HSTPIPICR_SPEC>; 10],
pub hstpipifr: [Reg<HSTPIPIFR_SPEC>; 10],
pub hstpipimr: [Reg<HSTPIPIMR_SPEC>; 10],
pub hstpipier: [Reg<HSTPIPIER_SPEC>; 10],
pub hstpipidr: [Reg<HSTPIPIDR_SPEC>; 10],
pub hstpipinrq: [Reg<HSTPIPINRQ_SPEC>; 10],
pub hstpiperr: [Reg<HSTPIPERR_SPEC>; 10],
pub usbhs_hstdma: [USBHS_HSTDMA; 7],
pub ctrl: Reg<CTRL_SPEC>,
pub sr: Reg<SR_SPEC>,
pub scr: Reg<SCR_SPEC>,
pub sfr: Reg<SFR_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
devctrl: Reg<DEVCTRL_SPEC>
0x00 - Device General Control Register
devisr: Reg<DEVISR_SPEC>
0x04 - Device Global Interrupt Status Register
devicr: Reg<DEVICR_SPEC>
0x08 - Device Global Interrupt Clear Register
devifr: Reg<DEVIFR_SPEC>
0x0c - Device Global Interrupt Set Register
devimr: Reg<DEVIMR_SPEC>
0x10 - Device Global Interrupt Mask Register
devidr: Reg<DEVIDR_SPEC>
0x14 - Device Global Interrupt Disable Register
devier: Reg<DEVIER_SPEC>
0x18 - Device Global Interrupt Enable Register
devept: Reg<DEVEPT_SPEC>
0x1c - Device Endpoint Register
devfnum: Reg<DEVFNUM_SPEC>
0x20 - Device Frame Number Register
deveptcfg: [Reg<DEVEPTCFG_SPEC>; 10]
0x100..0x128 - Device Endpoint Configuration Register (n = 0) 0
deveptisr: [Reg<DEVEPTISR_SPEC>; 10]
0x130..0x158 - Device Endpoint Status Register (n = 0) 0
devepticr: [Reg<DEVEPTICR_SPEC>; 10]
0x160..0x188 - Device Endpoint Clear Register (n = 0) 0
deveptifr: [Reg<DEVEPTIFR_SPEC>; 10]
0x190..0x1b8 - Device Endpoint Set Register (n = 0) 0
deveptimr: [Reg<DEVEPTIMR_SPEC>; 10]
0x1c0..0x1e8 - Device Endpoint Mask Register (n = 0) 0
deveptier: [Reg<DEVEPTIER_SPEC>; 10]
0x1f0..0x218 - Device Endpoint Enable Register (n = 0) 0
deveptidr: [Reg<DEVEPTIDR_SPEC>; 10]
0x220..0x248 - Device Endpoint Disable Register (n = 0) 0
usbhs_devdma: [USBHS_DEVDMA; 7]
0x310..0x380 - Device DMA Channel Next Descriptor Address Register (n = 1)
hstctrl: Reg<HSTCTRL_SPEC>
0x400 - Host General Control Register
hstisr: Reg<HSTISR_SPEC>
0x404 - Host Global Interrupt Status Register
hsticr: Reg<HSTICR_SPEC>
0x408 - Host Global Interrupt Clear Register
hstifr: Reg<HSTIFR_SPEC>
0x40c - Host Global Interrupt Set Register
hstimr: Reg<HSTIMR_SPEC>
0x410 - Host Global Interrupt Mask Register
hstidr: Reg<HSTIDR_SPEC>
0x414 - Host Global Interrupt Disable Register
hstier: Reg<HSTIER_SPEC>
0x418 - Host Global Interrupt Enable Register
hstpip: Reg<HSTPIP_SPEC>
0x41c - Host Pipe Register
hstfnum: Reg<HSTFNUM_SPEC>
0x420 - Host Frame Number Register
hstaddr1: Reg<HSTADDR1_SPEC>
0x424 - Host Address 1 Register
hstaddr2: Reg<HSTADDR2_SPEC>
0x428 - Host Address 2 Register
hstaddr3: Reg<HSTADDR3_SPEC>
0x42c - Host Address 3 Register
hstpipcfg: [Reg<HSTPIPCFG_SPEC>; 10]
0x500..0x528 - Host Pipe Configuration Register (n = 0) 0
hstpipisr: [Reg<HSTPIPISR_SPEC>; 10]
0x530..0x558 - Host Pipe Status Register (n = 0) 0
hstpipicr: [Reg<HSTPIPICR_SPEC>; 10]
0x560..0x588 - Host Pipe Clear Register (n = 0) 0
hstpipifr: [Reg<HSTPIPIFR_SPEC>; 10]
0x590..0x5b8 - Host Pipe Set Register (n = 0) 0
hstpipimr: [Reg<HSTPIPIMR_SPEC>; 10]
0x5c0..0x5e8 - Host Pipe Mask Register (n = 0) 0
hstpipier: [Reg<HSTPIPIER_SPEC>; 10]
0x5f0..0x618 - Host Pipe Enable Register (n = 0) 0
hstpipidr: [Reg<HSTPIPIDR_SPEC>; 10]
0x620..0x648 - Host Pipe Disable Register (n = 0) 0
hstpipinrq: [Reg<HSTPIPINRQ_SPEC>; 10]
0x650..0x678 - Host Pipe IN Request Register (n = 0) 0
hstpiperr: [Reg<HSTPIPERR_SPEC>; 10]
0x680..0x6a8 - Host Pipe Error Register (n = 0) 0
usbhs_hstdma: [USBHS_HSTDMA; 7]
0x710..0x780 - Host DMA Channel Next Descriptor Address Register (n = 1)
ctrl: Reg<CTRL_SPEC>
0x800 - General Control Register
sr: Reg<SR_SPEC>
0x804 - General Status Register
scr: Reg<SCR_SPEC>
0x808 - General Status Clear Register
sfr: Reg<SFR_SPEC>
0x80c - General Status Set Register