[−][src]Type Definition atsame70j21b::mcan0::mcan_ils::W
type W = W<u32, MCAN_ILS>;
Writer for register MCAN_ILS
Implementations
impl W
[src]
pub fn rf0nl(&mut self) -> RF0NL_W
[src]
Bit 0 - Receive FIFO 0 New Message Interrupt Line
pub fn rf0wl(&mut self) -> RF0WL_W
[src]
Bit 1 - Receive FIFO 0 Watermark Reached Interrupt Line
pub fn rf0fl(&mut self) -> RF0FL_W
[src]
Bit 2 - Receive FIFO 0 Full Interrupt Line
pub fn rf0ll(&mut self) -> RF0LL_W
[src]
Bit 3 - Receive FIFO 0 Message Lost Interrupt Line
pub fn rf1nl(&mut self) -> RF1NL_W
[src]
Bit 4 - Receive FIFO 1 New Message Interrupt Line
pub fn rf1wl(&mut self) -> RF1WL_W
[src]
Bit 5 - Receive FIFO 1 Watermark Reached Interrupt Line
pub fn rf1fl(&mut self) -> RF1FL_W
[src]
Bit 6 - Receive FIFO 1 Full Interrupt Line
pub fn rf1ll(&mut self) -> RF1LL_W
[src]
Bit 7 - Receive FIFO 1 Message Lost Interrupt Line
pub fn hpml(&mut self) -> HPML_W
[src]
Bit 8 - High Priority Message Interrupt Line
pub fn tcl(&mut self) -> TCL_W
[src]
Bit 9 - Transmission Completed Interrupt Line
pub fn tcfl(&mut self) -> TCFL_W
[src]
Bit 10 - Transmission Cancellation Finished Interrupt Line
pub fn tfel(&mut self) -> TFEL_W
[src]
Bit 11 - Tx FIFO Empty Interrupt Line
pub fn tefnl(&mut self) -> TEFNL_W
[src]
Bit 12 - Tx Event FIFO New Entry Interrupt Line
pub fn tefwl(&mut self) -> TEFWL_W
[src]
Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line
pub fn teffl(&mut self) -> TEFFL_W
[src]
Bit 14 - Tx Event FIFO Full Interrupt Line
pub fn tefll(&mut self) -> TEFLL_W
[src]
Bit 15 - Tx Event FIFO Event Lost Interrupt Line
pub fn tswl(&mut self) -> TSWL_W
[src]
Bit 16 - Timestamp Wraparound Interrupt Line
pub fn mrafl(&mut self) -> MRAFL_W
[src]
Bit 17 - Message RAM Access Failure Interrupt Line
pub fn tool(&mut self) -> TOOL_W
[src]
Bit 18 - Timeout Occurred Interrupt Line
pub fn drxl(&mut self) -> DRXL_W
[src]
Bit 19 - Message stored to Dedicated Receive Buffer Interrupt Line
pub fn elol(&mut self) -> ELOL_W
[src]
Bit 22 - Error Logging Overflow Interrupt Line
pub fn epl(&mut self) -> EPL_W
[src]
Bit 23 - Error Passive Interrupt Line
pub fn ewl(&mut self) -> EWL_W
[src]
Bit 24 - Warning Status Interrupt Line
pub fn bol(&mut self) -> BOL_W
[src]
Bit 25 - Bus_Off Status Interrupt Line
pub fn wdil(&mut self) -> WDIL_W
[src]
Bit 26 - Watchdog Interrupt Line
pub fn peal(&mut self) -> PEAL_W
[src]
Bit 27 - Protocol Error in Arbitration Phase Line
pub fn pedl(&mut self) -> PEDL_W
[src]
Bit 28 - Protocol Error in Data Phase Line
pub fn aral(&mut self) -> ARAL_W
[src]
Bit 29 - Access to Reserved Address Line