[][src]Type Definition atsame70j21b::isi::isi_cfg1::W

type W = W<u32, ISI_CFG1>;

Writer for register ISI_CFG1

Implementations

impl W[src]

pub fn hsync_pol(&mut self) -> HSYNC_POL_W[src]

Bit 2 - Horizontal Synchronization Polarity

pub fn vsync_pol(&mut self) -> VSYNC_POL_W[src]

Bit 3 - Vertical Synchronization Polarity

pub fn pixclk_pol(&mut self) -> PIXCLK_POL_W[src]

Bit 4 - Pixel Clock Polarity

pub fn grayle(&mut self) -> GRAYLE_W[src]

Bit 5 - Grayscale Little Endian

pub fn emb_sync(&mut self) -> EMB_SYNC_W[src]

Bit 6 - Embedded Synchronization

pub fn crc_sync(&mut self) -> CRC_SYNC_W[src]

Bit 7 - Embedded Synchronization Correction

pub fn frate(&mut self) -> FRATE_W[src]

Bits 8:10 - Frame Rate [0..7]

pub fn discr(&mut self) -> DISCR_W[src]

Bit 11 - Disable Codec Request

pub fn full(&mut self) -> FULL_W[src]

Bit 12 - Full Mode is Allowed

pub fn thmask(&mut self) -> THMASK_W[src]

Bits 13:14 - Threshold Mask

pub fn sld(&mut self) -> SLD_W[src]

Bits 16:23 - Start of Line Delay

pub fn sfd(&mut self) -> SFD_W[src]

Bits 24:31 - Start of Frame Delay