[][src]Type Definition atsame70j19b::pwm0::pwm_clk::R

type R = R<u32, PWM_CLK>;

Reader of register PWM_CLK

Implementations

impl R[src]

pub fn diva(&self) -> DIVA_R[src]

Bits 0:7 - CLKA Divide Factor

pub fn prea(&self) -> PREA_R[src]

Bits 8:11 - CLKA Source Clock Selection

pub fn divb(&self) -> DIVB_R[src]

Bits 16:23 - CLKB Divide Factor

pub fn preb(&self) -> PREB_R[src]

Bits 24:27 - CLKB Source Clock Selection