Struct atsame54p19a_pac::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer.

Used as an argument to the closures in the write and modify methods of the register.

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register.

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

impl W<u8, Reg<u8, _CTRLB>>

pub fn start0(&mut self) -> START0_W<'_>

Bit 0 - Comparator 0 Start Comparison

pub fn start1(&mut self) -> START1_W<'_>

Bit 1 - Comparator 1 Start Comparison

impl W<u16, Reg<u16, _EVCTRL>>

pub fn compeo0(&mut self) -> COMPEO0_W<'_>

Bit 0 - Comparator 0 Event Output Enable

pub fn compeo1(&mut self) -> COMPEO1_W<'_>

Bit 1 - Comparator 1 Event Output Enable

pub fn wineo0(&mut self) -> WINEO0_W<'_>

Bit 4 - Window 0 Event Output Enable

pub fn compei0(&mut self) -> COMPEI0_W<'_>

Bit 8 - Comparator 0 Event Input Enable

pub fn compei1(&mut self) -> COMPEI1_W<'_>

Bit 9 - Comparator 1 Event Input Enable

pub fn invei0(&mut self) -> INVEI0_W<'_>

Bit 12 - Comparator 0 Input Event Invert Enable

pub fn invei1(&mut self) -> INVEI1_W<'_>

Bit 13 - Comparator 1 Input Event Invert Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1 Interrupt Enable

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0 Interrupt Enable

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1 Interrupt Enable

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bit 0 - Comparator 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bit 1 - Comparator 1

pub fn win0(&mut self) -> WIN0_W<'_>

Bit 4 - Window 0

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u8, Reg<u8, _WINCTRL>>

pub fn wen0(&mut self) -> WEN0_W<'_>

Bit 0 - Window 0 Mode Enable

pub fn wintsel0(&mut self) -> WINTSEL0_W<'_>

Bits 1:2 - Window 0 Interrupt Selection

impl W<u8, Reg<u8, _SCALER>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:5 - Scaler Value

impl W<u32, Reg<u32, _COMPCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn single(&mut self) -> SINGLE_W<'_>

Bit 2 - Single-Shot Mode

pub fn intsel(&mut self) -> INTSEL_W<'_>

Bits 3:4 - Interrupt Selection

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn muxneg(&mut self) -> MUXNEG_W<'_>

Bits 8:10 - Negative Input Mux Selection

pub fn muxpos(&mut self) -> MUXPOS_W<'_>

Bits 12:14 - Positive Input Mux Selection

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap Inputs and Invert

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 16:17 - Speed Selection

pub fn hysten(&mut self) -> HYSTEN_W<'_>

Bit 19 - Hysteresis Enable

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 20:21 - Hysteresis Level

pub fn flen(&mut self) -> FLEN_W<'_>

Bits 24:26 - Filter Length

pub fn out(&mut self) -> OUT_W<'_>

Bits 28:29 - Output

impl W<u16, Reg<u16, _CALIB>>

pub fn bias0(&mut self) -> BIAS0_W<'_>

Bits 0:1 - COMP0/1 Bias Scaling

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn dualsel(&mut self) -> DUALSEL_W<'_>

Bits 3:4 - Dual Mode Trigger Selection

pub fn slaveen(&mut self) -> SLAVEEN_W<'_>

Bit 5 - Slave Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler Configuration

pub fn r2r(&mut self) -> R2R_W<'_>

Bit 15 - Rail to Rail Operation Enable

impl W<u8, Reg<u8, _EVCTRL>>

pub fn flushei(&mut self) -> FLUSHEI_W<'_>

Bit 0 - Flush Event Input Enable

pub fn startei(&mut self) -> STARTEI_W<'_>

Bit 1 - Start Conversion Event Input Enable

pub fn flushinv(&mut self) -> FLUSHINV_W<'_>

Bit 2 - Flush Event Invert Enable

pub fn startinv(&mut self) -> STARTINV_W<'_>

Bit 3 - Start Conversion Event Invert Enable

pub fn resrdyeo(&mut self) -> RESRDYEO_W<'_>

Bit 4 - Result Ready Event Out

pub fn winmoneo(&mut self) -> WINMONEO_W<'_>

Bit 5 - Window Monitor Event Out

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u16, Reg<u16, _INPUTCTRL>>

pub fn muxpos(&mut self) -> MUXPOS_W<'_>

Bits 0:4 - Positive Mux Input Selection

pub fn diffmode(&mut self) -> DIFFMODE_W<'_>

Bit 7 - Differential Mode

pub fn muxneg(&mut self) -> MUXNEG_W<'_>

Bits 8:12 - Negative Mux Input Selection

pub fn dseqstop(&mut self) -> DSEQSTOP_W<'_>

Bit 15 - Stop DMA Sequencing

impl W<u16, Reg<u16, _CTRLB>>

pub fn leftadj(&mut self) -> LEFTADJ_W<'_>

Bit 0 - Left-Adjusted Result

pub fn freerun(&mut self) -> FREERUN_W<'_>

Bit 1 - Free Running Mode

pub fn corren(&mut self) -> CORREN_W<'_>

Bit 2 - Digital Correction Logic Enable

pub fn ressel(&mut self) -> RESSEL_W<'_>

Bits 3:4 - Conversion Result Resolution

pub fn winmode(&mut self) -> WINMODE_W<'_>

Bits 8:10 - Window Monitor Mode

pub fn winss(&mut self) -> WINSS_W<'_>

Bit 11 - Window Single Sample

impl W<u8, Reg<u8, _REFCTRL>>

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 0:3 - Reference Selection

pub fn refcomp(&mut self) -> REFCOMP_W<'_>

Bit 7 - Reference Buffer Offset Compensation Enable

impl W<u8, Reg<u8, _AVGCTRL>>

pub fn samplenum(&mut self) -> SAMPLENUM_W<'_>

Bits 0:3 - Number of Samples to be Collected

pub fn adjres(&mut self) -> ADJRES_W<'_>

Bits 4:6 - Adjusting Result / Division Coefficient

impl W<u8, Reg<u8, _SAMPCTRL>>

pub fn samplen(&mut self) -> SAMPLEN_W<'_>

Bits 0:5 - Sampling Time Length

pub fn offcomp(&mut self) -> OFFCOMP_W<'_>

Bit 7 - Comparator Offset Compensation Enable

impl W<u16, Reg<u16, _WINLT>>

pub fn winlt(&mut self) -> WINLT_W<'_>

Bits 0:15 - Window Lower Threshold

impl W<u16, Reg<u16, _WINUT>>

pub fn winut(&mut self) -> WINUT_W<'_>

Bits 0:15 - Window Upper Threshold

impl W<u16, Reg<u16, _GAINCORR>>

pub fn gaincorr(&mut self) -> GAINCORR_W<'_>

Bits 0:11 - Gain Correction Value

impl W<u16, Reg<u16, _OFFSETCORR>>

pub fn offsetcorr(&mut self) -> OFFSETCORR_W<'_>

Bits 0:11 - Offset Correction Value

impl W<u8, Reg<u8, _SWTRIG>>

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 0 - ADC Conversion Flush

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start ADC Conversion

impl W<u8, Reg<u8, _INTENCLR>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready Interrupt Disable

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun Interrupt Disable

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready Interrupt Enable

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun Interrupt Enable

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn resrdy(&mut self) -> RESRDY_W<'_>

Bit 0 - Result Ready Interrupt Flag

pub fn overrun(&mut self) -> OVERRUN_W<'_>

Bit 1 - Overrun Interrupt Flag

pub fn winmon(&mut self) -> WINMON_W<'_>

Bit 2 - Window Monitor Interrupt Flag

impl W<u32, Reg<u32, _DSEQDATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - DMA Sequential Data

impl W<u32, Reg<u32, _DSEQCTRL>>

pub fn inputctrl(&mut self) -> INPUTCTRL_W<'_>

Bit 0 - Input Control

pub fn ctrlb(&mut self) -> CTRLB_W<'_>

Bit 1 - Control B

pub fn refctrl(&mut self) -> REFCTRL_W<'_>

Bit 2 - Reference Control

pub fn avgctrl(&mut self) -> AVGCTRL_W<'_>

Bit 3 - Average Control

pub fn sampctrl(&mut self) -> SAMPCTRL_W<'_>

Bit 4 - Sampling Time Control

pub fn winlt(&mut self) -> WINLT_W<'_>

Bit 5 - Window Monitor Lower Threshold

pub fn winut(&mut self) -> WINUT_W<'_>

Bit 6 - Window Monitor Upper Threshold

pub fn gaincorr(&mut self) -> GAINCORR_W<'_>

Bit 7 - Gain Correction

pub fn offsetcorr(&mut self) -> OFFSETCORR_W<'_>

Bit 8 - Offset Correction

pub fn autostart(&mut self) -> AUTOSTART_W<'_>

Bit 31 - ADC Auto-Start Conversion

impl W<u16, Reg<u16, _CALIB>>

pub fn biascomp(&mut self) -> BIASCOMP_W<'_>

Bits 0:2 - Bias Comparator Scaling

pub fn biasr2r(&mut self) -> BIASR2R_W<'_>

Bits 4:6 - Bias R2R Ampli scaling

pub fn biasrefbuf(&mut self) -> BIASREFBUF_W<'_>

Bits 8:10 - Bias Reference Buffer Scaling

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn aesmode(&mut self) -> AESMODE_W<'_>

Bits 2:4 - AES Modes of operation

pub fn cfbs(&mut self) -> CFBS_W<'_>

Bits 5:7 - Cipher Feedback Block Size

pub fn keysize(&mut self) -> KEYSIZE_W<'_>

Bits 8:9 - Encryption Key Size

pub fn cipher(&mut self) -> CIPHER_W<'_>

Bit 10 - Cipher Mode

pub fn startmode(&mut self) -> STARTMODE_W<'_>

Bit 11 - Start Mode Select

pub fn lod(&mut self) -> LOD_W<'_>

Bit 12 - Last Output Data Mode

pub fn keygen(&mut self) -> KEYGEN_W<'_>

Bit 13 - Last Key Generation

pub fn xorkey(&mut self) -> XORKEY_W<'_>

Bit 14 - XOR Key Operation

pub fn ctype(&mut self) -> CTYPE_W<'_>

Bits 16:19 - Counter Measure Type

impl W<u8, Reg<u8, _CTRLB>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Encryption/Decryption

pub fn newmsg(&mut self) -> NEWMSG_W<'_>

Bit 1 - New message

pub fn eom(&mut self) -> EOM_W<'_>

Bit 2 - End of message

pub fn gfmul(&mut self) -> GFMUL_W<'_>

Bit 3 - GF Multiplication

impl W<u8, Reg<u8, _INTENCLR>>

pub fn enccmp(&mut self) -> ENCCMP_W<'_>

Bit 0 - Encryption Complete Interrupt Enable

pub fn gfmcmp(&mut self) -> GFMCMP_W<'_>

Bit 1 - GF Multiplication Complete Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn enccmp(&mut self) -> ENCCMP_W<'_>

Bit 0 - Encryption Complete Interrupt Enable

pub fn gfmcmp(&mut self) -> GFMCMP_W<'_>

Bit 1 - GF Multiplication Complete Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn enccmp(&mut self) -> ENCCMP_W<'_>

Bit 0 - Encryption Complete

pub fn gfmcmp(&mut self) -> GFMCMP_W<'_>

Bit 1 - GF Multiplication Complete

impl W<u8, Reg<u8, _DATABUFPTR>>

pub fn indataptr(&mut self) -> INDATAPTR_W<'_>

Bits 0:1 - Input Data Pointer

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u32, Reg<u32, _MRCFG>>

pub fn qos(&mut self) -> QOS_W<'_>

Bits 0:1 - Quality of Service

impl W<u32, Reg<u32, _DBTP>>

pub fn dsjw(&mut self) -> DSJW_W<'_>

Bits 0:3 - Data (Re)Synchronization Jump Width

pub fn dtseg2(&mut self) -> DTSEG2_W<'_>

Bits 4:7 - Data time segment after sample point

pub fn dtseg1(&mut self) -> DTSEG1_W<'_>

Bits 8:12 - Data time segment before sample point

pub fn dbrp(&mut self) -> DBRP_W<'_>

Bits 16:20 - Data Baud Rate Prescaler

pub fn tdc(&mut self) -> TDC_W<'_>

Bit 23 - Tranceiver Delay Compensation

impl W<u32, Reg<u32, _TEST>>

pub fn lbck(&mut self) -> LBCK_W<'_>

Bit 4 - Loop Back Mode

pub fn tx(&mut self) -> TX_W<'_>

Bits 5:6 - Control of Transmit Pin

pub fn rx(&mut self) -> RX_W<'_>

Bit 7 - Receive Pin

impl W<u32, Reg<u32, _RWD>>

pub fn wdc(&mut self) -> WDC_W<'_>

Bits 0:7 - Watchdog Configuration

pub fn wdv(&mut self) -> WDV_W<'_>

Bits 8:15 - Watchdog Value

impl W<u32, Reg<u32, _CCCR>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialization

pub fn cce(&mut self) -> CCE_W<'_>

Bit 1 - Configuration Change Enable

pub fn asm(&mut self) -> ASM_W<'_>

Bit 2 - ASM Restricted Operation Mode

pub fn csa(&mut self) -> CSA_W<'_>

Bit 3 - Clock Stop Acknowledge

pub fn csr(&mut self) -> CSR_W<'_>

Bit 4 - Clock Stop Request

pub fn mon(&mut self) -> MON_W<'_>

Bit 5 - Bus Monitoring Mode

pub fn dar(&mut self) -> DAR_W<'_>

Bit 6 - Disable Automatic Retransmission

pub fn test(&mut self) -> TEST_W<'_>

Bit 7 - Test Mode Enable

pub fn fdoe(&mut self) -> FDOE_W<'_>

Bit 8 - FD Operation Enable

pub fn brse(&mut self) -> BRSE_W<'_>

Bit 9 - Bit Rate Switch Enable

pub fn pxhd(&mut self) -> PXHD_W<'_>

Bit 12 - Protocol Exception Handling Disable

pub fn efbi(&mut self) -> EFBI_W<'_>

Bit 13 - Edge Filtering during Bus Integration

pub fn txp(&mut self) -> TXP_W<'_>

Bit 14 - Transmit Pause

impl W<u32, Reg<u32, _NBTP>>

pub fn ntseg2(&mut self) -> NTSEG2_W<'_>

Bits 0:6 - Nominal Time segment after sample point

pub fn ntseg1(&mut self) -> NTSEG1_W<'_>

Bits 8:15 - Nominal Time segment before sample point

pub fn nbrp(&mut self) -> NBRP_W<'_>

Bits 16:24 - Nominal Baud Rate Prescaler

pub fn nsjw(&mut self) -> NSJW_W<'_>

Bits 25:31 - Nominal (Re)Synchronization Jump Width

impl W<u32, Reg<u32, _TSCC>>

pub fn tss(&mut self) -> TSS_W<'_>

Bits 0:1 - Timestamp Select

pub fn tcp(&mut self) -> TCP_W<'_>

Bits 16:19 - Timestamp Counter Prescaler

impl W<u32, Reg<u32, _TOCC>>

pub fn etoc(&mut self) -> ETOC_W<'_>

Bit 0 - Enable Timeout Counter

pub fn tos(&mut self) -> TOS_W<'_>

Bits 1:2 - Timeout Select

pub fn top(&mut self) -> TOP_W<'_>

Bits 16:31 - Timeout Period

impl W<u32, Reg<u32, _TOCV>>

pub fn toc(&mut self) -> TOC_W<'_>

Bits 0:15 - Timeout Counter

impl W<u32, Reg<u32, _TDCR>>

pub fn tdcf(&mut self) -> TDCF_W<'_>

Bits 0:6 - Transmitter Delay Compensation Filter Length

pub fn tdco(&mut self) -> TDCO_W<'_>

Bits 8:14 - Transmitter Delay Compensation Offset

impl W<u32, Reg<u32, _IR>>

pub fn rf0n(&mut self) -> RF0N_W<'_>

Bit 0 - Rx FIFO 0 New Message

pub fn rf0w(&mut self) -> RF0W_W<'_>

Bit 1 - Rx FIFO 0 Watermark Reached

pub fn rf0f(&mut self) -> RF0F_W<'_>

Bit 2 - Rx FIFO 0 Full

pub fn rf0l(&mut self) -> RF0L_W<'_>

Bit 3 - Rx FIFO 0 Message Lost

pub fn rf1n(&mut self) -> RF1N_W<'_>

Bit 4 - Rx FIFO 1 New Message

pub fn rf1w(&mut self) -> RF1W_W<'_>

Bit 5 - Rx FIFO 1 Watermark Reached

pub fn rf1f(&mut self) -> RF1F_W<'_>

Bit 6 - Rx FIFO 1 FIFO Full

pub fn rf1l(&mut self) -> RF1L_W<'_>

Bit 7 - Rx FIFO 1 Message Lost

pub fn hpm(&mut self) -> HPM_W<'_>

Bit 8 - High Priority Message

pub fn tc(&mut self) -> TC_W<'_>

Bit 9 - Timestamp Completed

pub fn tcf(&mut self) -> TCF_W<'_>

Bit 10 - Transmission Cancellation Finished

pub fn tfe(&mut self) -> TFE_W<'_>

Bit 11 - Tx FIFO Empty

pub fn tefn(&mut self) -> TEFN_W<'_>

Bit 12 - Tx Event FIFO New Entry

pub fn tefw(&mut self) -> TEFW_W<'_>

Bit 13 - Tx Event FIFO Watermark Reached

pub fn teff(&mut self) -> TEFF_W<'_>

Bit 14 - Tx Event FIFO Full

pub fn tefl(&mut self) -> TEFL_W<'_>

Bit 15 - Tx Event FIFO Element Lost

pub fn tsw(&mut self) -> TSW_W<'_>

Bit 16 - Timestamp Wraparound

pub fn mraf(&mut self) -> MRAF_W<'_>

Bit 17 - Message RAM Access Failure

pub fn too(&mut self) -> TOO_W<'_>

Bit 18 - Timeout Occurred

pub fn drx(&mut self) -> DRX_W<'_>

Bit 19 - Message stored to Dedicated Rx Buffer

pub fn bec(&mut self) -> BEC_W<'_>

Bit 20 - Bit Error Corrected

pub fn beu(&mut self) -> BEU_W<'_>

Bit 21 - Bit Error Uncorrected

pub fn elo(&mut self) -> ELO_W<'_>

Bit 22 - Error Logging Overflow

pub fn ep(&mut self) -> EP_W<'_>

Bit 23 - Error Passive

pub fn ew(&mut self) -> EW_W<'_>

Bit 24 - Warning Status

pub fn bo(&mut self) -> BO_W<'_>

Bit 25 - Bus_Off Status

pub fn wdi(&mut self) -> WDI_W<'_>

Bit 26 - Watchdog Interrupt

pub fn pea(&mut self) -> PEA_W<'_>

Bit 27 - Protocol Error in Arbitration Phase

pub fn ped(&mut self) -> PED_W<'_>

Bit 28 - Protocol Error in Data Phase

pub fn ara(&mut self) -> ARA_W<'_>

Bit 29 - Access to Reserved Address

impl W<u32, Reg<u32, _IE>>

pub fn rf0ne(&mut self) -> RF0NE_W<'_>

Bit 0 - Rx FIFO 0 New Message Interrupt Enable

pub fn rf0we(&mut self) -> RF0WE_W<'_>

Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable

pub fn rf0fe(&mut self) -> RF0FE_W<'_>

Bit 2 - Rx FIFO 0 Full Interrupt Enable

pub fn rf0le(&mut self) -> RF0LE_W<'_>

Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable

pub fn rf1ne(&mut self) -> RF1NE_W<'_>

Bit 4 - Rx FIFO 1 New Message Interrupt Enable

pub fn rf1we(&mut self) -> RF1WE_W<'_>

Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable

pub fn rf1fe(&mut self) -> RF1FE_W<'_>

Bit 6 - Rx FIFO 1 FIFO Full Interrupt Enable

pub fn rf1le(&mut self) -> RF1LE_W<'_>

Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable

pub fn hpme(&mut self) -> HPME_W<'_>

Bit 8 - High Priority Message Interrupt Enable

pub fn tce(&mut self) -> TCE_W<'_>

Bit 9 - Timestamp Completed Interrupt Enable

pub fn tcfe(&mut self) -> TCFE_W<'_>

Bit 10 - Transmission Cancellation Finished Interrupt Enable

pub fn tfee(&mut self) -> TFEE_W<'_>

Bit 11 - Tx FIFO Empty Interrupt Enable

pub fn tefne(&mut self) -> TEFNE_W<'_>

Bit 12 - Tx Event FIFO New Entry Interrupt Enable

pub fn tefwe(&mut self) -> TEFWE_W<'_>

Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable

pub fn teffe(&mut self) -> TEFFE_W<'_>

Bit 14 - Tx Event FIFO Full Interrupt Enable

pub fn tefle(&mut self) -> TEFLE_W<'_>

Bit 15 - Tx Event FIFO Element Lost Interrupt Enable

pub fn tswe(&mut self) -> TSWE_W<'_>

Bit 16 - Timestamp Wraparound Interrupt Enable

pub fn mrafe(&mut self) -> MRAFE_W<'_>

Bit 17 - Message RAM Access Failure Interrupt Enable

pub fn tooe(&mut self) -> TOOE_W<'_>

Bit 18 - Timeout Occurred Interrupt Enable

pub fn drxe(&mut self) -> DRXE_W<'_>

Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable

pub fn bece(&mut self) -> BECE_W<'_>

Bit 20 - Bit Error Corrected Interrupt Enable

pub fn beue(&mut self) -> BEUE_W<'_>

Bit 21 - Bit Error Uncorrected Interrupt Enable

pub fn eloe(&mut self) -> ELOE_W<'_>

Bit 22 - Error Logging Overflow Interrupt Enable

pub fn epe(&mut self) -> EPE_W<'_>

Bit 23 - Error Passive Interrupt Enable

pub fn ewe(&mut self) -> EWE_W<'_>

Bit 24 - Warning Status Interrupt Enable

pub fn boe(&mut self) -> BOE_W<'_>

Bit 25 - Bus_Off Status Interrupt Enable

pub fn wdie(&mut self) -> WDIE_W<'_>

Bit 26 - Watchdog Interrupt Interrupt Enable

pub fn peae(&mut self) -> PEAE_W<'_>

Bit 27 - Protocol Error in Arbitration Phase Enable

pub fn pede(&mut self) -> PEDE_W<'_>

Bit 28 - Protocol Error in Data Phase Enable

pub fn arae(&mut self) -> ARAE_W<'_>

Bit 29 - Access to Reserved Address Enable

impl W<u32, Reg<u32, _ILS>>

pub fn rf0nl(&mut self) -> RF0NL_W<'_>

Bit 0 - Rx FIFO 0 New Message Interrupt Line

pub fn rf0wl(&mut self) -> RF0WL_W<'_>

Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line

pub fn rf0fl(&mut self) -> RF0FL_W<'_>

Bit 2 - Rx FIFO 0 Full Interrupt Line

pub fn rf0ll(&mut self) -> RF0LL_W<'_>

Bit 3 - Rx FIFO 0 Message Lost Interrupt Line

pub fn rf1nl(&mut self) -> RF1NL_W<'_>

Bit 4 - Rx FIFO 1 New Message Interrupt Line

pub fn rf1wl(&mut self) -> RF1WL_W<'_>

Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line

pub fn rf1fl(&mut self) -> RF1FL_W<'_>

Bit 6 - Rx FIFO 1 FIFO Full Interrupt Line

pub fn rf1ll(&mut self) -> RF1LL_W<'_>

Bit 7 - Rx FIFO 1 Message Lost Interrupt Line

pub fn hpml(&mut self) -> HPML_W<'_>

Bit 8 - High Priority Message Interrupt Line

pub fn tcl(&mut self) -> TCL_W<'_>

Bit 9 - Timestamp Completed Interrupt Line

pub fn tcfl(&mut self) -> TCFL_W<'_>

Bit 10 - Transmission Cancellation Finished Interrupt Line

pub fn tfel(&mut self) -> TFEL_W<'_>

Bit 11 - Tx FIFO Empty Interrupt Line

pub fn tefnl(&mut self) -> TEFNL_W<'_>

Bit 12 - Tx Event FIFO New Entry Interrupt Line

pub fn tefwl(&mut self) -> TEFWL_W<'_>

Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line

pub fn teffl(&mut self) -> TEFFL_W<'_>

Bit 14 - Tx Event FIFO Full Interrupt Line

pub fn tefll(&mut self) -> TEFLL_W<'_>

Bit 15 - Tx Event FIFO Element Lost Interrupt Line

pub fn tswl(&mut self) -> TSWL_W<'_>

Bit 16 - Timestamp Wraparound Interrupt Line

pub fn mrafl(&mut self) -> MRAFL_W<'_>

Bit 17 - Message RAM Access Failure Interrupt Line

pub fn tool(&mut self) -> TOOL_W<'_>

Bit 18 - Timeout Occurred Interrupt Line

pub fn drxl(&mut self) -> DRXL_W<'_>

Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line

pub fn becl(&mut self) -> BECL_W<'_>

Bit 20 - Bit Error Corrected Interrupt Line

pub fn beul(&mut self) -> BEUL_W<'_>

Bit 21 - Bit Error Uncorrected Interrupt Line

pub fn elol(&mut self) -> ELOL_W<'_>

Bit 22 - Error Logging Overflow Interrupt Line

pub fn epl(&mut self) -> EPL_W<'_>

Bit 23 - Error Passive Interrupt Line

pub fn ewl(&mut self) -> EWL_W<'_>

Bit 24 - Warning Status Interrupt Line

pub fn bol(&mut self) -> BOL_W<'_>

Bit 25 - Bus_Off Status Interrupt Line

pub fn wdil(&mut self) -> WDIL_W<'_>

Bit 26 - Watchdog Interrupt Interrupt Line

pub fn peal(&mut self) -> PEAL_W<'_>

Bit 27 - Protocol Error in Arbitration Phase Line

pub fn pedl(&mut self) -> PEDL_W<'_>

Bit 28 - Protocol Error in Data Phase Line

pub fn aral(&mut self) -> ARAL_W<'_>

Bit 29 - Access to Reserved Address Line

impl W<u32, Reg<u32, _ILE>>

pub fn eint0(&mut self) -> EINT0_W<'_>

Bit 0 - Enable Interrupt Line 0

pub fn eint1(&mut self) -> EINT1_W<'_>

Bit 1 - Enable Interrupt Line 1

impl W<u32, Reg<u32, _GFC>>

pub fn rrfe(&mut self) -> RRFE_W<'_>

Bit 0 - Reject Remote Frames Extended

pub fn rrfs(&mut self) -> RRFS_W<'_>

Bit 1 - Reject Remote Frames Standard

pub fn anfe(&mut self) -> ANFE_W<'_>

Bits 2:3 - Accept Non-matching Frames Extended

pub fn anfs(&mut self) -> ANFS_W<'_>

Bits 4:5 - Accept Non-matching Frames Standard

impl W<u32, Reg<u32, _SIDFC>>

pub fn flssa(&mut self) -> FLSSA_W<'_>

Bits 0:15 - Filter List Standard Start Address

pub fn lss(&mut self) -> LSS_W<'_>

Bits 16:23 - List Size Standard

impl W<u32, Reg<u32, _XIDFC>>

pub fn flesa(&mut self) -> FLESA_W<'_>

Bits 0:15 - Filter List Extended Start Address

pub fn lse(&mut self) -> LSE_W<'_>

Bits 16:22 - List Size Extended

impl W<u32, Reg<u32, _XIDAM>>

pub fn eidm(&mut self) -> EIDM_W<'_>

Bits 0:28 - Extended ID Mask

impl W<u32, Reg<u32, _NDAT1>>

pub fn nd0(&mut self) -> ND0_W<'_>

Bit 0 - New Data 0

pub fn nd1(&mut self) -> ND1_W<'_>

Bit 1 - New Data 1

pub fn nd2(&mut self) -> ND2_W<'_>

Bit 2 - New Data 2

pub fn nd3(&mut self) -> ND3_W<'_>

Bit 3 - New Data 3

pub fn nd4(&mut self) -> ND4_W<'_>

Bit 4 - New Data 4

pub fn nd5(&mut self) -> ND5_W<'_>

Bit 5 - New Data 5

pub fn nd6(&mut self) -> ND6_W<'_>

Bit 6 - New Data 6

pub fn nd7(&mut self) -> ND7_W<'_>

Bit 7 - New Data 7

pub fn nd8(&mut self) -> ND8_W<'_>

Bit 8 - New Data 8

pub fn nd9(&mut self) -> ND9_W<'_>

Bit 9 - New Data 9

pub fn nd10(&mut self) -> ND10_W<'_>

Bit 10 - New Data 10

pub fn nd11(&mut self) -> ND11_W<'_>

Bit 11 - New Data 11

pub fn nd12(&mut self) -> ND12_W<'_>

Bit 12 - New Data 12

pub fn nd13(&mut self) -> ND13_W<'_>

Bit 13 - New Data 13

pub fn nd14(&mut self) -> ND14_W<'_>

Bit 14 - New Data 14

pub fn nd15(&mut self) -> ND15_W<'_>

Bit 15 - New Data 15

pub fn nd16(&mut self) -> ND16_W<'_>

Bit 16 - New Data 16

pub fn nd17(&mut self) -> ND17_W<'_>

Bit 17 - New Data 17

pub fn nd18(&mut self) -> ND18_W<'_>

Bit 18 - New Data 18

pub fn nd19(&mut self) -> ND19_W<'_>

Bit 19 - New Data 19

pub fn nd20(&mut self) -> ND20_W<'_>

Bit 20 - New Data 20

pub fn nd21(&mut self) -> ND21_W<'_>

Bit 21 - New Data 21

pub fn nd22(&mut self) -> ND22_W<'_>

Bit 22 - New Data 22

pub fn nd23(&mut self) -> ND23_W<'_>

Bit 23 - New Data 23

pub fn nd24(&mut self) -> ND24_W<'_>

Bit 24 - New Data 24

pub fn nd25(&mut self) -> ND25_W<'_>

Bit 25 - New Data 25

pub fn nd26(&mut self) -> ND26_W<'_>

Bit 26 - New Data 26

pub fn nd27(&mut self) -> ND27_W<'_>

Bit 27 - New Data 27

pub fn nd28(&mut self) -> ND28_W<'_>

Bit 28 - New Data 28

pub fn nd29(&mut self) -> ND29_W<'_>

Bit 29 - New Data 29

pub fn nd30(&mut self) -> ND30_W<'_>

Bit 30 - New Data 30

pub fn nd31(&mut self) -> ND31_W<'_>

Bit 31 - New Data 31

impl W<u32, Reg<u32, _NDAT2>>

pub fn nd32(&mut self) -> ND32_W<'_>

Bit 0 - New Data 32

pub fn nd33(&mut self) -> ND33_W<'_>

Bit 1 - New Data 33

pub fn nd34(&mut self) -> ND34_W<'_>

Bit 2 - New Data 34

pub fn nd35(&mut self) -> ND35_W<'_>

Bit 3 - New Data 35

pub fn nd36(&mut self) -> ND36_W<'_>

Bit 4 - New Data 36

pub fn nd37(&mut self) -> ND37_W<'_>

Bit 5 - New Data 37

pub fn nd38(&mut self) -> ND38_W<'_>

Bit 6 - New Data 38

pub fn nd39(&mut self) -> ND39_W<'_>

Bit 7 - New Data 39

pub fn nd40(&mut self) -> ND40_W<'_>

Bit 8 - New Data 40

pub fn nd41(&mut self) -> ND41_W<'_>

Bit 9 - New Data 41

pub fn nd42(&mut self) -> ND42_W<'_>

Bit 10 - New Data 42

pub fn nd43(&mut self) -> ND43_W<'_>

Bit 11 - New Data 43

pub fn nd44(&mut self) -> ND44_W<'_>

Bit 12 - New Data 44

pub fn nd45(&mut self) -> ND45_W<'_>

Bit 13 - New Data 45

pub fn nd46(&mut self) -> ND46_W<'_>

Bit 14 - New Data 46

pub fn nd47(&mut self) -> ND47_W<'_>

Bit 15 - New Data 47

pub fn nd48(&mut self) -> ND48_W<'_>

Bit 16 - New Data 48

pub fn nd49(&mut self) -> ND49_W<'_>

Bit 17 - New Data 49

pub fn nd50(&mut self) -> ND50_W<'_>

Bit 18 - New Data 50

pub fn nd51(&mut self) -> ND51_W<'_>

Bit 19 - New Data 51

pub fn nd52(&mut self) -> ND52_W<'_>

Bit 20 - New Data 52

pub fn nd53(&mut self) -> ND53_W<'_>

Bit 21 - New Data 53

pub fn nd54(&mut self) -> ND54_W<'_>

Bit 22 - New Data 54

pub fn nd55(&mut self) -> ND55_W<'_>

Bit 23 - New Data 55

pub fn nd56(&mut self) -> ND56_W<'_>

Bit 24 - New Data 56

pub fn nd57(&mut self) -> ND57_W<'_>

Bit 25 - New Data 57

pub fn nd58(&mut self) -> ND58_W<'_>

Bit 26 - New Data 58

pub fn nd59(&mut self) -> ND59_W<'_>

Bit 27 - New Data 59

pub fn nd60(&mut self) -> ND60_W<'_>

Bit 28 - New Data 60

pub fn nd61(&mut self) -> ND61_W<'_>

Bit 29 - New Data 61

pub fn nd62(&mut self) -> ND62_W<'_>

Bit 30 - New Data 62

pub fn nd63(&mut self) -> ND63_W<'_>

Bit 31 - New Data 63

impl W<u32, Reg<u32, _RXF0C>>

pub fn f0sa(&mut self) -> F0SA_W<'_>

Bits 0:15 - Rx FIFO 0 Start Address

pub fn f0s(&mut self) -> F0S_W<'_>

Bits 16:22 - Rx FIFO 0 Size

pub fn f0wm(&mut self) -> F0WM_W<'_>

Bits 24:30 - Rx FIFO 0 Watermark

pub fn f0om(&mut self) -> F0OM_W<'_>

Bit 31 - FIFO 0 Operation Mode

impl W<u32, Reg<u32, _RXF0A>>

pub fn f0ai(&mut self) -> F0AI_W<'_>

Bits 0:5 - Rx FIFO 0 Acknowledge Index

impl W<u32, Reg<u32, _RXBC>>

pub fn rbsa(&mut self) -> RBSA_W<'_>

Bits 0:15 - Rx Buffer Start Address

impl W<u32, Reg<u32, _RXF1C>>

pub fn f1sa(&mut self) -> F1SA_W<'_>

Bits 0:15 - Rx FIFO 1 Start Address

pub fn f1s(&mut self) -> F1S_W<'_>

Bits 16:22 - Rx FIFO 1 Size

pub fn f1wm(&mut self) -> F1WM_W<'_>

Bits 24:30 - Rx FIFO 1 Watermark

pub fn f1om(&mut self) -> F1OM_W<'_>

Bit 31 - FIFO 1 Operation Mode

impl W<u32, Reg<u32, _RXF1A>>

pub fn f1ai(&mut self) -> F1AI_W<'_>

Bits 0:5 - Rx FIFO 1 Acknowledge Index

impl W<u32, Reg<u32, _RXESC>>

pub fn f0ds(&mut self) -> F0DS_W<'_>

Bits 0:2 - Rx FIFO 0 Data Field Size

pub fn f1ds(&mut self) -> F1DS_W<'_>

Bits 4:6 - Rx FIFO 1 Data Field Size

pub fn rbds(&mut self) -> RBDS_W<'_>

Bits 8:10 - Rx Buffer Data Field Size

impl W<u32, Reg<u32, _TXBC>>

pub fn tbsa(&mut self) -> TBSA_W<'_>

Bits 0:15 - Tx Buffers Start Address

pub fn ndtb(&mut self) -> NDTB_W<'_>

Bits 16:21 - Number of Dedicated Transmit Buffers

pub fn tfqs(&mut self) -> TFQS_W<'_>

Bits 24:29 - Transmit FIFO/Queue Size

pub fn tfqm(&mut self) -> TFQM_W<'_>

Bit 30 - Tx FIFO/Queue Mode

impl W<u32, Reg<u32, _TXESC>>

pub fn tbds(&mut self) -> TBDS_W<'_>

Bits 0:2 - Tx Buffer Data Field Size

impl W<u32, Reg<u32, _TXBAR>>

pub fn ar0(&mut self) -> AR0_W<'_>

Bit 0 - Add Request 0

pub fn ar1(&mut self) -> AR1_W<'_>

Bit 1 - Add Request 1

pub fn ar2(&mut self) -> AR2_W<'_>

Bit 2 - Add Request 2

pub fn ar3(&mut self) -> AR3_W<'_>

Bit 3 - Add Request 3

pub fn ar4(&mut self) -> AR4_W<'_>

Bit 4 - Add Request 4

pub fn ar5(&mut self) -> AR5_W<'_>

Bit 5 - Add Request 5

pub fn ar6(&mut self) -> AR6_W<'_>

Bit 6 - Add Request 6

pub fn ar7(&mut self) -> AR7_W<'_>

Bit 7 - Add Request 7

pub fn ar8(&mut self) -> AR8_W<'_>

Bit 8 - Add Request 8

pub fn ar9(&mut self) -> AR9_W<'_>

Bit 9 - Add Request 9

pub fn ar10(&mut self) -> AR10_W<'_>

Bit 10 - Add Request 10

pub fn ar11(&mut self) -> AR11_W<'_>

Bit 11 - Add Request 11

pub fn ar12(&mut self) -> AR12_W<'_>

Bit 12 - Add Request 12

pub fn ar13(&mut self) -> AR13_W<'_>

Bit 13 - Add Request 13

pub fn ar14(&mut self) -> AR14_W<'_>

Bit 14 - Add Request 14

pub fn ar15(&mut self) -> AR15_W<'_>

Bit 15 - Add Request 15

pub fn ar16(&mut self) -> AR16_W<'_>

Bit 16 - Add Request 16

pub fn ar17(&mut self) -> AR17_W<'_>

Bit 17 - Add Request 17

pub fn ar18(&mut self) -> AR18_W<'_>

Bit 18 - Add Request 18

pub fn ar19(&mut self) -> AR19_W<'_>

Bit 19 - Add Request 19

pub fn ar20(&mut self) -> AR20_W<'_>

Bit 20 - Add Request 20

pub fn ar21(&mut self) -> AR21_W<'_>

Bit 21 - Add Request 21

pub fn ar22(&mut self) -> AR22_W<'_>

Bit 22 - Add Request 22

pub fn ar23(&mut self) -> AR23_W<'_>

Bit 23 - Add Request 23

pub fn ar24(&mut self) -> AR24_W<'_>

Bit 24 - Add Request 24

pub fn ar25(&mut self) -> AR25_W<'_>

Bit 25 - Add Request 25

pub fn ar26(&mut self) -> AR26_W<'_>

Bit 26 - Add Request 26

pub fn ar27(&mut self) -> AR27_W<'_>

Bit 27 - Add Request 27

pub fn ar28(&mut self) -> AR28_W<'_>

Bit 28 - Add Request 28

pub fn ar29(&mut self) -> AR29_W<'_>

Bit 29 - Add Request 29

pub fn ar30(&mut self) -> AR30_W<'_>

Bit 30 - Add Request 30

pub fn ar31(&mut self) -> AR31_W<'_>

Bit 31 - Add Request 31

impl W<u32, Reg<u32, _TXBCR>>

pub fn cr0(&mut self) -> CR0_W<'_>

Bit 0 - Cancellation Request 0

pub fn cr1(&mut self) -> CR1_W<'_>

Bit 1 - Cancellation Request 1

pub fn cr2(&mut self) -> CR2_W<'_>

Bit 2 - Cancellation Request 2

pub fn cr3(&mut self) -> CR3_W<'_>

Bit 3 - Cancellation Request 3

pub fn cr4(&mut self) -> CR4_W<'_>

Bit 4 - Cancellation Request 4

pub fn cr5(&mut self) -> CR5_W<'_>

Bit 5 - Cancellation Request 5

pub fn cr6(&mut self) -> CR6_W<'_>

Bit 6 - Cancellation Request 6

pub fn cr7(&mut self) -> CR7_W<'_>

Bit 7 - Cancellation Request 7

pub fn cr8(&mut self) -> CR8_W<'_>

Bit 8 - Cancellation Request 8

pub fn cr9(&mut self) -> CR9_W<'_>

Bit 9 - Cancellation Request 9

pub fn cr10(&mut self) -> CR10_W<'_>

Bit 10 - Cancellation Request 10

pub fn cr11(&mut self) -> CR11_W<'_>

Bit 11 - Cancellation Request 11

pub fn cr12(&mut self) -> CR12_W<'_>

Bit 12 - Cancellation Request 12

pub fn cr13(&mut self) -> CR13_W<'_>

Bit 13 - Cancellation Request 13

pub fn cr14(&mut self) -> CR14_W<'_>

Bit 14 - Cancellation Request 14

pub fn cr15(&mut self) -> CR15_W<'_>

Bit 15 - Cancellation Request 15

pub fn cr16(&mut self) -> CR16_W<'_>

Bit 16 - Cancellation Request 16

pub fn cr17(&mut self) -> CR17_W<'_>

Bit 17 - Cancellation Request 17

pub fn cr18(&mut self) -> CR18_W<'_>

Bit 18 - Cancellation Request 18

pub fn cr19(&mut self) -> CR19_W<'_>

Bit 19 - Cancellation Request 19

pub fn cr20(&mut self) -> CR20_W<'_>

Bit 20 - Cancellation Request 20

pub fn cr21(&mut self) -> CR21_W<'_>

Bit 21 - Cancellation Request 21

pub fn cr22(&mut self) -> CR22_W<'_>

Bit 22 - Cancellation Request 22

pub fn cr23(&mut self) -> CR23_W<'_>

Bit 23 - Cancellation Request 23

pub fn cr24(&mut self) -> CR24_W<'_>

Bit 24 - Cancellation Request 24

pub fn cr25(&mut self) -> CR25_W<'_>

Bit 25 - Cancellation Request 25

pub fn cr26(&mut self) -> CR26_W<'_>

Bit 26 - Cancellation Request 26

pub fn cr27(&mut self) -> CR27_W<'_>

Bit 27 - Cancellation Request 27

pub fn cr28(&mut self) -> CR28_W<'_>

Bit 28 - Cancellation Request 28

pub fn cr29(&mut self) -> CR29_W<'_>

Bit 29 - Cancellation Request 29

pub fn cr30(&mut self) -> CR30_W<'_>

Bit 30 - Cancellation Request 30

pub fn cr31(&mut self) -> CR31_W<'_>

Bit 31 - Cancellation Request 31

impl W<u32, Reg<u32, _TXBTIE>>

pub fn tie0(&mut self) -> TIE0_W<'_>

Bit 0 - Transmission Interrupt Enable 0

pub fn tie1(&mut self) -> TIE1_W<'_>

Bit 1 - Transmission Interrupt Enable 1

pub fn tie2(&mut self) -> TIE2_W<'_>

Bit 2 - Transmission Interrupt Enable 2

pub fn tie3(&mut self) -> TIE3_W<'_>

Bit 3 - Transmission Interrupt Enable 3

pub fn tie4(&mut self) -> TIE4_W<'_>

Bit 4 - Transmission Interrupt Enable 4

pub fn tie5(&mut self) -> TIE5_W<'_>

Bit 5 - Transmission Interrupt Enable 5

pub fn tie6(&mut self) -> TIE6_W<'_>

Bit 6 - Transmission Interrupt Enable 6

pub fn tie7(&mut self) -> TIE7_W<'_>

Bit 7 - Transmission Interrupt Enable 7

pub fn tie8(&mut self) -> TIE8_W<'_>

Bit 8 - Transmission Interrupt Enable 8

pub fn tie9(&mut self) -> TIE9_W<'_>

Bit 9 - Transmission Interrupt Enable 9

pub fn tie10(&mut self) -> TIE10_W<'_>

Bit 10 - Transmission Interrupt Enable 10

pub fn tie11(&mut self) -> TIE11_W<'_>

Bit 11 - Transmission Interrupt Enable 11

pub fn tie12(&mut self) -> TIE12_W<'_>

Bit 12 - Transmission Interrupt Enable 12

pub fn tie13(&mut self) -> TIE13_W<'_>

Bit 13 - Transmission Interrupt Enable 13

pub fn tie14(&mut self) -> TIE14_W<'_>

Bit 14 - Transmission Interrupt Enable 14

pub fn tie15(&mut self) -> TIE15_W<'_>

Bit 15 - Transmission Interrupt Enable 15

pub fn tie16(&mut self) -> TIE16_W<'_>

Bit 16 - Transmission Interrupt Enable 16

pub fn tie17(&mut self) -> TIE17_W<'_>

Bit 17 - Transmission Interrupt Enable 17

pub fn tie18(&mut self) -> TIE18_W<'_>

Bit 18 - Transmission Interrupt Enable 18

pub fn tie19(&mut self) -> TIE19_W<'_>

Bit 19 - Transmission Interrupt Enable 19

pub fn tie20(&mut self) -> TIE20_W<'_>

Bit 20 - Transmission Interrupt Enable 20

pub fn tie21(&mut self) -> TIE21_W<'_>

Bit 21 - Transmission Interrupt Enable 21

pub fn tie22(&mut self) -> TIE22_W<'_>

Bit 22 - Transmission Interrupt Enable 22

pub fn tie23(&mut self) -> TIE23_W<'_>

Bit 23 - Transmission Interrupt Enable 23

pub fn tie24(&mut self) -> TIE24_W<'_>

Bit 24 - Transmission Interrupt Enable 24

pub fn tie25(&mut self) -> TIE25_W<'_>

Bit 25 - Transmission Interrupt Enable 25

pub fn tie26(&mut self) -> TIE26_W<'_>

Bit 26 - Transmission Interrupt Enable 26

pub fn tie27(&mut self) -> TIE27_W<'_>

Bit 27 - Transmission Interrupt Enable 27

pub fn tie28(&mut self) -> TIE28_W<'_>

Bit 28 - Transmission Interrupt Enable 28

pub fn tie29(&mut self) -> TIE29_W<'_>

Bit 29 - Transmission Interrupt Enable 29

pub fn tie30(&mut self) -> TIE30_W<'_>

Bit 30 - Transmission Interrupt Enable 30

pub fn tie31(&mut self) -> TIE31_W<'_>

Bit 31 - Transmission Interrupt Enable 31

impl W<u32, Reg<u32, _TXBCIE>>

pub fn cfie0(&mut self) -> CFIE0_W<'_>

Bit 0 - Cancellation Finished Interrupt Enable 0

pub fn cfie1(&mut self) -> CFIE1_W<'_>

Bit 1 - Cancellation Finished Interrupt Enable 1

pub fn cfie2(&mut self) -> CFIE2_W<'_>

Bit 2 - Cancellation Finished Interrupt Enable 2

pub fn cfie3(&mut self) -> CFIE3_W<'_>

Bit 3 - Cancellation Finished Interrupt Enable 3

pub fn cfie4(&mut self) -> CFIE4_W<'_>

Bit 4 - Cancellation Finished Interrupt Enable 4

pub fn cfie5(&mut self) -> CFIE5_W<'_>

Bit 5 - Cancellation Finished Interrupt Enable 5

pub fn cfie6(&mut self) -> CFIE6_W<'_>

Bit 6 - Cancellation Finished Interrupt Enable 6

pub fn cfie7(&mut self) -> CFIE7_W<'_>

Bit 7 - Cancellation Finished Interrupt Enable 7

pub fn cfie8(&mut self) -> CFIE8_W<'_>

Bit 8 - Cancellation Finished Interrupt Enable 8

pub fn cfie9(&mut self) -> CFIE9_W<'_>

Bit 9 - Cancellation Finished Interrupt Enable 9

pub fn cfie10(&mut self) -> CFIE10_W<'_>

Bit 10 - Cancellation Finished Interrupt Enable 10

pub fn cfie11(&mut self) -> CFIE11_W<'_>

Bit 11 - Cancellation Finished Interrupt Enable 11

pub fn cfie12(&mut self) -> CFIE12_W<'_>

Bit 12 - Cancellation Finished Interrupt Enable 12

pub fn cfie13(&mut self) -> CFIE13_W<'_>

Bit 13 - Cancellation Finished Interrupt Enable 13

pub fn cfie14(&mut self) -> CFIE14_W<'_>

Bit 14 - Cancellation Finished Interrupt Enable 14

pub fn cfie15(&mut self) -> CFIE15_W<'_>

Bit 15 - Cancellation Finished Interrupt Enable 15

pub fn cfie16(&mut self) -> CFIE16_W<'_>

Bit 16 - Cancellation Finished Interrupt Enable 16

pub fn cfie17(&mut self) -> CFIE17_W<'_>

Bit 17 - Cancellation Finished Interrupt Enable 17

pub fn cfie18(&mut self) -> CFIE18_W<'_>

Bit 18 - Cancellation Finished Interrupt Enable 18

pub fn cfie19(&mut self) -> CFIE19_W<'_>

Bit 19 - Cancellation Finished Interrupt Enable 19

pub fn cfie20(&mut self) -> CFIE20_W<'_>

Bit 20 - Cancellation Finished Interrupt Enable 20

pub fn cfie21(&mut self) -> CFIE21_W<'_>

Bit 21 - Cancellation Finished Interrupt Enable 21

pub fn cfie22(&mut self) -> CFIE22_W<'_>

Bit 22 - Cancellation Finished Interrupt Enable 22

pub fn cfie23(&mut self) -> CFIE23_W<'_>

Bit 23 - Cancellation Finished Interrupt Enable 23

pub fn cfie24(&mut self) -> CFIE24_W<'_>

Bit 24 - Cancellation Finished Interrupt Enable 24

pub fn cfie25(&mut self) -> CFIE25_W<'_>

Bit 25 - Cancellation Finished Interrupt Enable 25

pub fn cfie26(&mut self) -> CFIE26_W<'_>

Bit 26 - Cancellation Finished Interrupt Enable 26

pub fn cfie27(&mut self) -> CFIE27_W<'_>

Bit 27 - Cancellation Finished Interrupt Enable 27

pub fn cfie28(&mut self) -> CFIE28_W<'_>

Bit 28 - Cancellation Finished Interrupt Enable 28

pub fn cfie29(&mut self) -> CFIE29_W<'_>

Bit 29 - Cancellation Finished Interrupt Enable 29

pub fn cfie30(&mut self) -> CFIE30_W<'_>

Bit 30 - Cancellation Finished Interrupt Enable 30

pub fn cfie31(&mut self) -> CFIE31_W<'_>

Bit 31 - Cancellation Finished Interrupt Enable 31

impl W<u32, Reg<u32, _TXEFC>>

pub fn efsa(&mut self) -> EFSA_W<'_>

Bits 0:15 - Event FIFO Start Address

pub fn efs(&mut self) -> EFS_W<'_>

Bits 16:21 - Event FIFO Size

pub fn efwm(&mut self) -> EFWM_W<'_>

Bits 24:29 - Event FIFO Watermark

impl W<u32, Reg<u32, _TXEFA>>

pub fn efai(&mut self) -> EFAI_W<'_>

Bits 0:4 - Event FIFO Acknowledge Index

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

impl W<u8, Reg<u8, _SEQCTRL>>

pub fn seqsel(&mut self) -> SEQSEL_W<'_>

Bits 0:3 - Sequential Selection

impl W<u32, Reg<u32, _LUTCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - LUT Enable

pub fn filtsel(&mut self) -> FILTSEL_W<'_>

Bits 4:5 - Filter Selection

pub fn edgesel(&mut self) -> EDGESEL_W<'_>

Bit 7 - Edge Selection

pub fn insel0(&mut self) -> INSEL0_W<'_>

Bits 8:11 - Input Selection 0

pub fn insel1(&mut self) -> INSEL1_W<'_>

Bits 12:15 - Input Selection 1

pub fn insel2(&mut self) -> INSEL2_W<'_>

Bits 16:19 - Input Selection 2

pub fn invei(&mut self) -> INVEI_W<'_>

Bit 20 - Inverted Event Input Enable

pub fn lutei(&mut self) -> LUTEI_W<'_>

Bit 21 - LUT Event Input Enable

pub fn luteo(&mut self) -> LUTEO_W<'_>

Bit 22 - LUT Event Output Enable

pub fn truth(&mut self) -> TRUTH_W<'_>

Bits 24:31 - Truth Value

impl W<u32, Reg<u32, _CFG>>

pub fn icdis(&mut self) -> ICDIS_W<'_>

Bit 1 - Instruction Cache Disable

pub fn dcdis(&mut self) -> DCDIS_W<'_>

Bit 2 - Data Cache Disable

pub fn csizesw(&mut self) -> CSIZESW_W<'_>

Bits 4:6 - Cache size configured by software

impl W<u32, Reg<u32, _CTRL>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Cache Controller Enable

impl W<u32, Reg<u32, _LCKWAY>>

pub fn lckway(&mut self) -> LCKWAY_W<'_>

Bits 0:3 - Lockdown way Register

impl W<u32, Reg<u32, _MAINT0>>

pub fn invall(&mut self) -> INVALL_W<'_>

Bit 0 - Cache Controller invalidate All

impl W<u32, Reg<u32, _MAINT1>>

pub fn index(&mut self) -> INDEX_W<'_>

Bits 4:11 - Invalidate Index

pub fn way(&mut self) -> WAY_W<'_>

Bits 28:31 - Invalidate Way

impl W<u32, Reg<u32, _MCFG>>

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Cache Controller Monitor Counter Mode

impl W<u32, Reg<u32, _MEN>>

pub fn menable(&mut self) -> MENABLE_W<'_>

Bit 0 - Cache Controller Monitor Enable

impl W<u32, Reg<u32, _MCTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Cache Controller Software Reset

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable DAC Controller

impl W<u8, Reg<u8, _CTRLB>>

pub fn diff(&mut self) -> DIFF_W<'_>

Bit 0 - Differential mode enable

pub fn refsel(&mut self) -> REFSEL_W<'_>

Bits 1:2 - Reference Selection for DAC0/1

impl W<u8, Reg<u8, _EVCTRL>>

pub fn startei0(&mut self) -> STARTEI0_W<'_>

Bit 0 - Start Conversion Event Input DAC 0

pub fn startei1(&mut self) -> STARTEI1_W<'_>

Bit 1 - Start Conversion Event Input DAC 1

pub fn emptyeo0(&mut self) -> EMPTYEO0_W<'_>

Bit 2 - Data Buffer Empty Event Output DAC 0

pub fn emptyeo1(&mut self) -> EMPTYEO1_W<'_>

Bit 3 - Data Buffer Empty Event Output DAC 1

pub fn invei0(&mut self) -> INVEI0_W<'_>

Bit 4 - Enable Invertion of DAC 0 input event

pub fn invei1(&mut self) -> INVEI1_W<'_>

Bit 5 - Enable Invertion of DAC 1 input event

pub fn resrdyeo0(&mut self) -> RESRDYEO0_W<'_>

Bit 6 - Result Ready Event Output 0

pub fn resrdyeo1(&mut self) -> RESRDYEO1_W<'_>

Bit 7 - Result Ready Event Output 1

impl W<u8, Reg<u8, _INTENCLR>>

pub fn underrun0(&mut self) -> UNDERRUN0_W<'_>

Bit 0 - Underrun 0 Interrupt Enable

pub fn underrun1(&mut self) -> UNDERRUN1_W<'_>

Bit 1 - Underrun 1 Interrupt Enable

pub fn empty0(&mut self) -> EMPTY0_W<'_>

Bit 2 - Data Buffer 0 Empty Interrupt Enable

pub fn empty1(&mut self) -> EMPTY1_W<'_>

Bit 3 - Data Buffer 1 Empty Interrupt Enable

pub fn resrdy0(&mut self) -> RESRDY0_W<'_>

Bit 4 - Result 0 Ready Interrupt Enable

pub fn resrdy1(&mut self) -> RESRDY1_W<'_>

Bit 5 - Result 1 Ready Interrupt Enable

pub fn overrun0(&mut self) -> OVERRUN0_W<'_>

Bit 6 - Overrun 0 Interrupt Enable

pub fn overrun1(&mut self) -> OVERRUN1_W<'_>

Bit 7 - Overrun 1 Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn underrun0(&mut self) -> UNDERRUN0_W<'_>

Bit 0 - Underrun 0 Interrupt Enable

pub fn underrun1(&mut self) -> UNDERRUN1_W<'_>

Bit 1 - Underrun 1 Interrupt Enable

pub fn empty0(&mut self) -> EMPTY0_W<'_>

Bit 2 - Data Buffer 0 Empty Interrupt Enable

pub fn empty1(&mut self) -> EMPTY1_W<'_>

Bit 3 - Data Buffer 1 Empty Interrupt Enable

pub fn resrdy0(&mut self) -> RESRDY0_W<'_>

Bit 4 - Result 0 Ready Interrupt Enable

pub fn resrdy1(&mut self) -> RESRDY1_W<'_>

Bit 5 - Result 1 Ready Interrupt Enable

pub fn overrun0(&mut self) -> OVERRUN0_W<'_>

Bit 6 - Overrun 0 Interrupt Enable

pub fn overrun1(&mut self) -> OVERRUN1_W<'_>

Bit 7 - Overrun 1 Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn underrun0(&mut self) -> UNDERRUN0_W<'_>

Bit 0 - Result 0 Underrun

pub fn underrun1(&mut self) -> UNDERRUN1_W<'_>

Bit 1 - Result 1 Underrun

pub fn empty0(&mut self) -> EMPTY0_W<'_>

Bit 2 - Data Buffer 0 Empty

pub fn empty1(&mut self) -> EMPTY1_W<'_>

Bit 3 - Data Buffer 1 Empty

pub fn resrdy0(&mut self) -> RESRDY0_W<'_>

Bit 4 - Result 0 Ready

pub fn resrdy1(&mut self) -> RESRDY1_W<'_>

Bit 5 - Result 1 Ready

pub fn overrun0(&mut self) -> OVERRUN0_W<'_>

Bit 6 - Result 0 Overrun

pub fn overrun1(&mut self) -> OVERRUN1_W<'_>

Bit 7 - Result 1 Overrun

impl W<u16, Reg<u16, _DACCTRL>>

pub fn leftadj(&mut self) -> LEFTADJ_W<'_>

Bit 0 - Left Adjusted Data

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable DAC0

pub fn cctrl(&mut self) -> CCTRL_W<'_>

Bits 2:3 - Current Control

pub fn fext(&mut self) -> FEXT_W<'_>

Bit 5 - Standalone Filter

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn dither(&mut self) -> DITHER_W<'_>

Bit 7 - Dithering Mode

pub fn refresh(&mut self) -> REFRESH_W<'_>

Bits 8:11 - Refresh period

pub fn osr(&mut self) -> OSR_W<'_>

Bits 13:15 - Sampling Rate

impl W<u16, Reg<u16, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - DAC0 Data

impl W<u16, Reg<u16, _DATABUF>>

pub fn databuf(&mut self) -> DATABUF_W<'_>

Bits 0:15 - DAC0 Data Buffer

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u32, Reg<u32, _CHCTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Channel Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Channel Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Channel Run in Standby

pub fn trigsrc(&mut self) -> TRIGSRC_W<'_>

Bits 8:14 - Trigger Source

pub fn trigact(&mut self) -> TRIGACT_W<'_>

Bits 20:21 - Trigger Action

pub fn burstlen(&mut self) -> BURSTLEN_W<'_>

Bits 24:27 - Burst Length

pub fn threshold(&mut self) -> THRESHOLD_W<'_>

Bits 28:29 - FIFO Threshold

impl W<u8, Reg<u8, _CHCTRLB>>

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 0:1 - Software Command

impl W<u8, Reg<u8, _CHPRILVL>>

pub fn prilvl(&mut self) -> PRILVL_W<'_>

Bits 0:1 - Channel Priority Level

impl W<u8, Reg<u8, _CHEVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Channel Event Input Action

pub fn evomode(&mut self) -> EVOMODE_W<'_>

Bits 4:5 - Channel Event Output Mode

pub fn evie(&mut self) -> EVIE_W<'_>

Bit 6 - Channel Event Input Enable

pub fn evoe(&mut self) -> EVOE_W<'_>

Bit 7 - Channel Event Output Enable

impl W<u8, Reg<u8, _CHINTENCLR>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error Interrupt Enable

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete Interrupt Enable

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend Interrupt Enable

impl W<u8, Reg<u8, _CHINTENSET>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error Interrupt Enable

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete Interrupt Enable

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend Interrupt Enable

impl W<u8, Reg<u8, _CHINTFLAG>>

pub fn terr(&mut self) -> TERR_W<'_>

Bit 0 - Channel Transfer Error

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 1 - Channel Transfer Complete

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 2 - Channel Suspend

impl W<u8, Reg<u8, _CHSTATUS>>

pub fn pend(&mut self) -> PEND_W<'_>

Bit 0 - Channel Pending

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 1 - Channel Busy

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 2 - Channel Fetch Error

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 3 - Channel CRC Error

impl W<u16, Reg<u16, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn dmaenable(&mut self) -> DMAENABLE_W<'_>

Bit 1 - DMA Enable

pub fn lvlen0(&mut self) -> LVLEN0_W<'_>

Bit 8 - Priority Level 0 Enable

pub fn lvlen1(&mut self) -> LVLEN1_W<'_>

Bit 9 - Priority Level 1 Enable

pub fn lvlen2(&mut self) -> LVLEN2_W<'_>

Bit 10 - Priority Level 2 Enable

pub fn lvlen3(&mut self) -> LVLEN3_W<'_>

Bit 11 - Priority Level 3 Enable

impl W<u16, Reg<u16, _CRCCTRL>>

pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W<'_>

Bits 0:1 - CRC Beat Size

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 2:3 - CRC Polynomial Type

pub fn crcsrc(&mut self) -> CRCSRC_W<'_>

Bits 8:13 - CRC Input Source

pub fn crcmode(&mut self) -> CRCMODE_W<'_>

Bits 14:15 - CRC Operating Mode

impl W<u32, Reg<u32, _CRCDATAIN>>

pub fn crcdatain(&mut self) -> CRCDATAIN_W<'_>

Bits 0:31 - CRC Data Input

impl W<u32, Reg<u32, _CRCCHKSUM>>

pub fn crcchksum(&mut self) -> CRCCHKSUM_W<'_>

Bits 0:31 - CRC Checksum

impl W<u8, Reg<u8, _CRCSTATUS>>

pub fn crcbusy(&mut self) -> CRCBUSY_W<'_>

Bit 0 - CRC Module Busy

pub fn crczero(&mut self) -> CRCZERO_W<'_>

Bit 1 - CRC Zero

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 2 - CRC Error

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run

impl W<u32, Reg<u32, _SWTRIGCTRL>>

pub fn swtrig0(&mut self) -> SWTRIG0_W<'_>

Bit 0 - Channel 0 Software Trigger

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 1 - Channel 1 Software Trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 2 - Channel 2 Software Trigger

pub fn swtrig3(&mut self) -> SWTRIG3_W<'_>

Bit 3 - Channel 3 Software Trigger

pub fn swtrig4(&mut self) -> SWTRIG4_W<'_>

Bit 4 - Channel 4 Software Trigger

pub fn swtrig5(&mut self) -> SWTRIG5_W<'_>

Bit 5 - Channel 5 Software Trigger

pub fn swtrig6(&mut self) -> SWTRIG6_W<'_>

Bit 6 - Channel 6 Software Trigger

pub fn swtrig7(&mut self) -> SWTRIG7_W<'_>

Bit 7 - Channel 7 Software Trigger

pub fn swtrig8(&mut self) -> SWTRIG8_W<'_>

Bit 8 - Channel 8 Software Trigger

pub fn swtrig9(&mut self) -> SWTRIG9_W<'_>

Bit 9 - Channel 9 Software Trigger

pub fn swtrig10(&mut self) -> SWTRIG10_W<'_>

Bit 10 - Channel 10 Software Trigger

pub fn swtrig11(&mut self) -> SWTRIG11_W<'_>

Bit 11 - Channel 11 Software Trigger

pub fn swtrig12(&mut self) -> SWTRIG12_W<'_>

Bit 12 - Channel 12 Software Trigger

pub fn swtrig13(&mut self) -> SWTRIG13_W<'_>

Bit 13 - Channel 13 Software Trigger

pub fn swtrig14(&mut self) -> SWTRIG14_W<'_>

Bit 14 - Channel 14 Software Trigger

pub fn swtrig15(&mut self) -> SWTRIG15_W<'_>

Bit 15 - Channel 15 Software Trigger

pub fn swtrig16(&mut self) -> SWTRIG16_W<'_>

Bit 16 - Channel 16 Software Trigger

pub fn swtrig17(&mut self) -> SWTRIG17_W<'_>

Bit 17 - Channel 17 Software Trigger

pub fn swtrig18(&mut self) -> SWTRIG18_W<'_>

Bit 18 - Channel 18 Software Trigger

pub fn swtrig19(&mut self) -> SWTRIG19_W<'_>

Bit 19 - Channel 19 Software Trigger

pub fn swtrig20(&mut self) -> SWTRIG20_W<'_>

Bit 20 - Channel 20 Software Trigger

pub fn swtrig21(&mut self) -> SWTRIG21_W<'_>

Bit 21 - Channel 21 Software Trigger

pub fn swtrig22(&mut self) -> SWTRIG22_W<'_>

Bit 22 - Channel 22 Software Trigger

pub fn swtrig23(&mut self) -> SWTRIG23_W<'_>

Bit 23 - Channel 23 Software Trigger

pub fn swtrig24(&mut self) -> SWTRIG24_W<'_>

Bit 24 - Channel 24 Software Trigger

pub fn swtrig25(&mut self) -> SWTRIG25_W<'_>

Bit 25 - Channel 25 Software Trigger

pub fn swtrig26(&mut self) -> SWTRIG26_W<'_>

Bit 26 - Channel 26 Software Trigger

pub fn swtrig27(&mut self) -> SWTRIG27_W<'_>

Bit 27 - Channel 27 Software Trigger

pub fn swtrig28(&mut self) -> SWTRIG28_W<'_>

Bit 28 - Channel 28 Software Trigger

pub fn swtrig29(&mut self) -> SWTRIG29_W<'_>

Bit 29 - Channel 29 Software Trigger

pub fn swtrig30(&mut self) -> SWTRIG30_W<'_>

Bit 30 - Channel 30 Software Trigger

pub fn swtrig31(&mut self) -> SWTRIG31_W<'_>

Bit 31 - Channel 31 Software Trigger

impl W<u32, Reg<u32, _PRICTRL0>>

pub fn lvlpri0(&mut self) -> LVLPRI0_W<'_>

Bits 0:4 - Level 0 Channel Priority Number

pub fn qos0(&mut self) -> QOS0_W<'_>

Bits 5:6 - Level 0 Quality of Service

pub fn rrlvlen0(&mut self) -> RRLVLEN0_W<'_>

Bit 7 - Level 0 Round-Robin Scheduling Enable

pub fn lvlpri1(&mut self) -> LVLPRI1_W<'_>

Bits 8:12 - Level 1 Channel Priority Number

pub fn qos1(&mut self) -> QOS1_W<'_>

Bits 13:14 - Level 1 Quality of Service

pub fn rrlvlen1(&mut self) -> RRLVLEN1_W<'_>

Bit 15 - Level 1 Round-Robin Scheduling Enable

pub fn lvlpri2(&mut self) -> LVLPRI2_W<'_>

Bits 16:20 - Level 2 Channel Priority Number

pub fn qos2(&mut self) -> QOS2_W<'_>

Bits 21:22 - Level 2 Quality of Service

pub fn rrlvlen2(&mut self) -> RRLVLEN2_W<'_>

Bit 23 - Level 2 Round-Robin Scheduling Enable

pub fn lvlpri3(&mut self) -> LVLPRI3_W<'_>

Bits 24:28 - Level 3 Channel Priority Number

pub fn qos3(&mut self) -> QOS3_W<'_>

Bits 29:30 - Level 3 Quality of Service

pub fn rrlvlen3(&mut self) -> RRLVLEN3_W<'_>

Bit 31 - Level 3 Round-Robin Scheduling Enable

impl W<u16, Reg<u16, _INTPEND>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:4 - Channel ID

pub fn terr(&mut self) -> TERR_W<'_>

Bit 8 - Transfer Error

pub fn tcmpl(&mut self) -> TCMPL_W<'_>

Bit 9 - Transfer Complete

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 10 - Channel Suspend

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 12 - CRC Error

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 13 - Fetch Error

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 14 - Busy

pub fn pend(&mut self) -> PEND_W<'_>

Bit 15 - Pending

impl W<u32, Reg<u32, _BASEADDR>>

pub fn baseaddr(&mut self) -> BASEADDR_W<'_>

Bits 0:31 - Descriptor Memory Base Address

impl W<u32, Reg<u32, _WRBADDR>>

pub fn wrbaddr(&mut self) -> WRBADDR_W<'_>

Bits 0:31 - Write-Back Memory Base Address

impl W<u8, Reg<u8, _CTRL>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn crc(&mut self) -> CRC_W<'_>

Bit 2 - 32-bit Cyclic Redundancy Code

pub fn mbist(&mut self) -> MBIST_W<'_>

Bit 3 - Memory built-in self-test

pub fn ce(&mut self) -> CE_W<'_>

Bit 4 - Chip-Erase

impl W<u8, Reg<u8, _STATUSA>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Done

pub fn crstext(&mut self) -> CRSTEXT_W<'_>

Bit 1 - CPU Reset Phase Extension

pub fn berr(&mut self) -> BERR_W<'_>

Bit 2 - Bus Error

pub fn fail(&mut self) -> FAIL_W<'_>

Bit 3 - Failure

pub fn perr(&mut self) -> PERR_W<'_>

Bit 4 - Protection Error

impl W<u32, Reg<u32, _ADDR>>

pub fn amod(&mut self) -> AMOD_W<'_>

Bits 0:1 - Access Mode

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 2:31 - Address

impl W<u32, Reg<u32, _LENGTH>>

pub fn length(&mut self) -> LENGTH_W<'_>

Bits 2:31 - Length

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _DCC>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _CFG>>

pub fn lqos(&mut self) -> LQOS_W<'_>

Bits 0:1 - Latency Quality Of Service

pub fn dccdmalevel(&mut self) -> DCCDMALEVEL_W<'_>

Bits 2:3 - DMA Trigger Level

pub fn etbramen(&mut self) -> ETBRAMEN_W<'_>

Bit 4 - Trace Control

impl W<u32, Reg<u32, _DCFG>>

pub fn dcfg(&mut self) -> DCFG_W<'_>

Bits 0:31 - Device Configuration

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 4 - Clock Selection

impl W<u8, Reg<u8, _NMICTRL>>

pub fn nmisense(&mut self) -> NMISENSE_W<'_>

Bits 0:2 - Non-Maskable Interrupt Sense Configuration

pub fn nmifilten(&mut self) -> NMIFILTEN_W<'_>

Bit 3 - Non-Maskable Interrupt Filter Enable

pub fn nmiasynch(&mut self) -> NMIASYNCH_W<'_>

Bit 4 - Asynchronous Edge Detection Mode

impl W<u16, Reg<u16, _NMIFLAG>>

pub fn nmi(&mut self) -> NMI_W<'_>

Bit 0 - Non-Maskable Interrupt

impl W<u32, Reg<u32, _EVCTRL>>

pub fn extinteo(&mut self) -> EXTINTEO_W<'_>

Bits 0:15 - External Interrupt Event Output Enable

impl W<u32, Reg<u32, _INTENCLR>>

pub fn extint(&mut self) -> EXTINT_W<'_>

Bits 0:15 - External Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn extint(&mut self) -> EXTINT_W<'_>

Bits 0:15 - External Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn extint(&mut self) -> EXTINT_W<'_>

Bits 0:15 - External Interrupt

impl W<u32, Reg<u32, _ASYNCH>>

pub fn asynch(&mut self) -> ASYNCH_W<'_>

Bits 0:15 - Asynchronous Edge Detection Mode

impl W<u32, Reg<u32, _CONFIG>>

pub fn sense0(&mut self) -> SENSE0_W<'_>

Bits 0:2 - Input Sense Configuration 0

pub fn filten0(&mut self) -> FILTEN0_W<'_>

Bit 3 - Filter Enable 0

pub fn sense1(&mut self) -> SENSE1_W<'_>

Bits 4:6 - Input Sense Configuration 1

pub fn filten1(&mut self) -> FILTEN1_W<'_>

Bit 7 - Filter Enable 1

pub fn sense2(&mut self) -> SENSE2_W<'_>

Bits 8:10 - Input Sense Configuration 2

pub fn filten2(&mut self) -> FILTEN2_W<'_>

Bit 11 - Filter Enable 2

pub fn sense3(&mut self) -> SENSE3_W<'_>

Bits 12:14 - Input Sense Configuration 3

pub fn filten3(&mut self) -> FILTEN3_W<'_>

Bit 15 - Filter Enable 3

pub fn sense4(&mut self) -> SENSE4_W<'_>

Bits 16:18 - Input Sense Configuration 4

pub fn filten4(&mut self) -> FILTEN4_W<'_>

Bit 19 - Filter Enable 4

pub fn sense5(&mut self) -> SENSE5_W<'_>

Bits 20:22 - Input Sense Configuration 5

pub fn filten5(&mut self) -> FILTEN5_W<'_>

Bit 23 - Filter Enable 5

pub fn sense6(&mut self) -> SENSE6_W<'_>

Bits 24:26 - Input Sense Configuration 6

pub fn filten6(&mut self) -> FILTEN6_W<'_>

Bit 27 - Filter Enable 6

pub fn sense7(&mut self) -> SENSE7_W<'_>

Bits 28:30 - Input Sense Configuration 7

pub fn filten7(&mut self) -> FILTEN7_W<'_>

Bit 31 - Filter Enable 7

impl W<u32, Reg<u32, _DEBOUNCEN>>

pub fn debouncen(&mut self) -> DEBOUNCEN_W<'_>

Bits 0:15 - Debouncer Enable

impl W<u32, Reg<u32, _DPRESCALER>>

pub fn prescaler0(&mut self) -> PRESCALER0_W<'_>

Bits 0:2 - Debouncer Prescaler

pub fn states0(&mut self) -> STATES0_W<'_>

Bit 3 - Debouncer number of states

pub fn prescaler1(&mut self) -> PRESCALER1_W<'_>

Bits 4:6 - Debouncer Prescaler

pub fn states1(&mut self) -> STATES1_W<'_>

Bit 7 - Debouncer number of states

pub fn tickon(&mut self) -> TICKON_W<'_>

Bit 16 - Pin Sampler frequency selection

impl W<u32, Reg<u32, _CHANNEL>>

pub fn evgen(&mut self) -> EVGEN_W<'_>

Bits 0:6 - Event Generator Selection

pub fn path(&mut self) -> PATH_W<'_>

Bits 8:9 - Path Selection

pub fn edgsel(&mut self) -> EDGSEL_W<'_>

Bits 10:11 - Edge Detection Selection

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 14 - Run in standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 15 - Generic Clock On Demand

impl W<u8, Reg<u8, _CHINTENCLR>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 0 - Channel Overrun Interrupt Disable

pub fn evd(&mut self) -> EVD_W<'_>

Bit 1 - Channel Event Detected Interrupt Disable

impl W<u8, Reg<u8, _CHINTENSET>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 0 - Channel Overrun Interrupt Enable

pub fn evd(&mut self) -> EVD_W<'_>

Bit 1 - Channel Event Detected Interrupt Enable

impl W<u8, Reg<u8, _CHINTFLAG>>

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 0 - Channel Overrun

pub fn evd(&mut self) -> EVD_W<'_>

Bit 1 - Channel Event Detected

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

impl W<u32, Reg<u32, _SWEVT>>

pub fn channel0(&mut self) -> CHANNEL0_W<'_>

Bit 0 - Channel 0 Software Selection

pub fn channel1(&mut self) -> CHANNEL1_W<'_>

Bit 1 - Channel 1 Software Selection

pub fn channel2(&mut self) -> CHANNEL2_W<'_>

Bit 2 - Channel 2 Software Selection

pub fn channel3(&mut self) -> CHANNEL3_W<'_>

Bit 3 - Channel 3 Software Selection

pub fn channel4(&mut self) -> CHANNEL4_W<'_>

Bit 4 - Channel 4 Software Selection

pub fn channel5(&mut self) -> CHANNEL5_W<'_>

Bit 5 - Channel 5 Software Selection

pub fn channel6(&mut self) -> CHANNEL6_W<'_>

Bit 6 - Channel 6 Software Selection

pub fn channel7(&mut self) -> CHANNEL7_W<'_>

Bit 7 - Channel 7 Software Selection

pub fn channel8(&mut self) -> CHANNEL8_W<'_>

Bit 8 - Channel 8 Software Selection

pub fn channel9(&mut self) -> CHANNEL9_W<'_>

Bit 9 - Channel 9 Software Selection

pub fn channel10(&mut self) -> CHANNEL10_W<'_>

Bit 10 - Channel 10 Software Selection

pub fn channel11(&mut self) -> CHANNEL11_W<'_>

Bit 11 - Channel 11 Software Selection

pub fn channel12(&mut self) -> CHANNEL12_W<'_>

Bit 12 - Channel 12 Software Selection

pub fn channel13(&mut self) -> CHANNEL13_W<'_>

Bit 13 - Channel 13 Software Selection

pub fn channel14(&mut self) -> CHANNEL14_W<'_>

Bit 14 - Channel 14 Software Selection

pub fn channel15(&mut self) -> CHANNEL15_W<'_>

Bit 15 - Channel 15 Software Selection

pub fn channel16(&mut self) -> CHANNEL16_W<'_>

Bit 16 - Channel 16 Software Selection

pub fn channel17(&mut self) -> CHANNEL17_W<'_>

Bit 17 - Channel 17 Software Selection

pub fn channel18(&mut self) -> CHANNEL18_W<'_>

Bit 18 - Channel 18 Software Selection

pub fn channel19(&mut self) -> CHANNEL19_W<'_>

Bit 19 - Channel 19 Software Selection

pub fn channel20(&mut self) -> CHANNEL20_W<'_>

Bit 20 - Channel 20 Software Selection

pub fn channel21(&mut self) -> CHANNEL21_W<'_>

Bit 21 - Channel 21 Software Selection

pub fn channel22(&mut self) -> CHANNEL22_W<'_>

Bit 22 - Channel 22 Software Selection

pub fn channel23(&mut self) -> CHANNEL23_W<'_>

Bit 23 - Channel 23 Software Selection

pub fn channel24(&mut self) -> CHANNEL24_W<'_>

Bit 24 - Channel 24 Software Selection

pub fn channel25(&mut self) -> CHANNEL25_W<'_>

Bit 25 - Channel 25 Software Selection

pub fn channel26(&mut self) -> CHANNEL26_W<'_>

Bit 26 - Channel 26 Software Selection

pub fn channel27(&mut self) -> CHANNEL27_W<'_>

Bit 27 - Channel 27 Software Selection

pub fn channel28(&mut self) -> CHANNEL28_W<'_>

Bit 28 - Channel 28 Software Selection

pub fn channel29(&mut self) -> CHANNEL29_W<'_>

Bit 29 - Channel 29 Software Selection

pub fn channel30(&mut self) -> CHANNEL30_W<'_>

Bit 30 - Channel 30 Software Selection

pub fn channel31(&mut self) -> CHANNEL31_W<'_>

Bit 31 - Channel 31 Software Selection

impl W<u8, Reg<u8, _PRICTRL>>

pub fn pri(&mut self) -> PRI_W<'_>

Bits 0:3 - Channel Priority Number

pub fn rren(&mut self) -> RREN_W<'_>

Bit 7 - Round-Robin Scheduling Enable

impl W<u16, Reg<u16, _INTPEND>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:3 - Channel ID

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 8 - Channel Overrun

pub fn evd(&mut self) -> EVD_W<'_>

Bit 9 - Channel Event Detected

pub fn ready(&mut self) -> READY_W<'_>

Bit 14 - Ready

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 15 - Busy

impl W<u32, Reg<u32, _USER>>

pub fn channel(&mut self) -> CHANNEL_W<'_>

Bits 0:5 - Channel Event Selection

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

impl W<u8, Reg<u8, _CTRLB>>

pub fn start(&mut self) -> START_W<'_>

Bit 0 - Start Measurement

impl W<u16, Reg<u16, _CFGA>>

pub fn refnum(&mut self) -> REFNUM_W<'_>

Bits 0:7 - Number of Reference Clock Cycles

impl W<u8, Reg<u8, _INTENCLR>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Measurement Done Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Measurement Done Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Measurement Done

impl W<u8, Reg<u8, _STATUS>>

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 0 - FREQM Status

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 1 - Sticky Count Value Overflow

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

impl W<u32, Reg<u32, _GENCTRL>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:3 - Source Select

pub fn genen(&mut self) -> GENEN_W<'_>

Bit 8 - Generic Clock Generator Enable

pub fn idc(&mut self) -> IDC_W<'_>

Bit 9 - Improve Duty Cycle

pub fn oov(&mut self) -> OOV_W<'_>

Bit 10 - Output Off Value

pub fn oe(&mut self) -> OE_W<'_>

Bit 11 - Output Enable

pub fn divsel(&mut self) -> DIVSEL_W<'_>

Bit 12 - Divide Selection

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 13 - Run in Standby

pub fn div(&mut self) -> DIV_W<'_>

Bits 16:31 - Division Factor

impl W<u32, Reg<u32, _PCHCTRL>>

pub fn gen(&mut self) -> GEN_W<'_>

Bits 0:3 - Generic Clock Generator

pub fn chen(&mut self) -> CHEN_W<'_>

Bit 6 - Channel Enable

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 7 - Write Lock

impl W<u32, Reg<u32, _SAB>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Specific Address 1

impl W<u32, Reg<u32, _SAT>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific Address 1

impl W<u32, Reg<u32, _NCR>>

pub fn lbl(&mut self) -> LBL_W<'_>

Bit 1 - Loop Back Local

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 2 - Receive Enable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 3 - Transmit Enable

pub fn mpe(&mut self) -> MPE_W<'_>

Bit 4 - Management Port Enable

pub fn clrstat(&mut self) -> CLRSTAT_W<'_>

Bit 5 - Clear Statistics Registers

pub fn incstat(&mut self) -> INCSTAT_W<'_>

Bit 6 - Increment Statistics Registers

pub fn westat(&mut self) -> WESTAT_W<'_>

Bit 7 - Write Enable for Statistics Registers

pub fn bp(&mut self) -> BP_W<'_>

Bit 8 - Back pressure

pub fn tstart(&mut self) -> TSTART_W<'_>

Bit 9 - Start Transmission

pub fn thalt(&mut self) -> THALT_W<'_>

Bit 10 - Transmit Halt

pub fn txpf(&mut self) -> TXPF_W<'_>

Bit 11 - Transmit Pause Frame

pub fn txzqpf(&mut self) -> TXZQPF_W<'_>

Bit 12 - Transmit Zero Quantum Pause Frame

pub fn srtsm(&mut self) -> SRTSM_W<'_>

Bit 15 - Store Receive Time Stamp to Memory

pub fn enpbpr(&mut self) -> ENPBPR_W<'_>

Bit 16 - Enable PFC Priority-based Pause Reception

pub fn txpbpf(&mut self) -> TXPBPF_W<'_>

Bit 17 - Transmit PFC Priority-based Pause Frame

pub fn fnp(&mut self) -> FNP_W<'_>

Bit 18 - Flush Next Packet

pub fn lpi(&mut self) -> LPI_W<'_>

Bit 19 - Low Power Idle Enable

impl W<u32, Reg<u32, _NCFGR>>

pub fn spd(&mut self) -> SPD_W<'_>

Bit 0 - Speed

pub fn fd(&mut self) -> FD_W<'_>

Bit 1 - Full Duplex

pub fn dnvlan(&mut self) -> DNVLAN_W<'_>

Bit 2 - Discard Non-VLAN FRAMES

pub fn jframe(&mut self) -> JFRAME_W<'_>

Bit 3 - Jumbo Frame Size

pub fn caf(&mut self) -> CAF_W<'_>

Bit 4 - Copy All Frames

pub fn nbc(&mut self) -> NBC_W<'_>

Bit 5 - No Broadcast

pub fn mtihen(&mut self) -> MTIHEN_W<'_>

Bit 6 - Multicast Hash Enable

pub fn unihen(&mut self) -> UNIHEN_W<'_>

Bit 7 - Unicast Hash Enable

pub fn maxfs(&mut self) -> MAXFS_W<'_>

Bit 8 - 1536 Maximum Frame Size

pub fn rty(&mut self) -> RTY_W<'_>

Bit 12 - Retry Test

pub fn pen(&mut self) -> PEN_W<'_>

Bit 13 - Pause Enable

pub fn rxbufo(&mut self) -> RXBUFO_W<'_>

Bits 14:15 - Receive Buffer Offset

pub fn lferd(&mut self) -> LFERD_W<'_>

Bit 16 - Length Field Error Frame Discard

pub fn rfcs(&mut self) -> RFCS_W<'_>

Bit 17 - Remove FCS

pub fn clk(&mut self) -> CLK_W<'_>

Bits 18:20 - MDC CLock Division

pub fn dbw(&mut self) -> DBW_W<'_>

Bits 21:22 - Data Bus Width

pub fn dcpf(&mut self) -> DCPF_W<'_>

Bit 23 - Disable Copy of Pause Frames

pub fn rxcoen(&mut self) -> RXCOEN_W<'_>

Bit 24 - Receive Checksum Offload Enable

pub fn efrhd(&mut self) -> EFRHD_W<'_>

Bit 25 - Enable Frames Received in Half Duplex

pub fn irxfcs(&mut self) -> IRXFCS_W<'_>

Bit 26 - Ignore RX FCS

pub fn ipgsen(&mut self) -> IPGSEN_W<'_>

Bit 28 - IP Stretch Enable

pub fn rxbp(&mut self) -> RXBP_W<'_>

Bit 29 - Receive Bad Preamble

pub fn irxer(&mut self) -> IRXER_W<'_>

Bit 30 - Ignore IPG GRXER

impl W<u32, Reg<u32, _UR>>

pub fn mii(&mut self) -> MII_W<'_>

Bit 0 - MII Mode

impl W<u32, Reg<u32, _DCFGR>>

pub fn fbldo(&mut self) -> FBLDO_W<'_>

Bits 0:4 - Fixed Burst Length for DMA Data Operations:

pub fn esma(&mut self) -> ESMA_W<'_>

Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses

pub fn espa(&mut self) -> ESPA_W<'_>

Bit 7 - Endian Swap Mode Enable for Packet Data Accesses

pub fn rxbms(&mut self) -> RXBMS_W<'_>

Bits 8:9 - Receiver Packet Buffer Memory Size Select

pub fn txpbms(&mut self) -> TXPBMS_W<'_>

Bit 10 - Transmitter Packet Buffer Memory Size Select

pub fn txcoen(&mut self) -> TXCOEN_W<'_>

Bit 11 - Transmitter Checksum Generation Offload Enable

pub fn drbs(&mut self) -> DRBS_W<'_>

Bits 16:23 - DMA Receive Buffer Size

pub fn ddrp(&mut self) -> DDRP_W<'_>

Bit 24 - DMA Discard Receive Packets

impl W<u32, Reg<u32, _TSR>>

pub fn ubr(&mut self) -> UBR_W<'_>

Bit 0 - Used Bit Read

pub fn col(&mut self) -> COL_W<'_>

Bit 1 - Collision Occurred

pub fn rle(&mut self) -> RLE_W<'_>

Bit 2 - Retry Limit Exceeded

pub fn txgo(&mut self) -> TXGO_W<'_>

Bit 3 - Transmit Go

pub fn tfc(&mut self) -> TFC_W<'_>

Bit 4 - Transmit Frame Corruption Due to AHB Error

pub fn txcomp(&mut self) -> TXCOMP_W<'_>

Bit 5 - Transmit Complete

pub fn und(&mut self) -> UND_W<'_>

Bit 6 - Transmit Underrun

pub fn hresp(&mut self) -> HRESP_W<'_>

Bit 8 - HRESP Not OK

impl W<u32, Reg<u32, _RBQB>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 2:31 - Receive Buffer Queue Base Address

impl W<u32, Reg<u32, _TBQB>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 2:31 - Transmit Buffer Queue Base Address

impl W<u32, Reg<u32, _RSR>>

pub fn bna(&mut self) -> BNA_W<'_>

Bit 0 - Buffer Not Available

pub fn rec(&mut self) -> REC_W<'_>

Bit 1 - Frame Received

pub fn rxovr(&mut self) -> RXOVR_W<'_>

Bit 2 - Receive Overrun

pub fn hno(&mut self) -> HNO_W<'_>

Bit 3 - HRESP Not OK

impl W<u32, Reg<u32, _ISR>>

pub fn mfs(&mut self) -> MFS_W<'_>

Bit 0 - Management Frame Sent

pub fn rcomp(&mut self) -> RCOMP_W<'_>

Bit 1 - Receive Complete

pub fn rxubr(&mut self) -> RXUBR_W<'_>

Bit 2 - RX Used Bit Read

pub fn txubr(&mut self) -> TXUBR_W<'_>

Bit 3 - TX Used Bit Read

pub fn tur(&mut self) -> TUR_W<'_>

Bit 4 - Transmit Underrun

pub fn rlex(&mut self) -> RLEX_W<'_>

Bit 5 - Retry Limit Exceeded

pub fn tfc(&mut self) -> TFC_W<'_>

Bit 6 - Transmit Frame Corruption Due to AHB Error

pub fn tcomp(&mut self) -> TCOMP_W<'_>

Bit 7 - Transmit Complete

pub fn rovr(&mut self) -> ROVR_W<'_>

Bit 10 - Receive Overrun

pub fn hresp(&mut self) -> HRESP_W<'_>

Bit 11 - HRESP Not OK

pub fn pfnz(&mut self) -> PFNZ_W<'_>

Bit 12 - Pause Frame with Non-zero Pause Quantum Received

pub fn ptz(&mut self) -> PTZ_W<'_>

Bit 13 - Pause Time Zero

pub fn pftr(&mut self) -> PFTR_W<'_>

Bit 14 - Pause Frame Transmitted

pub fn drqfr(&mut self) -> DRQFR_W<'_>

Bit 18 - PTP Delay Request Frame Received

pub fn sfr(&mut self) -> SFR_W<'_>

Bit 19 - PTP Sync Frame Received

pub fn drqft(&mut self) -> DRQFT_W<'_>

Bit 20 - PTP Delay Request Frame Transmitted

pub fn sft(&mut self) -> SFT_W<'_>

Bit 21 - PTP Sync Frame Transmitted

pub fn pdrqfr(&mut self) -> PDRQFR_W<'_>

Bit 22 - PDelay Request Frame Received

pub fn pdrsfr(&mut self) -> PDRSFR_W<'_>

Bit 23 - PDelay Response Frame Received

pub fn pdrqft(&mut self) -> PDRQFT_W<'_>

Bit 24 - PDelay Request Frame Transmitted

pub fn pdrsft(&mut self) -> PDRSFT_W<'_>

Bit 25 - PDelay Response Frame Transmitted

pub fn sri(&mut self) -> SRI_W<'_>

Bit 26 - TSU Seconds Register Increment

pub fn rxlpisbc(&mut self) -> RXLPISBC_W<'_>

Bit 27 - Enable RX LPI Indication

pub fn wol(&mut self) -> WOL_W<'_>

Bit 28 - Wake On LAN

pub fn tsucmp(&mut self) -> TSUCMP_W<'_>

Bit 29 - Tsu timer comparison

impl W<u32, Reg<u32, _IER>>

pub fn mfs(&mut self) -> MFS_W<'_>

Bit 0 - Management Frame Sent

pub fn rcomp(&mut self) -> RCOMP_W<'_>

Bit 1 - Receive Complete

pub fn rxubr(&mut self) -> RXUBR_W<'_>

Bit 2 - RX Used Bit Read

pub fn txubr(&mut self) -> TXUBR_W<'_>

Bit 3 - TX Used Bit Read

pub fn tur(&mut self) -> TUR_W<'_>

Bit 4 - Transmit Underrun

pub fn rlex(&mut self) -> RLEX_W<'_>

Bit 5 - Retry Limit Exceeded or Late Collision

pub fn tfc(&mut self) -> TFC_W<'_>

Bit 6 - Transmit Frame Corruption Due to AHB Error

pub fn tcomp(&mut self) -> TCOMP_W<'_>

Bit 7 - Transmit Complete

pub fn rovr(&mut self) -> ROVR_W<'_>

Bit 10 - Receive Overrun

pub fn hresp(&mut self) -> HRESP_W<'_>

Bit 11 - HRESP Not OK

pub fn pfnz(&mut self) -> PFNZ_W<'_>

Bit 12 - Pause Frame with Non-zero Pause Quantum Received

pub fn ptz(&mut self) -> PTZ_W<'_>

Bit 13 - Pause Time Zero

pub fn pftr(&mut self) -> PFTR_W<'_>

Bit 14 - Pause Frame Transmitted

pub fn exint(&mut self) -> EXINT_W<'_>

Bit 15 - External Interrupt

pub fn drqfr(&mut self) -> DRQFR_W<'_>

Bit 18 - PTP Delay Request Frame Received

pub fn sfr(&mut self) -> SFR_W<'_>

Bit 19 - PTP Sync Frame Received

pub fn drqft(&mut self) -> DRQFT_W<'_>

Bit 20 - PTP Delay Request Frame Transmitted

pub fn sft(&mut self) -> SFT_W<'_>

Bit 21 - PTP Sync Frame Transmitted

pub fn pdrqfr(&mut self) -> PDRQFR_W<'_>

Bit 22 - PDelay Request Frame Received

pub fn pdrsfr(&mut self) -> PDRSFR_W<'_>

Bit 23 - PDelay Response Frame Received

pub fn pdrqft(&mut self) -> PDRQFT_W<'_>

Bit 24 - PDelay Request Frame Transmitted

pub fn pdrsft(&mut self) -> PDRSFT_W<'_>

Bit 25 - PDelay Response Frame Transmitted

pub fn sri(&mut self) -> SRI_W<'_>

Bit 26 - TSU Seconds Register Increment

pub fn rxlpisbc(&mut self) -> RXLPISBC_W<'_>

Bit 27 - Enable RX LPI Indication

pub fn wol(&mut self) -> WOL_W<'_>

Bit 28 - Wake On LAN

pub fn tsucmp(&mut self) -> TSUCMP_W<'_>

Bit 29 - Tsu timer comparison

impl W<u32, Reg<u32, _IDR>>

pub fn mfs(&mut self) -> MFS_W<'_>

Bit 0 - Management Frame Sent

pub fn rcomp(&mut self) -> RCOMP_W<'_>

Bit 1 - Receive Complete

pub fn rxubr(&mut self) -> RXUBR_W<'_>

Bit 2 - RX Used Bit Read

pub fn txubr(&mut self) -> TXUBR_W<'_>

Bit 3 - TX Used Bit Read

pub fn tur(&mut self) -> TUR_W<'_>

Bit 4 - Transmit Underrun

pub fn rlex(&mut self) -> RLEX_W<'_>

Bit 5 - Retry Limit Exceeded or Late Collision

pub fn tfc(&mut self) -> TFC_W<'_>

Bit 6 - Transmit Frame Corruption Due to AHB Error

pub fn tcomp(&mut self) -> TCOMP_W<'_>

Bit 7 - Transmit Complete

pub fn rovr(&mut self) -> ROVR_W<'_>

Bit 10 - Receive Overrun

pub fn hresp(&mut self) -> HRESP_W<'_>

Bit 11 - HRESP Not OK

pub fn pfnz(&mut self) -> PFNZ_W<'_>

Bit 12 - Pause Frame with Non-zero Pause Quantum Received

pub fn ptz(&mut self) -> PTZ_W<'_>

Bit 13 - Pause Time Zero

pub fn pftr(&mut self) -> PFTR_W<'_>

Bit 14 - Pause Frame Transmitted

pub fn exint(&mut self) -> EXINT_W<'_>

Bit 15 - External Interrupt

pub fn drqfr(&mut self) -> DRQFR_W<'_>

Bit 18 - PTP Delay Request Frame Received

pub fn sfr(&mut self) -> SFR_W<'_>

Bit 19 - PTP Sync Frame Received

pub fn drqft(&mut self) -> DRQFT_W<'_>

Bit 20 - PTP Delay Request Frame Transmitted

pub fn sft(&mut self) -> SFT_W<'_>

Bit 21 - PTP Sync Frame Transmitted

pub fn pdrqfr(&mut self) -> PDRQFR_W<'_>

Bit 22 - PDelay Request Frame Received

pub fn pdrsfr(&mut self) -> PDRSFR_W<'_>

Bit 23 - PDelay Response Frame Received

pub fn pdrqft(&mut self) -> PDRQFT_W<'_>

Bit 24 - PDelay Request Frame Transmitted

pub fn pdrsft(&mut self) -> PDRSFT_W<'_>

Bit 25 - PDelay Response Frame Transmitted

pub fn sri(&mut self) -> SRI_W<'_>

Bit 26 - TSU Seconds Register Increment

pub fn rxlpisbc(&mut self) -> RXLPISBC_W<'_>

Bit 27 - Enable RX LPI Indication

pub fn wol(&mut self) -> WOL_W<'_>

Bit 28 - Wake On LAN

pub fn tsucmp(&mut self) -> TSUCMP_W<'_>

Bit 29 - Tsu timer comparison

impl W<u32, Reg<u32, _MAN>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - PHY Data

pub fn wtn(&mut self) -> WTN_W<'_>

Bits 16:17 - Write Ten

pub fn rega(&mut self) -> REGA_W<'_>

Bits 18:22 - Register Address

pub fn phya(&mut self) -> PHYA_W<'_>

Bits 23:27 - PHY Address

pub fn op(&mut self) -> OP_W<'_>

Bits 28:29 - Operation

pub fn cltto(&mut self) -> CLTTO_W<'_>

Bit 30 - Clause 22 Operation

pub fn wzo(&mut self) -> WZO_W<'_>

Bit 31 - Write ZERO

impl W<u32, Reg<u32, _TPQ>>

pub fn tpq(&mut self) -> TPQ_W<'_>

Bits 0:15 - Transmit Pause Quantum

impl W<u32, Reg<u32, _TPSF>>

pub fn tpb1adr(&mut self) -> TPB1ADR_W<'_>

Bits 0:9 - TX packet buffer address

pub fn entxp(&mut self) -> ENTXP_W<'_>

Bit 31 - Enable TX partial store and forward operation

impl W<u32, Reg<u32, _RPSF>>

pub fn rpb1adr(&mut self) -> RPB1ADR_W<'_>

Bits 0:9 - RX packet buffer address

pub fn enrxp(&mut self) -> ENRXP_W<'_>

Bit 31 - Enable RX partial store and forward operation

impl W<u32, Reg<u32, _RJFML>>

pub fn fml(&mut self) -> FML_W<'_>

Bits 0:13 - Frame Max Length

impl W<u32, Reg<u32, _HRB>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Hash Address

impl W<u32, Reg<u32, _HRT>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Hash Address

impl W<u32, Reg<u32, _TIDM>>

pub fn tid(&mut self) -> TID_W<'_>

Bits 0:15 - Type ID Match n

pub fn enid(&mut self) -> ENID_W<'_>

Bit 31 - Enable Copying of TID n Matched Frames

impl W<u32, Reg<u32, _WOL>>

pub fn ip(&mut self) -> IP_W<'_>

Bits 0:15 - IP address

pub fn mag(&mut self) -> MAG_W<'_>

Bit 16 - Event enable

pub fn arp(&mut self) -> ARP_W<'_>

Bit 17 - LAN ARP req

pub fn sa1(&mut self) -> SA1_W<'_>

Bit 18 - WOL specific address reg 1

pub fn mti(&mut self) -> MTI_W<'_>

Bit 19 - WOL LAN multicast

impl W<u32, Reg<u32, _IPGS>>

pub fn fl(&mut self) -> FL_W<'_>

Bits 0:15 - Frame Length

impl W<u32, Reg<u32, _SVLAN>>

pub fn vlan_type(&mut self) -> VLAN_TYPE_W<'_>

Bits 0:15 - User Defined VLAN_TYPE Field

pub fn esvlan(&mut self) -> ESVLAN_W<'_>

Bit 31 - Enable Stacked VLAN Processing Mode

impl W<u32, Reg<u32, _TPFCP>>

pub fn pev(&mut self) -> PEV_W<'_>

Bits 0:7 - Priority Enable Vector

pub fn pq(&mut self) -> PQ_W<'_>

Bits 8:15 - Pause Quantum

impl W<u32, Reg<u32, _SAMB1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Specific Address 1 Mask

impl W<u32, Reg<u32, _SAMT1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:15 - Specific Address 1 Mask

impl W<u32, Reg<u32, _NSC>>

pub fn nanosec(&mut self) -> NANOSEC_W<'_>

Bits 0:20 - 1588 Timer Nanosecond comparison value

impl W<u32, Reg<u32, _SCL>>

pub fn sec(&mut self) -> SEC_W<'_>

Bits 0:31 - 1588 Timer Second comparison value

impl W<u32, Reg<u32, _SCH>>

pub fn sec(&mut self) -> SEC_W<'_>

Bits 0:15 - 1588 Timer Second comparison value

impl W<u32, Reg<u32, _TISUBN>>

pub fn lsbtir(&mut self) -> LSBTIR_W<'_>

Bits 0:15 - Lower Significant Bits of Timer Increment

impl W<u32, Reg<u32, _TSH>>

pub fn tcs(&mut self) -> TCS_W<'_>

Bits 0:15 - Timer Count in Seconds

impl W<u32, Reg<u32, _TSSSL>>

pub fn vts(&mut self) -> VTS_W<'_>

Bits 0:31 - Value of Timer Seconds Register Capture

impl W<u32, Reg<u32, _TSSN>>

pub fn vtn(&mut self) -> VTN_W<'_>

Bits 0:29 - Value Timer Nanoseconds Register Capture

impl W<u32, Reg<u32, _TSL>>

pub fn tcs(&mut self) -> TCS_W<'_>

Bits 0:31 - Timer Count in Seconds

impl W<u32, Reg<u32, _TN>>

pub fn tns(&mut self) -> TNS_W<'_>

Bits 0:29 - Timer Count in Nanoseconds

impl W<u32, Reg<u32, _TA>>

pub fn itdt(&mut self) -> ITDT_W<'_>

Bits 0:29 - Increment/Decrement

pub fn adj(&mut self) -> ADJ_W<'_>

Bit 31 - Adjust 1588 Timer

impl W<u32, Reg<u32, _TI>>

pub fn cns(&mut self) -> CNS_W<'_>

Bits 0:7 - Count Nanoseconds

pub fn acns(&mut self) -> ACNS_W<'_>

Bits 8:15 - Alternative Count Nanoseconds

pub fn nit(&mut self) -> NIT_W<'_>

Bits 16:23 - Number of Increments

impl W<u32, Reg<u32, _CFG>>

pub fn wbdis(&mut self) -> WBDIS_W<'_>

Bit 0 - Write Back Disable

pub fn eomdis(&mut self) -> EOMDIS_W<'_>

Bit 1 - End of Monitoring Disable

pub fn slbdis(&mut self) -> SLBDIS_W<'_>

Bit 2 - Secondary List Branching Disable

pub fn bbc(&mut self) -> BBC_W<'_>

Bits 4:7 - Bus Burden Control

pub fn ascd(&mut self) -> ASCD_W<'_>

Bit 8 - Automatic Switch To Compare Digest

pub fn dualbuff(&mut self) -> DUALBUFF_W<'_>

Bit 9 - Dual Input Buffer

pub fn uihash(&mut self) -> UIHASH_W<'_>

Bit 12 - User Initial Hash Value

pub fn ualgo(&mut self) -> UALGO_W<'_>

Bits 13:15 - User SHA Algorithm

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - ICM Enable

pub fn disable(&mut self) -> DISABLE_W<'_>

Bit 1 - ICM Disable Register

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 2 - Software Reset

pub fn rehash(&mut self) -> REHASH_W<'_>

Bits 4:7 - Recompute Internal Hash

pub fn rmdis(&mut self) -> RMDIS_W<'_>

Bits 8:11 - Region Monitoring Disable

pub fn rmen(&mut self) -> RMEN_W<'_>

Bits 12:15 - Region Monitoring Enable

impl W<u32, Reg<u32, _IER>>

pub fn rhc(&mut self) -> RHC_W<'_>

Bits 0:3 - Region Hash Completed Interrupt Enable

pub fn rdm(&mut self) -> RDM_W<'_>

Bits 4:7 - Region Digest Mismatch Interrupt Enable

pub fn rbe(&mut self) -> RBE_W<'_>

Bits 8:11 - Region Bus Error Interrupt Enable

pub fn rwc(&mut self) -> RWC_W<'_>

Bits 12:15 - Region Wrap Condition detected Interrupt Enable

pub fn rec(&mut self) -> REC_W<'_>

Bits 16:19 - Region End bit Condition Detected Interrupt Enable

pub fn rsu(&mut self) -> RSU_W<'_>

Bits 20:23 - Region Status Updated Interrupt Disable

pub fn urad(&mut self) -> URAD_W<'_>

Bit 24 - Undefined Register Access Detection Interrupt Enable

impl W<u32, Reg<u32, _IDR>>

pub fn rhc(&mut self) -> RHC_W<'_>

Bits 0:3 - Region Hash Completed Interrupt Disable

pub fn rdm(&mut self) -> RDM_W<'_>

Bits 4:7 - Region Digest Mismatch Interrupt Disable

pub fn rbe(&mut self) -> RBE_W<'_>

Bits 8:11 - Region Bus Error Interrupt Disable

pub fn rwc(&mut self) -> RWC_W<'_>

Bits 12:15 - Region Wrap Condition Detected Interrupt Disable

pub fn rec(&mut self) -> REC_W<'_>

Bits 16:19 - Region End bit Condition detected Interrupt Disable

pub fn rsu(&mut self) -> RSU_W<'_>

Bits 20:23 - Region Status Updated Interrupt Disable

pub fn urad(&mut self) -> URAD_W<'_>

Bit 24 - Undefined Register Access Detection Interrupt Disable

impl W<u32, Reg<u32, _DSCR>>

pub fn dasa(&mut self) -> DASA_W<'_>

Bits 6:31 - Descriptor Area Start Address

impl W<u32, Reg<u32, _HASH>>

pub fn hasa(&mut self) -> HASA_W<'_>

Bits 7:31 - Hash Area Start Address

impl W<u32, Reg<u32, _UIHVAL>>

pub fn val(&mut self) -> VAL_W<'_>

Bits 0:31 - Initial Hash Value

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn cken0(&mut self) -> CKEN0_W<'_>

Bit 2 - Clock Unit 0 Enable

pub fn cken1(&mut self) -> CKEN1_W<'_>

Bit 3 - Clock Unit 1 Enable

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 4 - Tx Serializer Enable

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 5 - Rx Serializer Enable

impl W<u32, Reg<u32, _CLKCTRL>>

pub fn slotsize(&mut self) -> SLOTSIZE_W<'_>

Bits 0:1 - Slot Size

pub fn nbslots(&mut self) -> NBSLOTS_W<'_>

Bits 2:4 - Number of Slots in Frame

pub fn fswidth(&mut self) -> FSWIDTH_W<'_>

Bits 5:6 - Frame Sync Width

pub fn bitdelay(&mut self) -> BITDELAY_W<'_>

Bit 7 - Data Delay from Frame Sync

pub fn fssel(&mut self) -> FSSEL_W<'_>

Bit 8 - Frame Sync Select

pub fn fsinv(&mut self) -> FSINV_W<'_>

Bit 9 - Frame Sync Invert

pub fn fsoutinv(&mut self) -> FSOUTINV_W<'_>

Bit 10 - Frame Sync Output Invert

pub fn scksel(&mut self) -> SCKSEL_W<'_>

Bit 11 - Serial Clock Select

pub fn sckoutinv(&mut self) -> SCKOUTINV_W<'_>

Bit 12 - Serial Clock Output Invert

pub fn mcksel(&mut self) -> MCKSEL_W<'_>

Bit 13 - Master Clock Select

pub fn mcken(&mut self) -> MCKEN_W<'_>

Bit 14 - Master Clock Enable

pub fn mckoutinv(&mut self) -> MCKOUTINV_W<'_>

Bit 15 - Master Clock Output Invert

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 16:21 - Master Clock Division Factor

pub fn mckoutdiv(&mut self) -> MCKOUTDIV_W<'_>

Bits 24:29 - Master Clock Output Division Factor

impl W<u16, Reg<u16, _INTENCLR>>

pub fn rxrdy0(&mut self) -> RXRDY0_W<'_>

Bit 0 - Receive Ready 0 Interrupt Enable

pub fn rxrdy1(&mut self) -> RXRDY1_W<'_>

Bit 1 - Receive Ready 1 Interrupt Enable

pub fn rxor0(&mut self) -> RXOR0_W<'_>

Bit 4 - Receive Overrun 0 Interrupt Enable

pub fn rxor1(&mut self) -> RXOR1_W<'_>

Bit 5 - Receive Overrun 1 Interrupt Enable

pub fn txrdy0(&mut self) -> TXRDY0_W<'_>

Bit 8 - Transmit Ready 0 Interrupt Enable

pub fn txrdy1(&mut self) -> TXRDY1_W<'_>

Bit 9 - Transmit Ready 1 Interrupt Enable

pub fn txur0(&mut self) -> TXUR0_W<'_>

Bit 12 - Transmit Underrun 0 Interrupt Enable

pub fn txur1(&mut self) -> TXUR1_W<'_>

Bit 13 - Transmit Underrun 1 Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn rxrdy0(&mut self) -> RXRDY0_W<'_>

Bit 0 - Receive Ready 0 Interrupt Enable

pub fn rxrdy1(&mut self) -> RXRDY1_W<'_>

Bit 1 - Receive Ready 1 Interrupt Enable

pub fn rxor0(&mut self) -> RXOR0_W<'_>

Bit 4 - Receive Overrun 0 Interrupt Enable

pub fn rxor1(&mut self) -> RXOR1_W<'_>

Bit 5 - Receive Overrun 1 Interrupt Enable

pub fn txrdy0(&mut self) -> TXRDY0_W<'_>

Bit 8 - Transmit Ready 0 Interrupt Enable

pub fn txrdy1(&mut self) -> TXRDY1_W<'_>

Bit 9 - Transmit Ready 1 Interrupt Enable

pub fn txur0(&mut self) -> TXUR0_W<'_>

Bit 12 - Transmit Underrun 0 Interrupt Enable

pub fn txur1(&mut self) -> TXUR1_W<'_>

Bit 13 - Transmit Underrun 1 Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn rxrdy0(&mut self) -> RXRDY0_W<'_>

Bit 0 - Receive Ready 0

pub fn rxrdy1(&mut self) -> RXRDY1_W<'_>

Bit 1 - Receive Ready 1

pub fn rxor0(&mut self) -> RXOR0_W<'_>

Bit 4 - Receive Overrun 0

pub fn rxor1(&mut self) -> RXOR1_W<'_>

Bit 5 - Receive Overrun 1

pub fn txrdy0(&mut self) -> TXRDY0_W<'_>

Bit 8 - Transmit Ready 0

pub fn txrdy1(&mut self) -> TXRDY1_W<'_>

Bit 9 - Transmit Ready 1

pub fn txur0(&mut self) -> TXUR0_W<'_>

Bit 12 - Transmit Underrun 0

pub fn txur1(&mut self) -> TXUR1_W<'_>

Bit 13 - Transmit Underrun 1

impl W<u32, Reg<u32, _TXCTRL>>

pub fn txdefault(&mut self) -> TXDEFAULT_W<'_>

Bits 2:3 - Line Default Line when Slot Disabled

pub fn txsame(&mut self) -> TXSAME_W<'_>

Bit 4 - Transmit Data when Underrun

pub fn slotadj(&mut self) -> SLOTADJ_W<'_>

Bit 7 - Data Slot Formatting Adjust

pub fn datasize(&mut self) -> DATASIZE_W<'_>

Bits 8:10 - Data Word Size

pub fn wordadj(&mut self) -> WORDADJ_W<'_>

Bit 12 - Data Word Formatting Adjust

pub fn extend(&mut self) -> EXTEND_W<'_>

Bits 13:14 - Data Formatting Bit Extension

pub fn bitrev(&mut self) -> BITREV_W<'_>

Bit 15 - Data Formatting Bit Reverse

pub fn slotdis0(&mut self) -> SLOTDIS0_W<'_>

Bit 16 - Slot 0 Disabled for this Serializer

pub fn slotdis1(&mut self) -> SLOTDIS1_W<'_>

Bit 17 - Slot 1 Disabled for this Serializer

pub fn slotdis2(&mut self) -> SLOTDIS2_W<'_>

Bit 18 - Slot 2 Disabled for this Serializer

pub fn slotdis3(&mut self) -> SLOTDIS3_W<'_>

Bit 19 - Slot 3 Disabled for this Serializer

pub fn slotdis4(&mut self) -> SLOTDIS4_W<'_>

Bit 20 - Slot 4 Disabled for this Serializer

pub fn slotdis5(&mut self) -> SLOTDIS5_W<'_>

Bit 21 - Slot 5 Disabled for this Serializer

pub fn slotdis6(&mut self) -> SLOTDIS6_W<'_>

Bit 22 - Slot 6 Disabled for this Serializer

pub fn slotdis7(&mut self) -> SLOTDIS7_W<'_>

Bit 23 - Slot 7 Disabled for this Serializer

pub fn mono(&mut self) -> MONO_W<'_>

Bit 24 - Mono Mode

pub fn dma(&mut self) -> DMA_W<'_>

Bit 25 - Single or Multiple DMA Channels

impl W<u32, Reg<u32, _RXCTRL>>

pub fn sermode(&mut self) -> SERMODE_W<'_>

Bits 0:1 - Serializer Mode

pub fn clksel(&mut self) -> CLKSEL_W<'_>

Bit 5 - Clock Unit Selection

pub fn slotadj(&mut self) -> SLOTADJ_W<'_>

Bit 7 - Data Slot Formatting Adjust

pub fn datasize(&mut self) -> DATASIZE_W<'_>

Bits 8:10 - Data Word Size

pub fn wordadj(&mut self) -> WORDADJ_W<'_>

Bit 12 - Data Word Formatting Adjust

pub fn extend(&mut self) -> EXTEND_W<'_>

Bits 13:14 - Data Formatting Bit Extension

pub fn bitrev(&mut self) -> BITREV_W<'_>

Bit 15 - Data Formatting Bit Reverse

pub fn slotdis0(&mut self) -> SLOTDIS0_W<'_>

Bit 16 - Slot 0 Disabled for this Serializer

pub fn slotdis1(&mut self) -> SLOTDIS1_W<'_>

Bit 17 - Slot 1 Disabled for this Serializer

pub fn slotdis2(&mut self) -> SLOTDIS2_W<'_>

Bit 18 - Slot 2 Disabled for this Serializer

pub fn slotdis3(&mut self) -> SLOTDIS3_W<'_>

Bit 19 - Slot 3 Disabled for this Serializer

pub fn slotdis4(&mut self) -> SLOTDIS4_W<'_>

Bit 20 - Slot 4 Disabled for this Serializer

pub fn slotdis5(&mut self) -> SLOTDIS5_W<'_>

Bit 21 - Slot 5 Disabled for this Serializer

pub fn slotdis6(&mut self) -> SLOTDIS6_W<'_>

Bit 22 - Slot 6 Disabled for this Serializer

pub fn slotdis7(&mut self) -> SLOTDIS7_W<'_>

Bit 23 - Slot 7 Disabled for this Serializer

pub fn mono(&mut self) -> MONO_W<'_>

Bit 24 - Mono Mode

pub fn dma(&mut self) -> DMA_W<'_>

Bit 25 - Single or Multiple DMA Channels

pub fn rxloop(&mut self) -> RXLOOP_W<'_>

Bit 26 - Loop-back Test Mode

impl W<u32, Reg<u32, _TXDATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Sample Data

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ckrdy(&mut self) -> CKRDY_W<'_>

Bit 0 - Clock Ready

impl W<u8, Reg<u8, _CPUDIV>>

pub fn div(&mut self) -> DIV_W<'_>

Bits 0:7 - Low-Power Clock Division Factor

impl W<u32, Reg<u32, _AHBMASK>>

pub fn hpb0_(&mut self) -> HPB0__W<'_>

Bit 0 - HPB0 AHB Clock Mask

pub fn hpb1_(&mut self) -> HPB1__W<'_>

Bit 1 - HPB1 AHB Clock Mask

pub fn hpb2_(&mut self) -> HPB2__W<'_>

Bit 2 - HPB2 AHB Clock Mask

pub fn hpb3_(&mut self) -> HPB3__W<'_>

Bit 3 - HPB3 AHB Clock Mask

pub fn dsu_(&mut self) -> DSU__W<'_>

Bit 4 - DSU AHB Clock Mask

pub fn hmatrix_(&mut self) -> HMATRIX__W<'_>

Bit 5 - HMATRIX AHB Clock Mask

pub fn nvmctrl_(&mut self) -> NVMCTRL__W<'_>

Bit 6 - NVMCTRL AHB Clock Mask

pub fn hsram_(&mut self) -> HSRAM__W<'_>

Bit 7 - HSRAM AHB Clock Mask

pub fn cmcc_(&mut self) -> CMCC__W<'_>

Bit 8 - CMCC AHB Clock Mask

pub fn dmac_(&mut self) -> DMAC__W<'_>

Bit 9 - DMAC AHB Clock Mask

pub fn usb_(&mut self) -> USB__W<'_>

Bit 10 - USB AHB Clock Mask

pub fn bkupram_(&mut self) -> BKUPRAM__W<'_>

Bit 11 - BKUPRAM AHB Clock Mask

pub fn pac_(&mut self) -> PAC__W<'_>

Bit 12 - PAC AHB Clock Mask

pub fn qspi_(&mut self) -> QSPI__W<'_>

Bit 13 - QSPI AHB Clock Mask

pub fn gmac_(&mut self) -> GMAC__W<'_>

Bit 14 - GMAC AHB Clock Mask

pub fn sdhc0_(&mut self) -> SDHC0__W<'_>

Bit 15 - SDHC0 AHB Clock Mask

pub fn sdhc1_(&mut self) -> SDHC1__W<'_>

Bit 16 - SDHC1 AHB Clock Mask

pub fn can0_(&mut self) -> CAN0__W<'_>

Bit 17 - CAN0 AHB Clock Mask

pub fn can1_(&mut self) -> CAN1__W<'_>

Bit 18 - CAN1 AHB Clock Mask

pub fn icm_(&mut self) -> ICM__W<'_>

Bit 19 - ICM AHB Clock Mask

pub fn pukcc_(&mut self) -> PUKCC__W<'_>

Bit 20 - PUKCC AHB Clock Mask

pub fn qspi_2x_(&mut self) -> QSPI_2X__W<'_>

Bit 21 - QSPI_2X AHB Clock Mask

pub fn nvmctrl_smeeprom_(&mut self) -> NVMCTRL_SMEEPROM__W<'_>

Bit 22 - NVMCTRL_SMEEPROM AHB Clock Mask

pub fn nvmctrl_cache_(&mut self) -> NVMCTRL_CACHE__W<'_>

Bit 23 - NVMCTRL_CACHE AHB Clock Mask

impl W<u32, Reg<u32, _APBAMASK>>

pub fn pac_(&mut self) -> PAC__W<'_>

Bit 0 - PAC APB Clock Enable

pub fn pm_(&mut self) -> PM__W<'_>

Bit 1 - PM APB Clock Enable

pub fn mclk_(&mut self) -> MCLK__W<'_>

Bit 2 - MCLK APB Clock Enable

pub fn rstc_(&mut self) -> RSTC__W<'_>

Bit 3 - RSTC APB Clock Enable

pub fn oscctrl_(&mut self) -> OSCCTRL__W<'_>

Bit 4 - OSCCTRL APB Clock Enable

pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W<'_>

Bit 5 - OSC32KCTRL APB Clock Enable

pub fn supc_(&mut self) -> SUPC__W<'_>

Bit 6 - SUPC APB Clock Enable

pub fn gclk_(&mut self) -> GCLK__W<'_>

Bit 7 - GCLK APB Clock Enable

pub fn wdt_(&mut self) -> WDT__W<'_>

Bit 8 - WDT APB Clock Enable

pub fn rtc_(&mut self) -> RTC__W<'_>

Bit 9 - RTC APB Clock Enable

pub fn eic_(&mut self) -> EIC__W<'_>

Bit 10 - EIC APB Clock Enable

pub fn freqm_(&mut self) -> FREQM__W<'_>

Bit 11 - FREQM APB Clock Enable

pub fn sercom0_(&mut self) -> SERCOM0__W<'_>

Bit 12 - SERCOM0 APB Clock Enable

pub fn sercom1_(&mut self) -> SERCOM1__W<'_>

Bit 13 - SERCOM1 APB Clock Enable

pub fn tc0_(&mut self) -> TC0__W<'_>

Bit 14 - TC0 APB Clock Enable

pub fn tc1_(&mut self) -> TC1__W<'_>

Bit 15 - TC1 APB Clock Enable

impl W<u32, Reg<u32, _APBBMASK>>

pub fn usb_(&mut self) -> USB__W<'_>

Bit 0 - USB APB Clock Enable

pub fn dsu_(&mut self) -> DSU__W<'_>

Bit 1 - DSU APB Clock Enable

pub fn nvmctrl_(&mut self) -> NVMCTRL__W<'_>

Bit 2 - NVMCTRL APB Clock Enable

pub fn port_(&mut self) -> PORT__W<'_>

Bit 4 - PORT APB Clock Enable

pub fn hmatrix_(&mut self) -> HMATRIX__W<'_>

Bit 6 - HMATRIX APB Clock Enable

pub fn evsys_(&mut self) -> EVSYS__W<'_>

Bit 7 - EVSYS APB Clock Enable

pub fn sercom2_(&mut self) -> SERCOM2__W<'_>

Bit 9 - SERCOM2 APB Clock Enable

pub fn sercom3_(&mut self) -> SERCOM3__W<'_>

Bit 10 - SERCOM3 APB Clock Enable

pub fn tcc0_(&mut self) -> TCC0__W<'_>

Bit 11 - TCC0 APB Clock Enable

pub fn tcc1_(&mut self) -> TCC1__W<'_>

Bit 12 - TCC1 APB Clock Enable

pub fn tc2_(&mut self) -> TC2__W<'_>

Bit 13 - TC2 APB Clock Enable

pub fn tc3_(&mut self) -> TC3__W<'_>

Bit 14 - TC3 APB Clock Enable

pub fn ramecc_(&mut self) -> RAMECC__W<'_>

Bit 16 - RAMECC APB Clock Enable

impl W<u32, Reg<u32, _APBCMASK>>

pub fn gmac_(&mut self) -> GMAC__W<'_>

Bit 2 - GMAC APB Clock Enable

pub fn tcc2_(&mut self) -> TCC2__W<'_>

Bit 3 - TCC2 APB Clock Enable

pub fn tcc3_(&mut self) -> TCC3__W<'_>

Bit 4 - TCC3 APB Clock Enable

pub fn tc4_(&mut self) -> TC4__W<'_>

Bit 5 - TC4 APB Clock Enable

pub fn tc5_(&mut self) -> TC5__W<'_>

Bit 6 - TC5 APB Clock Enable

pub fn pdec_(&mut self) -> PDEC__W<'_>

Bit 7 - PDEC APB Clock Enable

pub fn ac_(&mut self) -> AC__W<'_>

Bit 8 - AC APB Clock Enable

pub fn aes_(&mut self) -> AES__W<'_>

Bit 9 - AES APB Clock Enable

pub fn trng_(&mut self) -> TRNG__W<'_>

Bit 10 - TRNG APB Clock Enable

pub fn icm_(&mut self) -> ICM__W<'_>

Bit 11 - ICM APB Clock Enable

pub fn qspi_(&mut self) -> QSPI__W<'_>

Bit 13 - QSPI APB Clock Enable

pub fn ccl_(&mut self) -> CCL__W<'_>

Bit 14 - CCL APB Clock Enable

impl W<u32, Reg<u32, _APBDMASK>>

pub fn sercom4_(&mut self) -> SERCOM4__W<'_>

Bit 0 - SERCOM4 APB Clock Enable

pub fn sercom5_(&mut self) -> SERCOM5__W<'_>

Bit 1 - SERCOM5 APB Clock Enable

pub fn sercom6_(&mut self) -> SERCOM6__W<'_>

Bit 2 - SERCOM6 APB Clock Enable

pub fn sercom7_(&mut self) -> SERCOM7__W<'_>

Bit 3 - SERCOM7 APB Clock Enable

pub fn tcc4_(&mut self) -> TCC4__W<'_>

Bit 4 - TCC4 APB Clock Enable

pub fn tc6_(&mut self) -> TC6__W<'_>

Bit 5 - TC6 APB Clock Enable

pub fn tc7_(&mut self) -> TC7__W<'_>

Bit 6 - TC7 APB Clock Enable

pub fn adc0_(&mut self) -> ADC0__W<'_>

Bit 7 - ADC0 APB Clock Enable

pub fn adc1_(&mut self) -> ADC1__W<'_>

Bit 8 - ADC1 APB Clock Enable

pub fn dac_(&mut self) -> DAC__W<'_>

Bit 9 - DAC APB Clock Enable

pub fn i2s_(&mut self) -> I2S__W<'_>

Bit 10 - I2S APB Clock Enable

pub fn pcc_(&mut self) -> PCC__W<'_>

Bit 11 - PCC APB Clock Enable

impl W<u16, Reg<u16, _CTRLA>>

pub fn autows(&mut self) -> AUTOWS_W<'_>

Bit 2 - Auto Wait State Enable

pub fn suspen(&mut self) -> SUSPEN_W<'_>

Bit 3 - Suspend Enable

pub fn wmode(&mut self) -> WMODE_W<'_>

Bits 4:5 - Write Mode

pub fn prm(&mut self) -> PRM_W<'_>

Bits 6:7 - Power Reduction Mode during Sleep

pub fn rws(&mut self) -> RWS_W<'_>

Bits 8:11 - NVM Read Wait States

pub fn ahbns0(&mut self) -> AHBNS0_W<'_>

Bit 12 - Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated

pub fn ahbns1(&mut self) -> AHBNS1_W<'_>

Bit 13 - Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated

pub fn cachedis0(&mut self) -> CACHEDIS0_W<'_>

Bit 14 - AHB0 Cache Disable

pub fn cachedis1(&mut self) -> CACHEDIS1_W<'_>

Bit 15 - AHB1 Cache Disable

impl W<u16, Reg<u16, _CTRLB>>

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 0:6 - Command

pub fn cmdex(&mut self) -> CMDEX_W<'_>

Bits 8:15 - Command Execution

impl W<u16, Reg<u16, _INTENCLR>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Command Done Interrupt Clear

pub fn addre(&mut self) -> ADDRE_W<'_>

Bit 1 - Address Error

pub fn proge(&mut self) -> PROGE_W<'_>

Bit 2 - Programming Error Interrupt Clear

pub fn locke(&mut self) -> LOCKE_W<'_>

Bit 3 - Lock Error Interrupt Clear

pub fn eccse(&mut self) -> ECCSE_W<'_>

Bit 4 - ECC Single Error Interrupt Clear

pub fn eccde(&mut self) -> ECCDE_W<'_>

Bit 5 - ECC Dual Error Interrupt Clear

pub fn nvme(&mut self) -> NVME_W<'_>

Bit 6 - NVM Error Interrupt Clear

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 7 - Suspended Write Or Erase Interrupt Clear

pub fn seesfull(&mut self) -> SEESFULL_W<'_>

Bit 8 - Active SEES Full Interrupt Clear

pub fn seesovf(&mut self) -> SEESOVF_W<'_>

Bit 9 - Active SEES Overflow Interrupt Clear

pub fn seewrc(&mut self) -> SEEWRC_W<'_>

Bit 10 - SEE Write Completed Interrupt Clear

impl W<u16, Reg<u16, _INTENSET>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Command Done Interrupt Enable

pub fn addre(&mut self) -> ADDRE_W<'_>

Bit 1 - Address Error Interrupt Enable

pub fn proge(&mut self) -> PROGE_W<'_>

Bit 2 - Programming Error Interrupt Enable

pub fn locke(&mut self) -> LOCKE_W<'_>

Bit 3 - Lock Error Interrupt Enable

pub fn eccse(&mut self) -> ECCSE_W<'_>

Bit 4 - ECC Single Error Interrupt Enable

pub fn eccde(&mut self) -> ECCDE_W<'_>

Bit 5 - ECC Dual Error Interrupt Enable

pub fn nvme(&mut self) -> NVME_W<'_>

Bit 6 - NVM Error Interrupt Enable

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 7 - Suspended Write Or Erase Interrupt Enable

pub fn seesfull(&mut self) -> SEESFULL_W<'_>

Bit 8 - Active SEES Full Interrupt Enable

pub fn seesovf(&mut self) -> SEESOVF_W<'_>

Bit 9 - Active SEES Overflow Interrupt Enable

pub fn seewrc(&mut self) -> SEEWRC_W<'_>

Bit 10 - SEE Write Completed Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn done(&mut self) -> DONE_W<'_>

Bit 0 - Command Done

pub fn addre(&mut self) -> ADDRE_W<'_>

Bit 1 - Address Error

pub fn proge(&mut self) -> PROGE_W<'_>

Bit 2 - Programming Error

pub fn locke(&mut self) -> LOCKE_W<'_>

Bit 3 - Lock Error

pub fn eccse(&mut self) -> ECCSE_W<'_>

Bit 4 - ECC Single Error

pub fn eccde(&mut self) -> ECCDE_W<'_>

Bit 5 - ECC Dual Error

pub fn nvme(&mut self) -> NVME_W<'_>

Bit 6 - NVM Error

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 7 - Suspended Write Or Erase Operation

pub fn seesfull(&mut self) -> SEESFULL_W<'_>

Bit 8 - Active SEES Full

pub fn seesovf(&mut self) -> SEESOVF_W<'_>

Bit 9 - Active SEES Overflow

pub fn seewrc(&mut self) -> SEEWRC_W<'_>

Bit 10 - SEE Write Completed

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:23 - NVM Address

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn eccdis(&mut self) -> ECCDIS_W<'_>

Bit 0 - Debugger ECC Read Disable

pub fn eccelog(&mut self) -> ECCELOG_W<'_>

Bit 1 - Debugger ECC Error Tracking Mode

impl W<u8, Reg<u8, _SEECFG>>

pub fn wmode(&mut self) -> WMODE_W<'_>

Bit 0 - Write Mode

pub fn aprdis(&mut self) -> APRDIS_W<'_>

Bit 1 - Automatic Page Reallocation Disable

impl W<u8, Reg<u8, _DPLLCTRLA>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - DPLL Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

impl W<u32, Reg<u32, _DPLLRATIO>>

pub fn ldr(&mut self) -> LDR_W<'_>

Bits 0:12 - Loop Divider Ratio

pub fn ldrfrac(&mut self) -> LDRFRAC_W<'_>

Bits 16:20 - Loop Divider Ratio Fractional Part

impl W<u32, Reg<u32, _DPLLCTRLB>>

pub fn filter(&mut self) -> FILTER_W<'_>

Bits 0:3 - Proportional Integral Filter Selection

pub fn wuf(&mut self) -> WUF_W<'_>

Bit 4 - Wake Up Fast

pub fn refclk(&mut self) -> REFCLK_W<'_>

Bits 5:7 - Reference Clock Selection

pub fn ltime(&mut self) -> LTIME_W<'_>

Bits 8:10 - Lock Time

pub fn lbypass(&mut self) -> LBYPASS_W<'_>

Bit 11 - Lock Bypass

pub fn dcofilter(&mut self) -> DCOFILTER_W<'_>

Bits 12:14 - Sigma-Delta DCO Filter Selection

pub fn dcoen(&mut self) -> DCOEN_W<'_>

Bit 15 - DCO Filter Enable

pub fn div(&mut self) -> DIV_W<'_>

Bits 16:26 - Clock Divider

impl W<u8, Reg<u8, _EVCTRL>>

pub fn cfdeo0(&mut self) -> CFDEO0_W<'_>

Bit 0 - Clock 0 Failure Detector Event Output Enable

pub fn cfdeo1(&mut self) -> CFDEO1_W<'_>

Bit 1 - Clock 1 Failure Detector Event Output Enable

impl W<u32, Reg<u32, _INTENCLR>>

pub fn xoscrdy0(&mut self) -> XOSCRDY0_W<'_>

Bit 0 - XOSC 0 Ready Interrupt Enable

pub fn xoscrdy1(&mut self) -> XOSCRDY1_W<'_>

Bit 1 - XOSC 1 Ready Interrupt Enable

pub fn xoscfail0(&mut self) -> XOSCFAIL0_W<'_>

Bit 2 - XOSC 0 Clock Failure Detector Interrupt Enable

pub fn xoscfail1(&mut self) -> XOSCFAIL1_W<'_>

Bit 3 - XOSC 1 Clock Failure Detector Interrupt Enable

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 8 - DFLL Ready Interrupt Enable

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 9 - DFLL Out Of Bounds Interrupt Enable

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 10 - DFLL Lock Fine Interrupt Enable

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 11 - DFLL Lock Coarse Interrupt Enable

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 12 - DFLL Reference Clock Stopped Interrupt Enable

pub fn dpll0lckr(&mut self) -> DPLL0LCKR_W<'_>

Bit 16 - DPLL0 Lock Rise Interrupt Enable

pub fn dpll0lckf(&mut self) -> DPLL0LCKF_W<'_>

Bit 17 - DPLL0 Lock Fall Interrupt Enable

pub fn dpll0lto(&mut self) -> DPLL0LTO_W<'_>

Bit 18 - DPLL0 Lock Timeout Interrupt Enable

pub fn dpll0ldrto(&mut self) -> DPLL0LDRTO_W<'_>

Bit 19 - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable

pub fn dpll1lckr(&mut self) -> DPLL1LCKR_W<'_>

Bit 24 - DPLL1 Lock Rise Interrupt Enable

pub fn dpll1lckf(&mut self) -> DPLL1LCKF_W<'_>

Bit 25 - DPLL1 Lock Fall Interrupt Enable

pub fn dpll1lto(&mut self) -> DPLL1LTO_W<'_>

Bit 26 - DPLL1 Lock Timeout Interrupt Enable

pub fn dpll1ldrto(&mut self) -> DPLL1LDRTO_W<'_>

Bit 27 - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn xoscrdy0(&mut self) -> XOSCRDY0_W<'_>

Bit 0 - XOSC 0 Ready Interrupt Enable

pub fn xoscrdy1(&mut self) -> XOSCRDY1_W<'_>

Bit 1 - XOSC 1 Ready Interrupt Enable

pub fn xoscfail0(&mut self) -> XOSCFAIL0_W<'_>

Bit 2 - XOSC 0 Clock Failure Detector Interrupt Enable

pub fn xoscfail1(&mut self) -> XOSCFAIL1_W<'_>

Bit 3 - XOSC 1 Clock Failure Detector Interrupt Enable

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 8 - DFLL Ready Interrupt Enable

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 9 - DFLL Out Of Bounds Interrupt Enable

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 10 - DFLL Lock Fine Interrupt Enable

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 11 - DFLL Lock Coarse Interrupt Enable

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 12 - DFLL Reference Clock Stopped Interrupt Enable

pub fn dpll0lckr(&mut self) -> DPLL0LCKR_W<'_>

Bit 16 - DPLL0 Lock Rise Interrupt Enable

pub fn dpll0lckf(&mut self) -> DPLL0LCKF_W<'_>

Bit 17 - DPLL0 Lock Fall Interrupt Enable

pub fn dpll0lto(&mut self) -> DPLL0LTO_W<'_>

Bit 18 - DPLL0 Lock Timeout Interrupt Enable

pub fn dpll0ldrto(&mut self) -> DPLL0LDRTO_W<'_>

Bit 19 - DPLL0 Loop Divider Ratio Update Complete Interrupt Enable

pub fn dpll1lckr(&mut self) -> DPLL1LCKR_W<'_>

Bit 24 - DPLL1 Lock Rise Interrupt Enable

pub fn dpll1lckf(&mut self) -> DPLL1LCKF_W<'_>

Bit 25 - DPLL1 Lock Fall Interrupt Enable

pub fn dpll1lto(&mut self) -> DPLL1LTO_W<'_>

Bit 26 - DPLL1 Lock Timeout Interrupt Enable

pub fn dpll1ldrto(&mut self) -> DPLL1LDRTO_W<'_>

Bit 27 - DPLL1 Loop Divider Ratio Update Complete Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn xoscrdy0(&mut self) -> XOSCRDY0_W<'_>

Bit 0 - XOSC 0 Ready

pub fn xoscrdy1(&mut self) -> XOSCRDY1_W<'_>

Bit 1 - XOSC 1 Ready

pub fn xoscfail0(&mut self) -> XOSCFAIL0_W<'_>

Bit 2 - XOSC 0 Clock Failure Detector

pub fn xoscfail1(&mut self) -> XOSCFAIL1_W<'_>

Bit 3 - XOSC 1 Clock Failure Detector

pub fn dfllrdy(&mut self) -> DFLLRDY_W<'_>

Bit 8 - DFLL Ready

pub fn dflloob(&mut self) -> DFLLOOB_W<'_>

Bit 9 - DFLL Out Of Bounds

pub fn dflllckf(&mut self) -> DFLLLCKF_W<'_>

Bit 10 - DFLL Lock Fine

pub fn dflllckc(&mut self) -> DFLLLCKC_W<'_>

Bit 11 - DFLL Lock Coarse

pub fn dfllrcs(&mut self) -> DFLLRCS_W<'_>

Bit 12 - DFLL Reference Clock Stopped

pub fn dpll0lckr(&mut self) -> DPLL0LCKR_W<'_>

Bit 16 - DPLL0 Lock Rise

pub fn dpll0lckf(&mut self) -> DPLL0LCKF_W<'_>

Bit 17 - DPLL0 Lock Fall

pub fn dpll0lto(&mut self) -> DPLL0LTO_W<'_>

Bit 18 - DPLL0 Lock Timeout

pub fn dpll0ldrto(&mut self) -> DPLL0LDRTO_W<'_>

Bit 19 - DPLL0 Loop Divider Ratio Update Complete

pub fn dpll1lckr(&mut self) -> DPLL1LCKR_W<'_>

Bit 24 - DPLL1 Lock Rise

pub fn dpll1lckf(&mut self) -> DPLL1LCKF_W<'_>

Bit 25 - DPLL1 Lock Fall

pub fn dpll1lto(&mut self) -> DPLL1LTO_W<'_>

Bit 26 - DPLL1 Lock Timeout

pub fn dpll1ldrto(&mut self) -> DPLL1LDRTO_W<'_>

Bit 27 - DPLL1 Loop Divider Ratio Update Complete

impl W<u32, Reg<u32, _XOSCCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn xtalen(&mut self) -> XTALEN_W<'_>

Bit 2 - Crystal Oscillator Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn lowbufgain(&mut self) -> LOWBUFGAIN_W<'_>

Bit 8 - Low Buffer Gain Enable

pub fn iptat(&mut self) -> IPTAT_W<'_>

Bits 9:10 - Oscillator Current Reference

pub fn imult(&mut self) -> IMULT_W<'_>

Bits 11:14 - Oscillator Current Multiplier

pub fn enalc(&mut self) -> ENALC_W<'_>

Bit 15 - Automatic Loop Control Enable

pub fn cfden(&mut self) -> CFDEN_W<'_>

Bit 16 - Clock Failure Detector Enable

pub fn swben(&mut self) -> SWBEN_W<'_>

Bit 17 - Xosc Clock Switch Enable

pub fn startup(&mut self) -> STARTUP_W<'_>

Bits 20:23 - Start-Up Time

pub fn cfdpresc(&mut self) -> CFDPRESC_W<'_>

Bits 24:27 - Clock Failure Detector Prescaler

impl W<u8, Reg<u8, _DFLLCTRLA>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - DFLL Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

impl W<u8, Reg<u8, _DFLLCTRLB>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - Operating Mode Selection

pub fn stable(&mut self) -> STABLE_W<'_>

Bit 1 - Stable DFLL Frequency

pub fn llaw(&mut self) -> LLAW_W<'_>

Bit 2 - Lose Lock After Wake

pub fn usbcrm(&mut self) -> USBCRM_W<'_>

Bit 3 - USB Clock Recovery Mode

pub fn ccdis(&mut self) -> CCDIS_W<'_>

Bit 4 - Chill Cycle Disable

pub fn qldis(&mut self) -> QLDIS_W<'_>

Bit 5 - Quick Lock Disable

pub fn bplckc(&mut self) -> BPLCKC_W<'_>

Bit 6 - Bypass Coarse Lock

pub fn waitlock(&mut self) -> WAITLOCK_W<'_>

Bit 7 - Wait Lock

impl W<u32, Reg<u32, _DFLLVAL>>

pub fn fine(&mut self) -> FINE_W<'_>

Bits 0:7 - Fine Value

pub fn coarse(&mut self) -> COARSE_W<'_>

Bits 10:15 - Coarse Value

pub fn diff(&mut self) -> DIFF_W<'_>

Bits 16:31 - Multiplication Ratio Difference

impl W<u32, Reg<u32, _DFLLMUL>>

pub fn mul(&mut self) -> MUL_W<'_>

Bits 0:15 - DFLL Multiply Factor

pub fn fstep(&mut self) -> FSTEP_W<'_>

Bits 16:23 - Fine Maximum Step

pub fn cstep(&mut self) -> CSTEP_W<'_>

Bits 26:31 - Coarse Maximum Step

impl W<u8, Reg<u8, _DFLLSYNC>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - ENABLE Synchronization Busy

pub fn dfllctrlb(&mut self) -> DFLLCTRLB_W<'_>

Bit 2 - DFLLCTRLB Synchronization Busy

pub fn dfllval(&mut self) -> DFLLVAL_W<'_>

Bit 3 - DFLLVAL Synchronization Busy

pub fn dfllmul(&mut self) -> DFLLMUL_W<'_>

Bit 4 - DFLLMUL Synchronization Busy

impl W<u32, Reg<u32, _INTENCLR>>

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 0 - XOSC32K Ready Interrupt Enable

pub fn xosc32kfail(&mut self) -> XOSC32KFAIL_W<'_>

Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 0 - XOSC32K Ready Interrupt Enable

pub fn xosc32kfail(&mut self) -> XOSC32KFAIL_W<'_>

Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<'_>

Bit 0 - XOSC32K Ready

pub fn xosc32kfail(&mut self) -> XOSC32KFAIL_W<'_>

Bit 2 - XOSC32K Clock Failure Detector

impl W<u8, Reg<u8, _RTCCTRL>>

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 0:2 - RTC Clock Selection

impl W<u16, Reg<u16, _XOSC32K>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Oscillator Enable

pub fn xtalen(&mut self) -> XTALEN_W<'_>

Bit 2 - Crystal Oscillator Enable

pub fn en32k(&mut self) -> EN32K_W<'_>

Bit 3 - 32kHz Output Enable

pub fn en1k(&mut self) -> EN1K_W<'_>

Bit 4 - 1kHz Output Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Control

pub fn startup(&mut self) -> STARTUP_W<'_>

Bits 8:10 - Oscillator Start-Up Time

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 12 - Write Lock

pub fn cgm(&mut self) -> CGM_W<'_>

Bits 13:14 - Control Gain Mode

impl W<u8, Reg<u8, _CFDCTRL>>

pub fn cfden(&mut self) -> CFDEN_W<'_>

Bit 0 - Clock Failure Detector Enable

pub fn swback(&mut self) -> SWBACK_W<'_>

Bit 1 - Clock Switch Back

pub fn cfdpresc(&mut self) -> CFDPRESC_W<'_>

Bit 2 - Clock Failure Detector Prescaler

impl W<u8, Reg<u8, _EVCTRL>>

pub fn cfdeo(&mut self) -> CFDEO_W<'_>

Bit 0 - Clock Failure Detector Event Output Enable

impl W<u32, Reg<u32, _OSCULP32K>>

pub fn en32k(&mut self) -> EN32K_W<'_>

Bit 1 - Enable Out 32k

pub fn en1k(&mut self) -> EN1K_W<'_>

Bit 2 - Enable Out 1k

pub fn wrtlock(&mut self) -> WRTLOCK_W<'_>

Bit 15 - Write Lock

impl W<u32, Reg<u32, _WRCTRL>>

pub fn perid(&mut self) -> PERID_W<'_>

Bits 0:15 - Peripheral identifier

pub fn key(&mut self) -> KEY_W<'_>

Bits 16:23 - Peripheral access control key

impl W<u8, Reg<u8, _EVCTRL>>

pub fn erreo(&mut self) -> ERREO_W<'_>

Bit 0 - Peripheral acess error event output

impl W<u8, Reg<u8, _INTENCLR>>

pub fn err(&mut self) -> ERR_W<'_>

Bit 0 - Peripheral access error interrupt disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn err(&mut self) -> ERR_W<'_>

Bit 0 - Peripheral access error interrupt enable

impl W<u32, Reg<u32, _INTFLAGAHB>>

pub fn flash_(&mut self) -> FLASH__W<'_>

Bit 0 - FLASH

pub fn flash_alt_(&mut self) -> FLASH_ALT__W<'_>

Bit 1 - FLASH_ALT

pub fn seeprom_(&mut self) -> SEEPROM__W<'_>

Bit 2 - SEEPROM

pub fn ramcm4s_(&mut self) -> RAMCM4S__W<'_>

Bit 3 - RAMCM4S

pub fn rampppdsu_(&mut self) -> RAMPPPDSU__W<'_>

Bit 4 - RAMPPPDSU

pub fn ramdmawr_(&mut self) -> RAMDMAWR__W<'_>

Bit 5 - RAMDMAWR

pub fn ramdmacicm_(&mut self) -> RAMDMACICM__W<'_>

Bit 6 - RAMDMACICM

pub fn hpb0_(&mut self) -> HPB0__W<'_>

Bit 7 - HPB0

pub fn hpb1_(&mut self) -> HPB1__W<'_>

Bit 8 - HPB1

pub fn hpb2_(&mut self) -> HPB2__W<'_>

Bit 9 - HPB2

pub fn hpb3_(&mut self) -> HPB3__W<'_>

Bit 10 - HPB3

pub fn pukcc_(&mut self) -> PUKCC__W<'_>

Bit 11 - PUKCC

pub fn sdhc0_(&mut self) -> SDHC0__W<'_>

Bit 12 - SDHC0

pub fn sdhc1_(&mut self) -> SDHC1__W<'_>

Bit 13 - SDHC1

pub fn qspi_(&mut self) -> QSPI__W<'_>

Bit 14 - QSPI

pub fn bkupram_(&mut self) -> BKUPRAM__W<'_>

Bit 15 - BKUPRAM

impl W<u32, Reg<u32, _INTFLAGA>>

pub fn pac_(&mut self) -> PAC__W<'_>

Bit 0 - PAC

pub fn pm_(&mut self) -> PM__W<'_>

Bit 1 - PM

pub fn mclk_(&mut self) -> MCLK__W<'_>

Bit 2 - MCLK

pub fn rstc_(&mut self) -> RSTC__W<'_>

Bit 3 - RSTC

pub fn oscctrl_(&mut self) -> OSCCTRL__W<'_>

Bit 4 - OSCCTRL

pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W<'_>

Bit 5 - OSC32KCTRL

pub fn supc_(&mut self) -> SUPC__W<'_>

Bit 6 - SUPC

pub fn gclk_(&mut self) -> GCLK__W<'_>

Bit 7 - GCLK

pub fn wdt_(&mut self) -> WDT__W<'_>

Bit 8 - WDT

pub fn rtc_(&mut self) -> RTC__W<'_>

Bit 9 - RTC

pub fn eic_(&mut self) -> EIC__W<'_>

Bit 10 - EIC

pub fn freqm_(&mut self) -> FREQM__W<'_>

Bit 11 - FREQM

pub fn sercom0_(&mut self) -> SERCOM0__W<'_>

Bit 12 - SERCOM0

pub fn sercom1_(&mut self) -> SERCOM1__W<'_>

Bit 13 - SERCOM1

pub fn tc0_(&mut self) -> TC0__W<'_>

Bit 14 - TC0

pub fn tc1_(&mut self) -> TC1__W<'_>

Bit 15 - TC1

impl W<u32, Reg<u32, _INTFLAGB>>

pub fn usb_(&mut self) -> USB__W<'_>

Bit 0 - USB

pub fn dsu_(&mut self) -> DSU__W<'_>

Bit 1 - DSU

pub fn nvmctrl_(&mut self) -> NVMCTRL__W<'_>

Bit 2 - NVMCTRL

pub fn cmcc_(&mut self) -> CMCC__W<'_>

Bit 3 - CMCC

pub fn port_(&mut self) -> PORT__W<'_>

Bit 4 - PORT

pub fn dmac_(&mut self) -> DMAC__W<'_>

Bit 5 - DMAC

pub fn hmatrix_(&mut self) -> HMATRIX__W<'_>

Bit 6 - HMATRIX

pub fn evsys_(&mut self) -> EVSYS__W<'_>

Bit 7 - EVSYS

pub fn sercom2_(&mut self) -> SERCOM2__W<'_>

Bit 9 - SERCOM2

pub fn sercom3_(&mut self) -> SERCOM3__W<'_>

Bit 10 - SERCOM3

pub fn tcc0_(&mut self) -> TCC0__W<'_>

Bit 11 - TCC0

pub fn tcc1_(&mut self) -> TCC1__W<'_>

Bit 12 - TCC1

pub fn tc2_(&mut self) -> TC2__W<'_>

Bit 13 - TC2

pub fn tc3_(&mut self) -> TC3__W<'_>

Bit 14 - TC3

pub fn ramecc_(&mut self) -> RAMECC__W<'_>

Bit 16 - RAMECC

impl W<u32, Reg<u32, _INTFLAGC>>

pub fn can0_(&mut self) -> CAN0__W<'_>

Bit 0 - CAN0

pub fn can1_(&mut self) -> CAN1__W<'_>

Bit 1 - CAN1

pub fn gmac_(&mut self) -> GMAC__W<'_>

Bit 2 - GMAC

pub fn tcc2_(&mut self) -> TCC2__W<'_>

Bit 3 - TCC2

pub fn tcc3_(&mut self) -> TCC3__W<'_>

Bit 4 - TCC3

pub fn tc4_(&mut self) -> TC4__W<'_>

Bit 5 - TC4

pub fn tc5_(&mut self) -> TC5__W<'_>

Bit 6 - TC5

pub fn pdec_(&mut self) -> PDEC__W<'_>

Bit 7 - PDEC

pub fn ac_(&mut self) -> AC__W<'_>

Bit 8 - AC

pub fn aes_(&mut self) -> AES__W<'_>

Bit 9 - AES

pub fn trng_(&mut self) -> TRNG__W<'_>

Bit 10 - TRNG

pub fn icm_(&mut self) -> ICM__W<'_>

Bit 11 - ICM

pub fn pukcc_(&mut self) -> PUKCC__W<'_>

Bit 12 - PUKCC

pub fn qspi_(&mut self) -> QSPI__W<'_>

Bit 13 - QSPI

pub fn ccl_(&mut self) -> CCL__W<'_>

Bit 14 - CCL

impl W<u32, Reg<u32, _INTFLAGD>>

pub fn sercom4_(&mut self) -> SERCOM4__W<'_>

Bit 0 - SERCOM4

pub fn sercom5_(&mut self) -> SERCOM5__W<'_>

Bit 1 - SERCOM5

pub fn sercom6_(&mut self) -> SERCOM6__W<'_>

Bit 2 - SERCOM6

pub fn sercom7_(&mut self) -> SERCOM7__W<'_>

Bit 3 - SERCOM7

pub fn tcc4_(&mut self) -> TCC4__W<'_>

Bit 4 - TCC4

pub fn tc6_(&mut self) -> TC6__W<'_>

Bit 5 - TC6

pub fn tc7_(&mut self) -> TC7__W<'_>

Bit 6 - TC7

pub fn adc0_(&mut self) -> ADC0__W<'_>

Bit 7 - ADC0

pub fn adc1_(&mut self) -> ADC1__W<'_>

Bit 8 - ADC1

pub fn dac_(&mut self) -> DAC__W<'_>

Bit 9 - DAC

pub fn i2s_(&mut self) -> I2S__W<'_>

Bit 10 - I2S

pub fn pcc_(&mut self) -> PCC__W<'_>

Bit 11 - PCC

impl W<u32, Reg<u32, _MR>>

pub fn pcen(&mut self) -> PCEN_W<'_>

Bit 0 - Parallel Capture Enable

pub fn dsize(&mut self) -> DSIZE_W<'_>

Bits 4:5 - Data size

pub fn scale(&mut self) -> SCALE_W<'_>

Bit 8 - Scale data

pub fn alwys(&mut self) -> ALWYS_W<'_>

Bit 9 - Always Sampling

pub fn halfs(&mut self) -> HALFS_W<'_>

Bit 10 - Half Sampling

pub fn frsts(&mut self) -> FRSTS_W<'_>

Bit 11 - First sample

pub fn isize(&mut self) -> ISIZE_W<'_>

Bits 16:18 - Input Data Size

pub fn cid(&mut self) -> CID_W<'_>

Bits 30:31 - Clear If Disabled

impl W<u32, Reg<u32, _IER>>

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 0 - Data Ready Interrupt Enable

pub fn ovre(&mut self) -> OVRE_W<'_>

Bit 1 - Overrun Error Interrupt Enable

impl W<u32, Reg<u32, _IDR>>

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 0 - Data Ready Interrupt Disable

pub fn ovre(&mut self) -> OVRE_W<'_>

Bit 1 - Overrun Error Interrupt Disable

impl W<u32, Reg<u32, _WPMR>>

pub fn wpen(&mut self) -> WPEN_W<'_>

Bit 0 - Write Protection Enable

pub fn wpkey(&mut self) -> WPKEY_W<'_>

Bits 8:31 - Write Protection Key

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operation Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

pub fn conf(&mut self) -> CONF_W<'_>

Bits 8:10 - PDEC Configuration

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 11 - Auto Lock

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 14 - PDEC Phase A and B Swap

pub fn peren(&mut self) -> PEREN_W<'_>

Bit 15 - Period Enable

pub fn pinen0(&mut self) -> PINEN0_W<'_>

Bit 16 - PDEC Input From Pin 0 Enable

pub fn pinen1(&mut self) -> PINEN1_W<'_>

Bit 17 - PDEC Input From Pin 1 Enable

pub fn pinen2(&mut self) -> PINEN2_W<'_>

Bit 18 - PDEC Input From Pin 2 Enable

pub fn pinven0(&mut self) -> PINVEN0_W<'_>

Bit 20 - IO Pin 0 Invert Enable

pub fn pinven1(&mut self) -> PINVEN1_W<'_>

Bit 21 - IO Pin 1 Invert Enable

pub fn pinven2(&mut self) -> PINVEN2_W<'_>

Bit 22 - IO Pin 2 Invert Enable

pub fn angular(&mut self) -> ANGULAR_W<'_>

Bits 24:26 - Angular Counter Length

pub fn maxcmp(&mut self) -> MAXCMP_W<'_>

Bits 28:31 - Maximum Consecutive Missing Pulses

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:1 - Event Action

pub fn evinv(&mut self) -> EVINV_W<'_>

Bits 2:4 - Inverted Event Input Enable

pub fn evei(&mut self) -> EVEI_W<'_>

Bits 5:7 - Event Input Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Output Event Enable

pub fn erreo(&mut self) -> ERREO_W<'_>

Bit 9 - Error Output Event Enable

pub fn direo(&mut self) -> DIREO_W<'_>

Bit 10 - Direction Output Event Enable

pub fn vlceo(&mut self) -> VLCEO_W<'_>

Bit 11 - Velocity Output Event Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - Match Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - Match Channel 1 Event Output Enable

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow/Underflow Interrupt Disable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Disable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 2 - Direction Interrupt Disable

pub fn vlc(&mut self) -> VLC_W<'_>

Bit 3 - Velocity Interrupt Disable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Channel 0 Compare Match Disable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Channel 1 Compare Match Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow/Underflow Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error Interrupt Enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 2 - Direction Interrupt Enable

pub fn vlc(&mut self) -> VLC_W<'_>

Bit 3 - Velocity Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Channel 0 Compare Match Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Channel 1 Compare Match Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow/Underflow

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - Error

pub fn dir(&mut self) -> DIR_W<'_>

Bit 2 - Direction Change

pub fn vlc(&mut self) -> VLC_W<'_>

Bit 3 - Velocity

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - Channel 0 Compare Match

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - Channel 1 Compare Match

impl W<u16, Reg<u16, _STATUS>>

pub fn qerr(&mut self) -> QERR_W<'_>

Bit 0 - Quadrature Error Flag

pub fn idxerr(&mut self) -> IDXERR_W<'_>

Bit 1 - Index Error Flag

pub fn mperr(&mut self) -> MPERR_W<'_>

Bit 2 - Missing Pulse Error flag

pub fn winerr(&mut self) -> WINERR_W<'_>

Bit 4 - Window Error Flag

pub fn herr(&mut self) -> HERR_W<'_>

Bit 5 - Hall Error Flag

pub fn stop(&mut self) -> STOP_W<'_>

Bit 6 - Stop

pub fn dir(&mut self) -> DIR_W<'_>

Bit 7 - Direction Status Flag

pub fn prescbufv(&mut self) -> PRESCBUFV_W<'_>

Bit 8 - Prescaler Buffer Valid

pub fn filterbufv(&mut self) -> FILTERBUFV_W<'_>

Bit 9 - Filter Buffer Valid

pub fn ccbufv0(&mut self) -> CCBUFV0_W<'_>

Bit 12 - Compare Channel 0 Buffer Valid

pub fn ccbufv1(&mut self) -> CCBUFV1_W<'_>

Bit 13 - Compare Channel 1 Buffer Valid

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Run Mode

impl W<u8, Reg<u8, _PRESC>>

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 0:3 - Prescaler Value

impl W<u8, Reg<u8, _FILTER>>

pub fn filter(&mut self) -> FILTER_W<'_>

Bits 0:7 - Filter Value

impl W<u8, Reg<u8, _PRESCBUF>>

pub fn prescbuf(&mut self) -> PRESCBUF_W<'_>

Bits 0:3 - Prescaler Buffer Value

impl W<u8, Reg<u8, _FILTERBUF>>

pub fn filterbuf(&mut self) -> FILTERBUF_W<'_>

Bits 0:7 - Filter Buffer Value

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:15 - Channel Compare Value

impl W<u32, Reg<u32, _CCBUF>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:15 - Channel Compare Buffer Value

impl W<u8, Reg<u8, _CTRLA>>

pub fn ioret(&mut self) -> IORET_W<'_>

Bit 2 - I/O Retention

impl W<u8, Reg<u8, _SLEEPCFG>>

pub fn sleepmode(&mut self) -> SLEEPMODE_W<'_>

Bits 0:2 - Sleep Mode

impl W<u8, Reg<u8, _INTENCLR>>

pub fn sleeprdy(&mut self) -> SLEEPRDY_W<'_>

Bit 0 - Sleep Mode Entry Ready Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn sleeprdy(&mut self) -> SLEEPRDY_W<'_>

Bit 0 - Sleep Mode Entry Ready Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn sleeprdy(&mut self) -> SLEEPRDY_W<'_>

Bit 0 - Sleep Mode Entry Ready

impl W<u8, Reg<u8, _STDBYCFG>>

pub fn ramcfg(&mut self) -> RAMCFG_W<'_>

Bits 0:1 - Ram Configuration

pub fn fastwkup(&mut self) -> FASTWKUP_W<'_>

Bits 4:5 - Fast Wakeup

impl W<u8, Reg<u8, _HIBCFG>>

pub fn ramcfg(&mut self) -> RAMCFG_W<'_>

Bits 0:1 - Ram Configuration

pub fn bramcfg(&mut self) -> BRAMCFG_W<'_>

Bits 2:3 - Backup Ram Configuration

impl W<u8, Reg<u8, _BKUPCFG>>

pub fn bramcfg(&mut self) -> BRAMCFG_W<'_>

Bits 0:1 - Ram Configuration

impl W<u8, Reg<u8, _PWSAKDLY>>

pub fn dlyval(&mut self) -> DLYVAL_W<'_>

Bits 0:6 - Delay Value

pub fn ignack(&mut self) -> IGNACK_W<'_>

Bit 7 - Ignore Acknowledge

impl W<u32, Reg<u32, _DIR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _DIRCLR>>

pub fn dirclr(&mut self) -> DIRCLR_W<'_>

Bits 0:31 - Port Data Direction Clear

impl W<u32, Reg<u32, _DIRSET>>

pub fn dirset(&mut self) -> DIRSET_W<'_>

Bits 0:31 - Port Data Direction Set

impl W<u32, Reg<u32, _DIRTGL>>

pub fn dirtgl(&mut self) -> DIRTGL_W<'_>

Bits 0:31 - Port Data Direction Toggle

impl W<u32, Reg<u32, _OUT>>

pub fn out(&mut self) -> OUT_W<'_>

Bits 0:31 - PORT Data Output Value

impl W<u32, Reg<u32, _OUTCLR>>

pub fn outclr(&mut self) -> OUTCLR_W<'_>

Bits 0:31 - PORT Data Output Value Clear

impl W<u32, Reg<u32, _OUTSET>>

pub fn outset(&mut self) -> OUTSET_W<'_>

Bits 0:31 - PORT Data Output Value Set

impl W<u32, Reg<u32, _OUTTGL>>

pub fn outtgl(&mut self) -> OUTTGL_W<'_>

Bits 0:31 - PORT Data Output Value Toggle

impl W<u32, Reg<u32, _CTRL>>

pub fn sampling(&mut self) -> SAMPLING_W<'_>

Bits 0:31 - Input Sampling Mode

impl W<u32, Reg<u32, _WRCONFIG>>

pub fn pinmask(&mut self) -> PINMASK_W<'_>

Bits 0:15 - Pin Mask for Multiple Pin Configuration

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 16 - Peripheral Multiplexer Enable

pub fn inen(&mut self) -> INEN_W<'_>

Bit 17 - Input Enable

pub fn pullen(&mut self) -> PULLEN_W<'_>

Bit 18 - Pull Enable

pub fn drvstr(&mut self) -> DRVSTR_W<'_>

Bit 22 - Output Driver Strength Selection

pub fn pmux(&mut self) -> PMUX_W<'_>

Bits 24:27 - Peripheral Multiplexing

pub fn wrpmux(&mut self) -> WRPMUX_W<'_>

Bit 28 - Write PMUX

pub fn wrpincfg(&mut self) -> WRPINCFG_W<'_>

Bit 30 - Write PINCFG

pub fn hwsel(&mut self) -> HWSEL_W<'_>

Bit 31 - Half-Word Select

impl W<u32, Reg<u32, _EVCTRL>>

pub fn pid0(&mut self) -> PID0_W<'_>

Bits 0:4 - PORT Event Pin Identifier 0

pub fn evact0(&mut self) -> EVACT0_W<'_>

Bits 5:6 - PORT Event Action 0

pub fn portei0(&mut self) -> PORTEI0_W<'_>

Bit 7 - PORT Event Input Enable 0

pub fn pid1(&mut self) -> PID1_W<'_>

Bits 8:12 - PORT Event Pin Identifier 1

pub fn evact1(&mut self) -> EVACT1_W<'_>

Bits 13:14 - PORT Event Action 1

pub fn portei1(&mut self) -> PORTEI1_W<'_>

Bit 15 - PORT Event Input Enable 1

pub fn pid2(&mut self) -> PID2_W<'_>

Bits 16:20 - PORT Event Pin Identifier 2

pub fn evact2(&mut self) -> EVACT2_W<'_>

Bits 21:22 - PORT Event Action 2

pub fn portei2(&mut self) -> PORTEI2_W<'_>

Bit 23 - PORT Event Input Enable 2

pub fn pid3(&mut self) -> PID3_W<'_>

Bits 24:28 - PORT Event Pin Identifier 3

pub fn evact3(&mut self) -> EVACT3_W<'_>

Bits 29:30 - PORT Event Action 3

pub fn portei3(&mut self) -> PORTEI3_W<'_>

Bit 31 - PORT Event Input Enable 3

impl W<u8, Reg<u8, _PMUX>>

pub fn pmuxe(&mut self) -> PMUXE_W<'_>

Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin

pub fn pmuxo(&mut self) -> PMUXO_W<'_>

Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin

impl W<u8, Reg<u8, _PINCFG>>

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 0 - Peripheral Multiplexer Enable

pub fn inen(&mut self) -> INEN_W<'_>

Bit 1 - Input Enable

pub fn pullen(&mut self) -> PULLEN_W<'_>

Bit 2 - Pull Enable

pub fn drvstr(&mut self) -> DRVSTR_W<'_>

Bit 6 - Output Driver Strength Selection

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn lastxfer(&mut self) -> LASTXFER_W<'_>

Bit 24 - Last Transfer

impl W<u32, Reg<u32, _CTRLB>>

pub fn mode(&mut self) -> MODE_W<'_>

Bit 0 - Serial Memory Mode

pub fn loopen(&mut self) -> LOOPEN_W<'_>

Bit 1 - Local Loopback Enable

pub fn wdrbt(&mut self) -> WDRBT_W<'_>

Bit 2 - Wait Data Read Before Transfer

pub fn smemreg(&mut self) -> SMEMREG_W<'_>

Bit 3 - Serial Memory reg

pub fn csmode(&mut self) -> CSMODE_W<'_>

Bits 4:5 - Chip Select Mode

pub fn datalen(&mut self) -> DATALEN_W<'_>

Bits 8:11 - Data Length

pub fn dlybct(&mut self) -> DLYBCT_W<'_>

Bits 16:23 - Delay Between Consecutive Transfers

pub fn dlycs(&mut self) -> DLYCS_W<'_>

Bits 24:31 - Minimum Inactive CS Delay

impl W<u32, Reg<u32, _BAUD>>

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 0 - Clock Polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 1 - Clock Phase

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 8:15 - Serial Clock Baud Rate

pub fn dlybs(&mut self) -> DLYBS_W<'_>

Bits 16:23 - Delay Before SCK

impl W<u32, Reg<u32, _TXDATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Transmit Data

impl W<u32, Reg<u32, _INTENCLR>>

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 0 - Receive Data Register Full Interrupt Disable

pub fn dre(&mut self) -> DRE_W<'_>

Bit 1 - Transmit Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 2 - Transmission Complete Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 3 - Overrun Error Interrupt Disable

pub fn csrise(&mut self) -> CSRISE_W<'_>

Bit 8 - Chip Select Rise Interrupt Disable

pub fn instrend(&mut self) -> INSTREND_W<'_>

Bit 10 - Instruction End Interrupt Disable

impl W<u32, Reg<u32, _INTENSET>>

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 0 - Receive Data Register Full Interrupt Enable

pub fn dre(&mut self) -> DRE_W<'_>

Bit 1 - Transmit Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 2 - Transmission Complete Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 3 - Overrun Error Interrupt Enable

pub fn csrise(&mut self) -> CSRISE_W<'_>

Bit 8 - Chip Select Rise Interrupt Enable

pub fn instrend(&mut self) -> INSTREND_W<'_>

Bit 10 - Instruction End Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 0 - Receive Data Register Full

pub fn dre(&mut self) -> DRE_W<'_>

Bit 1 - Transmit Data Register Empty

pub fn txc(&mut self) -> TXC_W<'_>

Bit 2 - Transmission Complete

pub fn error(&mut self) -> ERROR_W<'_>

Bit 3 - Overrun Error

pub fn csrise(&mut self) -> CSRISE_W<'_>

Bit 8 - Chip Select Rise

pub fn instrend(&mut self) -> INSTREND_W<'_>

Bit 10 - Instruction End

impl W<u32, Reg<u32, _INSTRADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - Instruction Address

impl W<u32, Reg<u32, _INSTRCTRL>>

pub fn instr(&mut self) -> INSTR_W<'_>

Bits 0:7 - Instruction Code

pub fn optcode(&mut self) -> OPTCODE_W<'_>

Bits 16:23 - Option Code

impl W<u32, Reg<u32, _INSTRFRAME>>

pub fn width(&mut self) -> WIDTH_W<'_>

Bits 0:2 - Instruction Code, Address, Option Code and Data Width

pub fn instren(&mut self) -> INSTREN_W<'_>

Bit 4 - Instruction Enable

pub fn addren(&mut self) -> ADDREN_W<'_>

Bit 5 - Address Enable

pub fn optcodeen(&mut self) -> OPTCODEEN_W<'_>

Bit 6 - Option Enable

pub fn dataen(&mut self) -> DATAEN_W<'_>

Bit 7 - Data Enable

pub fn optcodelen(&mut self) -> OPTCODELEN_W<'_>

Bits 8:9 - Option Code Length

pub fn addrlen(&mut self) -> ADDRLEN_W<'_>

Bit 10 - Address Length

pub fn tfrtype(&mut self) -> TFRTYPE_W<'_>

Bits 12:13 - Data Transfer Type

pub fn crmode(&mut self) -> CRMODE_W<'_>

Bit 14 - Continuous Read Mode

pub fn ddren(&mut self) -> DDREN_W<'_>

Bit 15 - Double Data Rate Enable

pub fn dummylen(&mut self) -> DUMMYLEN_W<'_>

Bits 16:20 - Dummy Cycles Length

impl W<u32, Reg<u32, _SCRAMBCTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Scrambling/Unscrambling Enable

pub fn randomdis(&mut self) -> RANDOMDIS_W<'_>

Bit 1 - Scrambling/Unscrambling Random Value Disable

impl W<u32, Reg<u32, _SCRAMBKEY>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:31 - Scrambling User Key

impl W<u8, Reg<u8, _INTENCLR>>

pub fn singlee(&mut self) -> SINGLEE_W<'_>

Bit 0 - Single Bit ECC Error Interrupt Enable Clear

pub fn duale(&mut self) -> DUALE_W<'_>

Bit 1 - Dual Bit ECC Error Interrupt Enable Clear

impl W<u8, Reg<u8, _INTENSET>>

pub fn singlee(&mut self) -> SINGLEE_W<'_>

Bit 0 - Single Bit ECC Error Interrupt Enable Set

pub fn duale(&mut self) -> DUALE_W<'_>

Bit 1 - Dual Bit ECC Error Interrupt Enable Set

impl W<u8, Reg<u8, _INTFLAG>>

pub fn singlee(&mut self) -> SINGLEE_W<'_>

Bit 0 - Single Bit ECC Error Interrupt

pub fn duale(&mut self) -> DUALE_W<'_>

Bit 1 - Dual Bit ECC Error Interrupt

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn eccdis(&mut self) -> ECCDIS_W<'_>

Bit 0 - ECC Disable

pub fn eccelog(&mut self) -> ECCELOG_W<'_>

Bit 1 - ECC Error Log

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn matchclr(&mut self) -> MATCHCLR_W<'_>

Bit 7 - Clear on Match

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

pub fn bktrst(&mut self) -> BKTRST_W<'_>

Bit 13 - BKUP Registers Reset On Tamper Enable

pub fn gptrst(&mut self) -> GPTRST_W<'_>

Bit 14 - GP Registers Reset On Tamper Enable

pub fn countsync(&mut self) -> COUNTSYNC_W<'_>

Bit 15 - Count Read Synchronization Enable

impl W<u16, Reg<u16, _CTRLB>>

pub fn gp0en(&mut self) -> GP0EN_W<'_>

Bit 0 - General Purpose 0 Enable

pub fn gp2en(&mut self) -> GP2EN_W<'_>

Bit 1 - General Purpose 2 Enable

pub fn debmaj(&mut self) -> DEBMAJ_W<'_>

Bit 4 - Debouncer Majority Enable

pub fn debasync(&mut self) -> DEBASYNC_W<'_>

Bit 5 - Debouncer Asynchronous Enable

pub fn rtcout(&mut self) -> RTCOUT_W<'_>

Bit 6 - RTC Output Enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 7 - DMA Enable

pub fn debf(&mut self) -> DEBF_W<'_>

Bits 8:10 - Debounce Freqnuency

pub fn actf(&mut self) -> ACTF_W<'_>

Bits 12:14 - Active Layer Freqnuency

impl W<u32, Reg<u32, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn cmpeo0(&mut self) -> CMPEO0_W<'_>

Bit 8 - Compare 0 Event Output Enable

pub fn cmpeo1(&mut self) -> CMPEO1_W<'_>

Bit 9 - Compare 1 Event Output Enable

pub fn tampereo(&mut self) -> TAMPEREO_W<'_>

Bit 14 - Tamper Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

pub fn tampevei(&mut self) -> TAMPEVEI_W<'_>

Bit 16 - Tamper Event Input Enable

impl W<u16, Reg<u16, _INTENCLR>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Interrupt Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Interrupt Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Interrupt Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Interrupt Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Interrupt Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Interrupt Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Interrupt Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Interrupt Enable

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Interrupt Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Interrupt Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Interrupt Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Interrupt Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Interrupt Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Interrupt Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Interrupt Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Interrupt Enable

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:31 - Compare Value

impl W<u32, Reg<u32, _GP>>

pub fn gp(&mut self) -> GP_W<'_>

Bits 0:31 - General Purpose

impl W<u32, Reg<u32, _TAMPCTRL>>

pub fn in0act(&mut self) -> IN0ACT_W<'_>

Bits 0:1 - Tamper Input 0 Action

pub fn in1act(&mut self) -> IN1ACT_W<'_>

Bits 2:3 - Tamper Input 1 Action

pub fn in2act(&mut self) -> IN2ACT_W<'_>

Bits 4:5 - Tamper Input 2 Action

pub fn in3act(&mut self) -> IN3ACT_W<'_>

Bits 6:7 - Tamper Input 3 Action

pub fn in4act(&mut self) -> IN4ACT_W<'_>

Bits 8:9 - Tamper Input 4 Action

pub fn tamlvl0(&mut self) -> TAMLVL0_W<'_>

Bit 16 - Tamper Level Select 0

pub fn tamlvl1(&mut self) -> TAMLVL1_W<'_>

Bit 17 - Tamper Level Select 1

pub fn tamlvl2(&mut self) -> TAMLVL2_W<'_>

Bit 18 - Tamper Level Select 2

pub fn tamlvl3(&mut self) -> TAMLVL3_W<'_>

Bit 19 - Tamper Level Select 3

pub fn tamlvl4(&mut self) -> TAMLVL4_W<'_>

Bit 20 - Tamper Level Select 4

pub fn debnc0(&mut self) -> DEBNC0_W<'_>

Bit 24 - Debouncer Enable 0

pub fn debnc1(&mut self) -> DEBNC1_W<'_>

Bit 25 - Debouncer Enable 1

pub fn debnc2(&mut self) -> DEBNC2_W<'_>

Bit 26 - Debouncer Enable 2

pub fn debnc3(&mut self) -> DEBNC3_W<'_>

Bit 27 - Debouncer Enable 3

pub fn debnc4(&mut self) -> DEBNC4_W<'_>

Bit 28 - Debouncer Enable 4

impl W<u32, Reg<u32, _TAMPID>>

pub fn tampid0(&mut self) -> TAMPID0_W<'_>

Bit 0 - Tamper Input 0 Detected

pub fn tampid1(&mut self) -> TAMPID1_W<'_>

Bit 1 - Tamper Input 1 Detected

pub fn tampid2(&mut self) -> TAMPID2_W<'_>

Bit 2 - Tamper Input 2 Detected

pub fn tampid3(&mut self) -> TAMPID3_W<'_>

Bit 3 - Tamper Input 3 Detected

pub fn tampid4(&mut self) -> TAMPID4_W<'_>

Bit 4 - Tamper Input 4 Detected

pub fn tampevt(&mut self) -> TAMPEVT_W<'_>

Bit 31 - Tamper Event Detected

impl W<u32, Reg<u32, _BKUP>>

pub fn bkup(&mut self) -> BKUP_W<'_>

Bits 0:31 - Backup

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

pub fn bktrst(&mut self) -> BKTRST_W<'_>

Bit 13 - BKUP Registers Reset On Tamper Enable

pub fn gptrst(&mut self) -> GPTRST_W<'_>

Bit 14 - GP Registers Reset On Tamper Enable

pub fn countsync(&mut self) -> COUNTSYNC_W<'_>

Bit 15 - Count Read Synchronization Enable

impl W<u16, Reg<u16, _CTRLB>>

pub fn gp0en(&mut self) -> GP0EN_W<'_>

Bit 0 - General Purpose 0 Enable

pub fn gp2en(&mut self) -> GP2EN_W<'_>

Bit 1 - General Purpose 2 Enable

pub fn debmaj(&mut self) -> DEBMAJ_W<'_>

Bit 4 - Debouncer Majority Enable

pub fn debasync(&mut self) -> DEBASYNC_W<'_>

Bit 5 - Debouncer Asynchronous Enable

pub fn rtcout(&mut self) -> RTCOUT_W<'_>

Bit 6 - RTC Output Enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 7 - DMA Enable

pub fn debf(&mut self) -> DEBF_W<'_>

Bits 8:10 - Debounce Freqnuency

pub fn actf(&mut self) -> ACTF_W<'_>

Bits 12:14 - Active Layer Freqnuency

impl W<u32, Reg<u32, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn cmpeo0(&mut self) -> CMPEO0_W<'_>

Bit 8 - Compare 0 Event Output Enable

pub fn cmpeo1(&mut self) -> CMPEO1_W<'_>

Bit 9 - Compare 1 Event Output Enable

pub fn cmpeo2(&mut self) -> CMPEO2_W<'_>

Bit 10 - Compare 2 Event Output Enable

pub fn cmpeo3(&mut self) -> CMPEO3_W<'_>

Bit 11 - Compare 3 Event Output Enable

pub fn tampereo(&mut self) -> TAMPEREO_W<'_>

Bit 14 - Tamper Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

pub fn tampevei(&mut self) -> TAMPEVEI_W<'_>

Bit 16 - Tamper Event Input Enable

impl W<u16, Reg<u16, _INTENCLR>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Interrupt Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Interrupt Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Interrupt Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Interrupt Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Interrupt Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Interrupt Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Interrupt Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Interrupt Enable

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1 Interrupt Enable

pub fn cmp2(&mut self) -> CMP2_W<'_>

Bit 10 - Compare 2 Interrupt Enable

pub fn cmp3(&mut self) -> CMP3_W<'_>

Bit 11 - Compare 3 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Interrupt Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Interrupt Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Interrupt Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Interrupt Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Interrupt Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Interrupt Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Interrupt Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Interrupt Enable

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0 Interrupt Enable

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1 Interrupt Enable

pub fn cmp2(&mut self) -> CMP2_W<'_>

Bit 10 - Compare 2 Interrupt Enable

pub fn cmp3(&mut self) -> CMP3_W<'_>

Bit 11 - Compare 3 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 8 - Compare 0

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 9 - Compare 1

pub fn cmp2(&mut self) -> CMP2_W<'_>

Bit 10 - Compare 2

pub fn cmp3(&mut self) -> CMP3_W<'_>

Bit 11 - Compare 3

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u16, Reg<u16, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Counter Value

impl W<u16, Reg<u16, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:15 - Counter Period

impl W<u16, Reg<u16, _COMP>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 0:15 - Compare Value

impl W<u32, Reg<u32, _GP>>

pub fn gp(&mut self) -> GP_W<'_>

Bits 0:31 - General Purpose

impl W<u32, Reg<u32, _TAMPCTRL>>

pub fn in0act(&mut self) -> IN0ACT_W<'_>

Bits 0:1 - Tamper Input 0 Action

pub fn in1act(&mut self) -> IN1ACT_W<'_>

Bits 2:3 - Tamper Input 1 Action

pub fn in2act(&mut self) -> IN2ACT_W<'_>

Bits 4:5 - Tamper Input 2 Action

pub fn in3act(&mut self) -> IN3ACT_W<'_>

Bits 6:7 - Tamper Input 3 Action

pub fn in4act(&mut self) -> IN4ACT_W<'_>

Bits 8:9 - Tamper Input 4 Action

pub fn tamlvl0(&mut self) -> TAMLVL0_W<'_>

Bit 16 - Tamper Level Select 0

pub fn tamlvl1(&mut self) -> TAMLVL1_W<'_>

Bit 17 - Tamper Level Select 1

pub fn tamlvl2(&mut self) -> TAMLVL2_W<'_>

Bit 18 - Tamper Level Select 2

pub fn tamlvl3(&mut self) -> TAMLVL3_W<'_>

Bit 19 - Tamper Level Select 3

pub fn tamlvl4(&mut self) -> TAMLVL4_W<'_>

Bit 20 - Tamper Level Select 4

pub fn debnc0(&mut self) -> DEBNC0_W<'_>

Bit 24 - Debouncer Enable 0

pub fn debnc1(&mut self) -> DEBNC1_W<'_>

Bit 25 - Debouncer Enable 1

pub fn debnc2(&mut self) -> DEBNC2_W<'_>

Bit 26 - Debouncer Enable 2

pub fn debnc3(&mut self) -> DEBNC3_W<'_>

Bit 27 - Debouncer Enable 3

pub fn debnc4(&mut self) -> DEBNC4_W<'_>

Bit 28 - Debouncer Enable 4

impl W<u32, Reg<u32, _TAMPID>>

pub fn tampid0(&mut self) -> TAMPID0_W<'_>

Bit 0 - Tamper Input 0 Detected

pub fn tampid1(&mut self) -> TAMPID1_W<'_>

Bit 1 - Tamper Input 1 Detected

pub fn tampid2(&mut self) -> TAMPID2_W<'_>

Bit 2 - Tamper Input 2 Detected

pub fn tampid3(&mut self) -> TAMPID3_W<'_>

Bit 3 - Tamper Input 3 Detected

pub fn tampid4(&mut self) -> TAMPID4_W<'_>

Bit 4 - Tamper Input 4 Detected

pub fn tampevt(&mut self) -> TAMPEVT_W<'_>

Bit 31 - Tamper Event Detected

impl W<u32, Reg<u32, _BKUP>>

pub fn bkup(&mut self) -> BKUP_W<'_>

Bits 0:31 - Backup

impl W<u16, Reg<u16, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Operating Mode

pub fn clkrep(&mut self) -> CLKREP_W<'_>

Bit 6 - Clock Representation

pub fn matchclr(&mut self) -> MATCHCLR_W<'_>

Bit 7 - Clear on Match

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:11 - Prescaler

pub fn bktrst(&mut self) -> BKTRST_W<'_>

Bit 13 - BKUP Registers Reset On Tamper Enable

pub fn gptrst(&mut self) -> GPTRST_W<'_>

Bit 14 - GP Registers Reset On Tamper Enable

pub fn clocksync(&mut self) -> CLOCKSYNC_W<'_>

Bit 15 - Clock Read Synchronization Enable

impl W<u16, Reg<u16, _CTRLB>>

pub fn gp0en(&mut self) -> GP0EN_W<'_>

Bit 0 - General Purpose 0 Enable

pub fn gp2en(&mut self) -> GP2EN_W<'_>

Bit 1 - General Purpose 2 Enable

pub fn debmaj(&mut self) -> DEBMAJ_W<'_>

Bit 4 - Debouncer Majority Enable

pub fn debasync(&mut self) -> DEBASYNC_W<'_>

Bit 5 - Debouncer Asynchronous Enable

pub fn rtcout(&mut self) -> RTCOUT_W<'_>

Bit 6 - RTC Output Enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 7 - DMA Enable

pub fn debf(&mut self) -> DEBF_W<'_>

Bits 8:10 - Debounce Freqnuency

pub fn actf(&mut self) -> ACTF_W<'_>

Bits 12:14 - Active Layer Freqnuency

impl W<u32, Reg<u32, _EVCTRL>>

pub fn pereo0(&mut self) -> PEREO0_W<'_>

Bit 0 - Periodic Interval 0 Event Output Enable

pub fn pereo1(&mut self) -> PEREO1_W<'_>

Bit 1 - Periodic Interval 1 Event Output Enable

pub fn pereo2(&mut self) -> PEREO2_W<'_>

Bit 2 - Periodic Interval 2 Event Output Enable

pub fn pereo3(&mut self) -> PEREO3_W<'_>

Bit 3 - Periodic Interval 3 Event Output Enable

pub fn pereo4(&mut self) -> PEREO4_W<'_>

Bit 4 - Periodic Interval 4 Event Output Enable

pub fn pereo5(&mut self) -> PEREO5_W<'_>

Bit 5 - Periodic Interval 5 Event Output Enable

pub fn pereo6(&mut self) -> PEREO6_W<'_>

Bit 6 - Periodic Interval 6 Event Output Enable

pub fn pereo7(&mut self) -> PEREO7_W<'_>

Bit 7 - Periodic Interval 7 Event Output Enable

pub fn alarmeo0(&mut self) -> ALARMEO0_W<'_>

Bit 8 - Alarm 0 Event Output Enable

pub fn alarmeo1(&mut self) -> ALARMEO1_W<'_>

Bit 9 - Alarm 1 Event Output Enable

pub fn tampereo(&mut self) -> TAMPEREO_W<'_>

Bit 14 - Tamper Event Output Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 15 - Overflow Event Output Enable

pub fn tampevei(&mut self) -> TAMPEVEI_W<'_>

Bit 16 - Tamper Event Input Enable

impl W<u16, Reg<u16, _INTENCLR>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Interrupt Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Interrupt Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Interrupt Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Interrupt Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Interrupt Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Interrupt Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Interrupt Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Interrupt Enable

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 8 - Alarm 0 Interrupt Enable

pub fn alarm1(&mut self) -> ALARM1_W<'_>

Bit 9 - Alarm 1 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0 Enable

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1 Enable

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2 Enable

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3 Enable

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4 Enable

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5 Enable

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6 Enable

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7 Enable

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 8 - Alarm 0 Interrupt Enable

pub fn alarm1(&mut self) -> ALARM1_W<'_>

Bit 9 - Alarm 1 Interrupt Enable

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper Enable

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn per0(&mut self) -> PER0_W<'_>

Bit 0 - Periodic Interval 0

pub fn per1(&mut self) -> PER1_W<'_>

Bit 1 - Periodic Interval 1

pub fn per2(&mut self) -> PER2_W<'_>

Bit 2 - Periodic Interval 2

pub fn per3(&mut self) -> PER3_W<'_>

Bit 3 - Periodic Interval 3

pub fn per4(&mut self) -> PER4_W<'_>

Bit 4 - Periodic Interval 4

pub fn per5(&mut self) -> PER5_W<'_>

Bit 5 - Periodic Interval 5

pub fn per6(&mut self) -> PER6_W<'_>

Bit 6 - Periodic Interval 6

pub fn per7(&mut self) -> PER7_W<'_>

Bit 7 - Periodic Interval 7

pub fn alarm0(&mut self) -> ALARM0_W<'_>

Bit 8 - Alarm 0

pub fn alarm1(&mut self) -> ALARM1_W<'_>

Bit 9 - Alarm 1

pub fn tamper(&mut self) -> TAMPER_W<'_>

Bit 14 - Tamper

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 15 - Overflow

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _FREQCORR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:6 - Correction Value

pub fn sign(&mut self) -> SIGN_W<'_>

Bit 7 - Correction Sign

impl W<u32, Reg<u32, _CLOCK>>

pub fn second(&mut self) -> SECOND_W<'_>

Bits 0:5 - Second

pub fn minute(&mut self) -> MINUTE_W<'_>

Bits 6:11 - Minute

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 12:16 - Hour

pub fn day(&mut self) -> DAY_W<'_>

Bits 17:21 - Day

pub fn month(&mut self) -> MONTH_W<'_>

Bits 22:25 - Month

pub fn year(&mut self) -> YEAR_W<'_>

Bits 26:31 - Year

impl W<u32, Reg<u32, _GP>>

pub fn gp(&mut self) -> GP_W<'_>

Bits 0:31 - General Purpose

impl W<u32, Reg<u32, _ALARM0>>

pub fn second(&mut self) -> SECOND_W<'_>

Bits 0:5 - Second

pub fn minute(&mut self) -> MINUTE_W<'_>

Bits 6:11 - Minute

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 12:16 - Hour

pub fn day(&mut self) -> DAY_W<'_>

Bits 17:21 - Day

pub fn month(&mut self) -> MONTH_W<'_>

Bits 22:25 - Month

pub fn year(&mut self) -> YEAR_W<'_>

Bits 26:31 - Year

impl W<u8, Reg<u8, _MASK0>>

pub fn sel(&mut self) -> SEL_W<'_>

Bits 0:2 - Alarm Mask Selection

impl W<u32, Reg<u32, _ALARM1>>

pub fn second(&mut self) -> SECOND_W<'_>

Bits 0:5 - Second

pub fn minute(&mut self) -> MINUTE_W<'_>

Bits 6:11 - Minute

pub fn hour(&mut self) -> HOUR_W<'_>

Bits 12:16 - Hour

pub fn day(&mut self) -> DAY_W<'_>

Bits 17:21 - Day

pub fn month(&mut self) -> MONTH_W<'_>

Bits 22:25 - Month

pub fn year(&mut self) -> YEAR_W<'_>

Bits 26:31 - Year

impl W<u8, Reg<u8, _MASK1>>

pub fn sel(&mut self) -> SEL_W<'_>

Bits 0:2 - Alarm Mask Selection

impl W<u32, Reg<u32, _TAMPCTRL>>

pub fn in0act(&mut self) -> IN0ACT_W<'_>

Bits 0:1 - Tamper Input 0 Action

pub fn in1act(&mut self) -> IN1ACT_W<'_>

Bits 2:3 - Tamper Input 1 Action

pub fn in2act(&mut self) -> IN2ACT_W<'_>

Bits 4:5 - Tamper Input 2 Action

pub fn in3act(&mut self) -> IN3ACT_W<'_>

Bits 6:7 - Tamper Input 3 Action

pub fn in4act(&mut self) -> IN4ACT_W<'_>

Bits 8:9 - Tamper Input 4 Action

pub fn tamlvl0(&mut self) -> TAMLVL0_W<'_>

Bit 16 - Tamper Level Select 0

pub fn tamlvl1(&mut self) -> TAMLVL1_W<'_>

Bit 17 - Tamper Level Select 1

pub fn tamlvl2(&mut self) -> TAMLVL2_W<'_>

Bit 18 - Tamper Level Select 2

pub fn tamlvl3(&mut self) -> TAMLVL3_W<'_>

Bit 19 - Tamper Level Select 3

pub fn tamlvl4(&mut self) -> TAMLVL4_W<'_>

Bit 20 - Tamper Level Select 4

pub fn debnc0(&mut self) -> DEBNC0_W<'_>

Bit 24 - Debouncer Enable 0

pub fn debnc1(&mut self) -> DEBNC1_W<'_>

Bit 25 - Debouncer Enable 1

pub fn debnc2(&mut self) -> DEBNC2_W<'_>

Bit 26 - Debouncer Enable 2

pub fn debnc3(&mut self) -> DEBNC3_W<'_>

Bit 27 - Debouncer Enable 3

pub fn debnc4(&mut self) -> DEBNC4_W<'_>

Bit 28 - Debouncer Enable 4

impl W<u32, Reg<u32, _TAMPID>>

pub fn tampid0(&mut self) -> TAMPID0_W<'_>

Bit 0 - Tamper Input 0 Detected

pub fn tampid1(&mut self) -> TAMPID1_W<'_>

Bit 1 - Tamper Input 1 Detected

pub fn tampid2(&mut self) -> TAMPID2_W<'_>

Bit 2 - Tamper Input 2 Detected

pub fn tampid3(&mut self) -> TAMPID3_W<'_>

Bit 3 - Tamper Input 3 Detected

pub fn tampid4(&mut self) -> TAMPID4_W<'_>

Bit 4 - Tamper Input 4 Detected

pub fn tampevt(&mut self) -> TAMPEVT_W<'_>

Bit 31 - Tamper Event Detected

impl W<u32, Reg<u32, _BKUP>>

pub fn bkup(&mut self) -> BKUP_W<'_>

Bits 0:31 - Backup

impl W<u32, Reg<u32, _SSAR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:31 - SDMA System Address

impl W<u32, Reg<u32, _SSAR_CMD23_MODE>>

pub fn arg2(&mut self) -> ARG2_W<'_>

Bits 0:31 - Argument 2

impl W<u16, Reg<u16, _BSR>>

pub fn blocksize(&mut self) -> BLOCKSIZE_W<'_>

Bits 0:9 - Transfer Block Size

pub fn boundary(&mut self) -> BOUNDARY_W<'_>

Bits 12:14 - SDMA Buffer Boundary

impl W<u16, Reg<u16, _BCR>>

pub fn bcnt(&mut self) -> BCNT_W<'_>

Bits 0:15 - Blocks Count for Current Transfer

impl W<u32, Reg<u32, _ARG1R>>

pub fn arg(&mut self) -> ARG_W<'_>

Bits 0:31 - Argument 1

impl W<u16, Reg<u16, _TMR>>

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMA Enable

pub fn bcen(&mut self) -> BCEN_W<'_>

Bit 1 - Block Count Enable

pub fn acmden(&mut self) -> ACMDEN_W<'_>

Bits 2:3 - Auto Command Enable

pub fn dtdsel(&mut self) -> DTDSEL_W<'_>

Bit 4 - Data Transfer Direction Selection

pub fn msbsel(&mut self) -> MSBSEL_W<'_>

Bit 5 - Multi/Single Block Selection

impl W<u16, Reg<u16, _CR>>

pub fn resptyp(&mut self) -> RESPTYP_W<'_>

Bits 0:1 - Response Type

pub fn cmdccen(&mut self) -> CMDCCEN_W<'_>

Bit 3 - Command CRC Check Enable

pub fn cmdicen(&mut self) -> CMDICEN_W<'_>

Bit 4 - Command Index Check Enable

pub fn dpsel(&mut self) -> DPSEL_W<'_>

Bit 5 - Data Present Select

pub fn cmdtyp(&mut self) -> CMDTYP_W<'_>

Bits 6:7 - Command Type

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bits 8:13 - Command Index

impl W<u32, Reg<u32, _BDPR>>

pub fn bufdata(&mut self) -> BUFDATA_W<'_>

Bits 0:31 - Buffer Data

impl W<u8, Reg<u8, _HC1R>>

pub fn ledctrl(&mut self) -> LEDCTRL_W<'_>

Bit 0 - LED Control

pub fn dw(&mut self) -> DW_W<'_>

Bit 1 - Data Width

pub fn hsen(&mut self) -> HSEN_W<'_>

Bit 2 - High Speed Enable

pub fn dmasel(&mut self) -> DMASEL_W<'_>

Bits 3:4 - DMA Select

pub fn carddtl(&mut self) -> CARDDTL_W<'_>

Bit 6 - Card Detect Test Level

pub fn carddsel(&mut self) -> CARDDSEL_W<'_>

Bit 7 - Card Detect Signal Selection

impl W<u8, Reg<u8, _HC1R_EMMC_MODE>>

pub fn dw(&mut self) -> DW_W<'_>

Bit 1 - Data Width

pub fn hsen(&mut self) -> HSEN_W<'_>

Bit 2 - High Speed Enable

pub fn dmasel(&mut self) -> DMASEL_W<'_>

Bits 3:4 - DMA Select

impl W<u8, Reg<u8, _PCR>>

pub fn sdbpwr(&mut self) -> SDBPWR_W<'_>

Bit 0 - SD Bus Power

pub fn sdbvsel(&mut self) -> SDBVSEL_W<'_>

Bits 1:3 - SD Bus Voltage Select

impl W<u8, Reg<u8, _BGCR>>

pub fn stpbgr(&mut self) -> STPBGR_W<'_>

Bit 0 - Stop at Block Gap Request

pub fn contr(&mut self) -> CONTR_W<'_>

Bit 1 - Continue Request

pub fn rwctrl(&mut self) -> RWCTRL_W<'_>

Bit 2 - Read Wait Control

pub fn intbg(&mut self) -> INTBG_W<'_>

Bit 3 - Interrupt at Block Gap

impl W<u8, Reg<u8, _BGCR_EMMC_MODE>>

pub fn stpbgr(&mut self) -> STPBGR_W<'_>

Bit 0 - Stop at Block Gap Request

pub fn contr(&mut self) -> CONTR_W<'_>

Bit 1 - Continue Request

impl W<u8, Reg<u8, _WCR>>

pub fn wkencint(&mut self) -> WKENCINT_W<'_>

Bit 0 - Wakeup Event Enable on Card Interrupt

pub fn wkencins(&mut self) -> WKENCINS_W<'_>

Bit 1 - Wakeup Event Enable on Card Insertion

pub fn wkencrem(&mut self) -> WKENCREM_W<'_>

Bit 2 - Wakeup Event Enable on Card Removal

impl W<u16, Reg<u16, _CCR>>

pub fn intclken(&mut self) -> INTCLKEN_W<'_>

Bit 0 - Internal Clock Enable

pub fn intclks(&mut self) -> INTCLKS_W<'_>

Bit 1 - Internal Clock Stable

pub fn sdclken(&mut self) -> SDCLKEN_W<'_>

Bit 2 - SD Clock Enable

pub fn clkgsel(&mut self) -> CLKGSEL_W<'_>

Bit 5 - Clock Generator Select

pub fn usdclkfsel(&mut self) -> USDCLKFSEL_W<'_>

Bits 6:7 - Upper Bits of SDCLK Frequency Select

pub fn sdclkfsel(&mut self) -> SDCLKFSEL_W<'_>

Bits 8:15 - SDCLK Frequency Select

impl W<u8, Reg<u8, _TCR>>

pub fn dtcval(&mut self) -> DTCVAL_W<'_>

Bits 0:3 - Data Timeout Counter Value

impl W<u8, Reg<u8, _SRR>>

pub fn swrstall(&mut self) -> SWRSTALL_W<'_>

Bit 0 - Software Reset For All

pub fn swrstcmd(&mut self) -> SWRSTCMD_W<'_>

Bit 1 - Software Reset For CMD Line

pub fn swrstdat(&mut self) -> SWRSTDAT_W<'_>

Bit 2 - Software Reset For DAT Line

impl W<u16, Reg<u16, _NISTR>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready

pub fn cins(&mut self) -> CINS_W<'_>

Bit 6 - Card Insertion

pub fn crem(&mut self) -> CREM_W<'_>

Bit 7 - Card Removal

pub fn cint(&mut self) -> CINT_W<'_>

Bit 8 - Card Interrupt

pub fn errint(&mut self) -> ERRINT_W<'_>

Bit 15 - Error Interrupt

impl W<u16, Reg<u16, _NISTR_EMMC_MODE>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready

pub fn bootar(&mut self) -> BOOTAR_W<'_>

Bit 14 - Boot Acknowledge Received

pub fn errint(&mut self) -> ERRINT_W<'_>

Bit 15 - Error Interrupt

impl W<u16, Reg<u16, _EISTR>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error

impl W<u16, Reg<u16, _EISTR_EMMC_MODE>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error

pub fn bootae(&mut self) -> BOOTAE_W<'_>

Bit 12 - Boot Acknowledge Error

impl W<u16, Reg<u16, _NISTER>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete Status Enable

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete Status Enable

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event Status Enable

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt Status Enable

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready Status Enable

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready Status Enable

pub fn cins(&mut self) -> CINS_W<'_>

Bit 6 - Card Insertion Status Enable

pub fn crem(&mut self) -> CREM_W<'_>

Bit 7 - Card Removal Status Enable

pub fn cint(&mut self) -> CINT_W<'_>

Bit 8 - Card Interrupt Status Enable

impl W<u16, Reg<u16, _NISTER_EMMC_MODE>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete Status Enable

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete Status Enable

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event Status Enable

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt Status Enable

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready Status Enable

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready Status Enable

pub fn bootar(&mut self) -> BOOTAR_W<'_>

Bit 14 - Boot Acknowledge Received Status Enable

impl W<u16, Reg<u16, _EISTER>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error Status Enable

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error Status Enable

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error Status Enable

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error Status Enable

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error Status Enable

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error Status Enable

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error Status Enable

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error Status Enable

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error Status Enable

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error Status Enable

impl W<u16, Reg<u16, _EISTER_EMMC_MODE>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error Status Enable

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error Status Enable

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error Status Enable

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error Status Enable

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error Status Enable

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error Status Enable

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error Status Enable

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error Status Enable

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error Status Enable

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error Status Enable

pub fn bootae(&mut self) -> BOOTAE_W<'_>

Bit 12 - Boot Acknowledge Error Status Enable

impl W<u16, Reg<u16, _NISIER>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete Signal Enable

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete Signal Enable

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event Signal Enable

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt Signal Enable

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready Signal Enable

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready Signal Enable

pub fn cins(&mut self) -> CINS_W<'_>

Bit 6 - Card Insertion Signal Enable

pub fn crem(&mut self) -> CREM_W<'_>

Bit 7 - Card Removal Signal Enable

pub fn cint(&mut self) -> CINT_W<'_>

Bit 8 - Card Interrupt Signal Enable

impl W<u16, Reg<u16, _NISIER_EMMC_MODE>>

pub fn cmdc(&mut self) -> CMDC_W<'_>

Bit 0 - Command Complete Signal Enable

pub fn trfc(&mut self) -> TRFC_W<'_>

Bit 1 - Transfer Complete Signal Enable

pub fn blkge(&mut self) -> BLKGE_W<'_>

Bit 2 - Block Gap Event Signal Enable

pub fn dmaint(&mut self) -> DMAINT_W<'_>

Bit 3 - DMA Interrupt Signal Enable

pub fn bwrrdy(&mut self) -> BWRRDY_W<'_>

Bit 4 - Buffer Write Ready Signal Enable

pub fn brdrdy(&mut self) -> BRDRDY_W<'_>

Bit 5 - Buffer Read Ready Signal Enable

pub fn bootar(&mut self) -> BOOTAR_W<'_>

Bit 14 - Boot Acknowledge Received Signal Enable

impl W<u16, Reg<u16, _EISIER>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error Signal Enable

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error Signal Enable

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error Signal Enable

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error Signal Enable

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error Signal Enable

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error Signal Enable

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error Signal Enable

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error Signal Enable

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error Signal Enable

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error Signal Enable

impl W<u16, Reg<u16, _EISIER_EMMC_MODE>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Command Timeout Error Signal Enable

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Command CRC Error Signal Enable

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Command End Bit Error Signal Enable

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Command Index Error Signal Enable

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Data Timeout Error Signal Enable

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Data CRC Error Signal Enable

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Data End Bit Error Signal Enable

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Current Limit Error Signal Enable

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Auto CMD Error Signal Enable

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - ADMA Error Signal Enable

pub fn bootae(&mut self) -> BOOTAE_W<'_>

Bit 12 - Boot Acknowledge Error Signal Enable

impl W<u16, Reg<u16, _HC2R>>

pub fn uhsms(&mut self) -> UHSMS_W<'_>

Bits 0:2 - UHS Mode Select

pub fn vs18en(&mut self) -> VS18EN_W<'_>

Bit 3 - 1.8V Signaling Enable

pub fn drvsel(&mut self) -> DRVSEL_W<'_>

Bits 4:5 - Driver Strength Select

pub fn extun(&mut self) -> EXTUN_W<'_>

Bit 6 - Execute Tuning

pub fn slcksel(&mut self) -> SLCKSEL_W<'_>

Bit 7 - Sampling Clock Select

pub fn asinten(&mut self) -> ASINTEN_W<'_>

Bit 14 - Asynchronous Interrupt Enable

pub fn pvalen(&mut self) -> PVALEN_W<'_>

Bit 15 - Preset Value Enable

impl W<u16, Reg<u16, _HC2R_EMMC_MODE>>

pub fn hs200en(&mut self) -> HS200EN_W<'_>

Bits 0:3 - HS200 Mode Enable

pub fn drvsel(&mut self) -> DRVSEL_W<'_>

Bits 4:5 - Driver Strength Select

pub fn extun(&mut self) -> EXTUN_W<'_>

Bit 6 - Execute Tuning

pub fn slcksel(&mut self) -> SLCKSEL_W<'_>

Bit 7 - Sampling Clock Select

pub fn pvalen(&mut self) -> PVALEN_W<'_>

Bit 15 - Preset Value Enable

impl W<u16, Reg<u16, _FERACES>>

pub fn acmd12ne(&mut self) -> ACMD12NE_W<'_>

Bit 0 - Force Event for Auto CMD12 Not Executed

pub fn acmdteo(&mut self) -> ACMDTEO_W<'_>

Bit 1 - Force Event for Auto CMD Timeout Error

pub fn acmdcrc(&mut self) -> ACMDCRC_W<'_>

Bit 2 - Force Event for Auto CMD CRC Error

pub fn acmdend(&mut self) -> ACMDEND_W<'_>

Bit 3 - Force Event for Auto CMD End Bit Error

pub fn acmdidx(&mut self) -> ACMDIDX_W<'_>

Bit 4 - Force Event for Auto CMD Index Error

pub fn cmdni(&mut self) -> CMDNI_W<'_>

Bit 7 - Force Event for Command Not Issued By Auto CMD12 Error

impl W<u16, Reg<u16, _FEREIS>>

pub fn cmdteo(&mut self) -> CMDTEO_W<'_>

Bit 0 - Force Event for Command Timeout Error

pub fn cmdcrc(&mut self) -> CMDCRC_W<'_>

Bit 1 - Force Event for Command CRC Error

pub fn cmdend(&mut self) -> CMDEND_W<'_>

Bit 2 - Force Event for Command End Bit Error

pub fn cmdidx(&mut self) -> CMDIDX_W<'_>

Bit 3 - Force Event for Command Index Error

pub fn datteo(&mut self) -> DATTEO_W<'_>

Bit 4 - Force Event for Data Timeout Error

pub fn datcrc(&mut self) -> DATCRC_W<'_>

Bit 5 - Force Event for Data CRC Error

pub fn datend(&mut self) -> DATEND_W<'_>

Bit 6 - Force Event for Data End Bit Error

pub fn curlim(&mut self) -> CURLIM_W<'_>

Bit 7 - Force Event for Current Limit Error

pub fn acmd(&mut self) -> ACMD_W<'_>

Bit 8 - Force Event for Auto CMD Error

pub fn adma(&mut self) -> ADMA_W<'_>

Bit 9 - Force Event for ADMA Error

pub fn bootae(&mut self) -> BOOTAE_W<'_>

Bit 12 - Force Event for Boot Acknowledge Error

impl W<u32, Reg<u32, _ASAR>>

pub fn admasa(&mut self) -> ADMASA_W<'_>

Bits 0:31 - ADMA System Address

impl W<u16, Reg<u16, _PVR>>

pub fn sdclkfsel(&mut self) -> SDCLKFSEL_W<'_>

Bits 0:9 - SDCLK Frequency Select Value for Initialization

pub fn clkgsel(&mut self) -> CLKGSEL_W<'_>

Bit 10 - Clock Generator Select Value for Initialization

pub fn drvsel(&mut self) -> DRVSEL_W<'_>

Bits 14:15 - Driver Strength Select Value for Initialization

impl W<u8, Reg<u8, _MC1R>>

pub fn cmdtyp(&mut self) -> CMDTYP_W<'_>

Bits 0:1 - e.MMC Command Type

pub fn ddr(&mut self) -> DDR_W<'_>

Bit 3 - e.MMC HSDDR Mode

pub fn opd(&mut self) -> OPD_W<'_>

Bit 4 - e.MMC Open Drain Mode

pub fn boota(&mut self) -> BOOTA_W<'_>

Bit 5 - e.MMC Boot Acknowledge Enable

pub fn rstn(&mut self) -> RSTN_W<'_>

Bit 6 - e.MMC Reset Signal

pub fn fcd(&mut self) -> FCD_W<'_>

Bit 7 - e.MMC Force Card Detect

impl W<u8, Reg<u8, _MC2R>>

pub fn sresp(&mut self) -> SRESP_W<'_>

Bit 0 - e.MMC Abort Wait IRQ

pub fn aboot(&mut self) -> ABOOT_W<'_>

Bit 1 - e.MMC Abort Boot

impl W<u32, Reg<u32, _ACR>>

pub fn bmax(&mut self) -> BMAX_W<'_>

Bits 0:1 - AHB Maximum Burst

impl W<u32, Reg<u32, _CC2R>>

pub fn fsdclkd(&mut self) -> FSDCLKD_W<'_>

Bit 0 - Force SDCK Disabled

impl W<u32, Reg<u32, _CACR>>

pub fn capwren(&mut self) -> CAPWREN_W<'_>

Bit 0 - Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)

pub fn key(&mut self) -> KEY_W<'_>

Bits 8:15 - Key (0x46)

impl W<u8, Reg<u8, _DBGR>>

pub fn nidbg(&mut self) -> NIDBG_W<'_>

Bit 0 - Non-intrusive debug enable

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run in Standby

pub fn pinout(&mut self) -> PINOUT_W<'_>

Bit 16 - Pin Usage

pub fn sdahold(&mut self) -> SDAHOLD_W<'_>

Bits 20:21 - SDA Hold Time

pub fn mexttoen(&mut self) -> MEXTTOEN_W<'_>

Bit 22 - Master SCL Low Extend Timeout

pub fn sexttoen(&mut self) -> SEXTTOEN_W<'_>

Bit 23 - Slave SCL Low Extend Timeout

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 24:25 - Transfer Speed

pub fn sclsm(&mut self) -> SCLSM_W<'_>

Bit 27 - SCL Clock Stretch Mode

pub fn inactout(&mut self) -> INACTOUT_W<'_>

Bits 28:29 - Inactive Time-Out

pub fn lowtouten(&mut self) -> LOWTOUTEN_W<'_>

Bit 30 - SCL Low Timeout Enable

impl W<u32, Reg<u32, _CTRLB>>

pub fn smen(&mut self) -> SMEN_W<'_>

Bit 8 - Smart Mode Enable

pub fn qcen(&mut self) -> QCEN_W<'_>

Bit 9 - Quick Command Enable

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 16:17 - Command

pub fn ackact(&mut self) -> ACKACT_W<'_>

Bit 18 - Acknowledge Action

impl W<u32, Reg<u32, _CTRLC>>

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bit 24 - Data 32 Bit

impl W<u32, Reg<u32, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:7 - Baud Rate Value

pub fn baudlow(&mut self) -> BAUDLOW_W<'_>

Bits 8:15 - Baud Rate Value Low

pub fn hsbaud(&mut self) -> HSBAUD_W<'_>

Bits 16:23 - High Speed Baud Rate Value

pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W<'_>

Bits 24:31 - High Speed Baud Rate Value Low

impl W<u8, Reg<u8, _INTENCLR>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt Disable

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt Enable

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn mb(&mut self) -> MB_W<'_>

Bit 0 - Master On Bus Interrupt

pub fn sb(&mut self) -> SB_W<'_>

Bit 1 - Slave On Bus Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 0 - Bus Error

pub fn arblost(&mut self) -> ARBLOST_W<'_>

Bit 1 - Arbitration Lost

pub fn rxnack(&mut self) -> RXNACK_W<'_>

Bit 2 - Received Not Acknowledge

pub fn busstate(&mut self) -> BUSSTATE_W<'_>

Bits 4:5 - Bus State

pub fn lowtout(&mut self) -> LOWTOUT_W<'_>

Bit 6 - SCL Low Timeout

pub fn clkhold(&mut self) -> CLKHOLD_W<'_>

Bit 7 - Clock Hold

pub fn mexttout(&mut self) -> MEXTTOUT_W<'_>

Bit 8 - Master SCL Low Extend Timeout

pub fn sexttout(&mut self) -> SEXTTOUT_W<'_>

Bit 9 - Slave SCL Low Extend Timeout

pub fn lenerr(&mut self) -> LENERR_W<'_>

Bit 10 - Length Error

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:10 - Address Value

pub fn lenen(&mut self) -> LENEN_W<'_>

Bit 13 - Length Enable

pub fn hs(&mut self) -> HS_W<'_>

Bit 14 - High Speed Mode

pub fn tenbiten(&mut self) -> TENBITEN_W<'_>

Bit 15 - Ten Bit Addressing Enable

pub fn len(&mut self) -> LEN_W<'_>

Bits 16:23 - Length

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn pinout(&mut self) -> PINOUT_W<'_>

Bit 16 - Pin Usage

pub fn sdahold(&mut self) -> SDAHOLD_W<'_>

Bits 20:21 - SDA Hold Time

pub fn sexttoen(&mut self) -> SEXTTOEN_W<'_>

Bit 23 - Slave SCL Low Extend Timeout

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 24:25 - Transfer Speed

pub fn sclsm(&mut self) -> SCLSM_W<'_>

Bit 27 - SCL Clock Stretch Mode

pub fn lowtouten(&mut self) -> LOWTOUTEN_W<'_>

Bit 30 - SCL Low Timeout Enable

impl W<u32, Reg<u32, _CTRLB>>

pub fn smen(&mut self) -> SMEN_W<'_>

Bit 8 - Smart Mode Enable

pub fn gcmd(&mut self) -> GCMD_W<'_>

Bit 9 - PMBus Group Command

pub fn aacken(&mut self) -> AACKEN_W<'_>

Bit 10 - Automatic Address Acknowledge

pub fn amode(&mut self) -> AMODE_W<'_>

Bits 14:15 - Address Mode

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 16:17 - Command

pub fn ackact(&mut self) -> ACKACT_W<'_>

Bit 18 - Acknowledge Action

impl W<u32, Reg<u32, _CTRLC>>

pub fn sdasetup(&mut self) -> SDASETUP_W<'_>

Bits 0:3 - SDA Setup Time

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bit 24 - Data 32 Bit

impl W<u8, Reg<u8, _INTENCLR>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt Disable

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt Disable

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt Enable

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt Enable

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn prec(&mut self) -> PREC_W<'_>

Bit 0 - Stop Received Interrupt

pub fn amatch(&mut self) -> AMATCH_W<'_>

Bit 1 - Address Match Interrupt

pub fn drdy(&mut self) -> DRDY_W<'_>

Bit 2 - Data Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn buserr(&mut self) -> BUSERR_W<'_>

Bit 0 - Bus Error

pub fn coll(&mut self) -> COLL_W<'_>

Bit 1 - Transmit Collision

pub fn rxnack(&mut self) -> RXNACK_W<'_>

Bit 2 - Received Not Acknowledge

pub fn dir(&mut self) -> DIR_W<'_>

Bit 3 - Read/Write Direction

pub fn sr(&mut self) -> SR_W<'_>

Bit 4 - Repeated Start

pub fn lowtout(&mut self) -> LOWTOUT_W<'_>

Bit 6 - SCL Low Timeout

pub fn clkhold(&mut self) -> CLKHOLD_W<'_>

Bit 7 - Clock Hold

pub fn sexttout(&mut self) -> SEXTTOUT_W<'_>

Bit 9 - Slave SCL Low Extend Timeout

pub fn hs(&mut self) -> HS_W<'_>

Bit 10 - High Speed

pub fn lenerr(&mut self) -> LENERR_W<'_>

Bit 11 - Transaction Length Error

impl W<u16, Reg<u16, _LENGTH>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:7 - Data Length

pub fn lenen(&mut self) -> LENEN_W<'_>

Bit 8 - Data Length Enable

impl W<u32, Reg<u32, _ADDR>>

pub fn gencen(&mut self) -> GENCEN_W<'_>

Bit 0 - General Call Address Enable

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 1:10 - Address Value

pub fn tenbiten(&mut self) -> TENBITEN_W<'_>

Bit 15 - Ten Bit Addressing Enable

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 17:26 - Address Mask

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn dopo(&mut self) -> DOPO_W<'_>

Bits 16:17 - Data Out Pinout

pub fn dipo(&mut self) -> DIPO_W<'_>

Bits 20:21 - Data In Pinout

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 28 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn ploaden(&mut self) -> PLOADEN_W<'_>

Bit 6 - Data Preload Enable

pub fn ssde(&mut self) -> SSDE_W<'_>

Bit 9 - Slave Select Low Detect Enable

pub fn mssen(&mut self) -> MSSEN_W<'_>

Bit 13 - Master Slave Select Enable

pub fn amode(&mut self) -> AMODE_W<'_>

Bits 14:15 - Address Mode

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

impl W<u32, Reg<u32, _CTRLC>>

pub fn icspace(&mut self) -> ICSPACE_W<'_>

Bits 0:5 - Inter-Character Spacing

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bit 24 - Data 32 Bit

impl W<u8, Reg<u8, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:7 - Baud Rate Value

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

pub fn lenerr(&mut self) -> LENERR_W<'_>

Bit 11 - Transaction Length Error

impl W<u16, Reg<u16, _LENGTH>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:7 - Data Length

pub fn lenen(&mut self) -> LENEN_W<'_>

Bit 8 - Data Length Enable

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:7 - Address Value

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 16:23 - Address Mask

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn dopo(&mut self) -> DOPO_W<'_>

Bits 16:17 - Data Out Pinout

pub fn dipo(&mut self) -> DIPO_W<'_>

Bits 20:21 - Data In Pinout

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 28 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn ploaden(&mut self) -> PLOADEN_W<'_>

Bit 6 - Data Preload Enable

pub fn ssde(&mut self) -> SSDE_W<'_>

Bit 9 - Slave Select Low Detect Enable

pub fn mssen(&mut self) -> MSSEN_W<'_>

Bit 13 - Master Slave Select Enable

pub fn amode(&mut self) -> AMODE_W<'_>

Bits 14:15 - Address Mode

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

impl W<u32, Reg<u32, _CTRLC>>

pub fn icspace(&mut self) -> ICSPACE_W<'_>

Bits 0:5 - Inter-Character Spacing

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bit 24 - Data 32 Bit

impl W<u8, Reg<u8, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:7 - Baud Rate Value

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt

pub fn ssl(&mut self) -> SSL_W<'_>

Bit 3 - Slave Select Low Interrupt Flag

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

pub fn lenerr(&mut self) -> LENERR_W<'_>

Bit 11 - Transaction Length Error

impl W<u16, Reg<u16, _LENGTH>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:7 - Data Length

pub fn lenen(&mut self) -> LENEN_W<'_>

Bit 8 - Data Length Enable

impl W<u32, Reg<u32, _ADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:7 - Address Value

pub fn addrmask(&mut self) -> ADDRMASK_W<'_>

Bits 16:23 - Address Mask

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 9 - Transmit Data Invert

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 10 - Receive Data Invert

pub fn sampr(&mut self) -> SAMPR_W<'_>

Bits 13:15 - Sample

pub fn txpo(&mut self) -> TXPO_W<'_>

Bits 16:17 - Transmit Data Pinout

pub fn rxpo(&mut self) -> RXPO_W<'_>

Bits 20:21 - Receive Data Pinout

pub fn sampa(&mut self) -> SAMPA_W<'_>

Bits 22:23 - Sample Adjustment

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cmode(&mut self) -> CMODE_W<'_>

Bit 28 - Communication Mode

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn sbmode(&mut self) -> SBMODE_W<'_>

Bit 6 - Stop Bit Mode

pub fn colden(&mut self) -> COLDEN_W<'_>

Bit 8 - Collision Detection Enable

pub fn sfde(&mut self) -> SFDE_W<'_>

Bit 9 - Start of Frame Detection Enable

pub fn enc(&mut self) -> ENC_W<'_>

Bit 10 - Encoding Format

pub fn pmode(&mut self) -> PMODE_W<'_>

Bit 13 - Parity Mode

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 16 - Transmitter Enable

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

pub fn lincmd(&mut self) -> LINCMD_W<'_>

Bits 24:25 - LIN Command

impl W<u32, Reg<u32, _CTRLC>>

pub fn gtime(&mut self) -> GTIME_W<'_>

Bits 0:2 - Guard Time

pub fn brklen(&mut self) -> BRKLEN_W<'_>

Bits 8:9 - LIN Master Break Length

pub fn hdrdly(&mut self) -> HDRDLY_W<'_>

Bits 10:11 - LIN Master Header Delay

pub fn inack(&mut self) -> INACK_W<'_>

Bit 16 - Inhibit Not Acknowledge

pub fn dsnack(&mut self) -> DSNACK_W<'_>

Bit 17 - Disable Successive NACK

pub fn maxiter(&mut self) -> MAXITER_W<'_>

Bits 20:22 - Maximum Iterations

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bits 24:25 - Data 32 Bit

impl W<u16, Reg<u16, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u16, Reg<u16, _BAUD_FRAC_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_FRACFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_USARTFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u8, Reg<u8, _RXPL>>

pub fn rxpl(&mut self) -> RXPL_W<'_>

Bits 0:7 - Receive Pulse Length

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Disable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Disable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Enable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Enable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn perr(&mut self) -> PERR_W<'_>

Bit 0 - Parity Error

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 1 - Frame Error

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

pub fn cts(&mut self) -> CTS_W<'_>

Bit 3 - Clear To Send

pub fn isf(&mut self) -> ISF_W<'_>

Bit 4 - Inconsistent Sync Field

pub fn coll(&mut self) -> COLL_W<'_>

Bit 5 - Collision Detected

pub fn txe(&mut self) -> TXE_W<'_>

Bit 6 - Transmitter Empty

pub fn iter(&mut self) -> ITER_W<'_>

Bit 7 - Maximum Number of Repetitions Reached

impl W<u16, Reg<u16, _LENGTH>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:7 - Data Length

pub fn lenen(&mut self) -> LENEN_W<'_>

Bits 8:9 - Data Length Enable

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:4 - Operating Mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 7 - Run during Standby

pub fn ibon(&mut self) -> IBON_W<'_>

Bit 8 - Immediate Buffer Overflow Notification

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 9 - Transmit Data Invert

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 10 - Receive Data Invert

pub fn sampr(&mut self) -> SAMPR_W<'_>

Bits 13:15 - Sample

pub fn txpo(&mut self) -> TXPO_W<'_>

Bits 16:17 - Transmit Data Pinout

pub fn rxpo(&mut self) -> RXPO_W<'_>

Bits 20:21 - Receive Data Pinout

pub fn sampa(&mut self) -> SAMPA_W<'_>

Bits 22:23 - Sample Adjustment

pub fn form(&mut self) -> FORM_W<'_>

Bits 24:27 - Frame Format

pub fn cmode(&mut self) -> CMODE_W<'_>

Bit 28 - Communication Mode

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 29 - Clock Polarity

pub fn dord(&mut self) -> DORD_W<'_>

Bit 30 - Data Order

impl W<u32, Reg<u32, _CTRLB>>

pub fn chsize(&mut self) -> CHSIZE_W<'_>

Bits 0:2 - Character Size

pub fn sbmode(&mut self) -> SBMODE_W<'_>

Bit 6 - Stop Bit Mode

pub fn colden(&mut self) -> COLDEN_W<'_>

Bit 8 - Collision Detection Enable

pub fn sfde(&mut self) -> SFDE_W<'_>

Bit 9 - Start of Frame Detection Enable

pub fn enc(&mut self) -> ENC_W<'_>

Bit 10 - Encoding Format

pub fn pmode(&mut self) -> PMODE_W<'_>

Bit 13 - Parity Mode

pub fn txen(&mut self) -> TXEN_W<'_>

Bit 16 - Transmitter Enable

pub fn rxen(&mut self) -> RXEN_W<'_>

Bit 17 - Receiver Enable

pub fn lincmd(&mut self) -> LINCMD_W<'_>

Bits 24:25 - LIN Command

impl W<u32, Reg<u32, _CTRLC>>

pub fn gtime(&mut self) -> GTIME_W<'_>

Bits 0:2 - Guard Time

pub fn brklen(&mut self) -> BRKLEN_W<'_>

Bits 8:9 - LIN Master Break Length

pub fn hdrdly(&mut self) -> HDRDLY_W<'_>

Bits 10:11 - LIN Master Header Delay

pub fn inack(&mut self) -> INACK_W<'_>

Bit 16 - Inhibit Not Acknowledge

pub fn dsnack(&mut self) -> DSNACK_W<'_>

Bit 17 - Disable Successive NACK

pub fn maxiter(&mut self) -> MAXITER_W<'_>

Bits 20:22 - Maximum Iterations

pub fn data32b(&mut self) -> DATA32B_W<'_>

Bits 24:25 - Data 32 Bit

impl W<u16, Reg<u16, _BAUD>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u16, Reg<u16, _BAUD_FRAC_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_FRACFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:12 - Baud Rate Value

pub fn fp(&mut self) -> FP_W<'_>

Bits 13:15 - Fractional Part

impl W<u16, Reg<u16, _BAUD_USARTFP_MODE>>

pub fn baud(&mut self) -> BAUD_W<'_>

Bits 0:15 - Baud Rate Value

impl W<u8, Reg<u8, _RXPL>>

pub fn rxpl(&mut self) -> RXPL_W<'_>

Bits 0:7 - Receive Pulse Length

impl W<u8, Reg<u8, _INTENCLR>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Disable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Disable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Disable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Disable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Disable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Disable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Disable

impl W<u8, Reg<u8, _INTENSET>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt Enable

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt Enable

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt Enable

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt Enable

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt Enable

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn dre(&mut self) -> DRE_W<'_>

Bit 0 - Data Register Empty Interrupt

pub fn txc(&mut self) -> TXC_W<'_>

Bit 1 - Transmit Complete Interrupt

pub fn rxc(&mut self) -> RXC_W<'_>

Bit 2 - Receive Complete Interrupt

pub fn rxs(&mut self) -> RXS_W<'_>

Bit 3 - Receive Start Interrupt

pub fn ctsic(&mut self) -> CTSIC_W<'_>

Bit 4 - Clear To Send Input Change Interrupt

pub fn rxbrk(&mut self) -> RXBRK_W<'_>

Bit 5 - Break Received Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 7 - Combined Error Interrupt

impl W<u16, Reg<u16, _STATUS>>

pub fn perr(&mut self) -> PERR_W<'_>

Bit 0 - Parity Error

pub fn ferr(&mut self) -> FERR_W<'_>

Bit 1 - Frame Error

pub fn bufovf(&mut self) -> BUFOVF_W<'_>

Bit 2 - Buffer Overflow

pub fn cts(&mut self) -> CTS_W<'_>

Bit 3 - Clear To Send

pub fn isf(&mut self) -> ISF_W<'_>

Bit 4 - Inconsistent Sync Field

pub fn coll(&mut self) -> COLL_W<'_>

Bit 5 - Collision Detected

pub fn txe(&mut self) -> TXE_W<'_>

Bit 6 - Transmitter Empty

pub fn iter(&mut self) -> ITER_W<'_>

Bit 7 - Maximum Number of Repetitions Reached

impl W<u16, Reg<u16, _LENGTH>>

pub fn len(&mut self) -> LEN_W<'_>

Bits 0:7 - Data Length

pub fn lenen(&mut self) -> LENEN_W<'_>

Bits 8:9 - Data Length Enable

impl W<u32, Reg<u32, _DATA>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgstop(&mut self) -> DBGSTOP_W<'_>

Bit 0 - Debug Mode

impl W<u32, Reg<u32, _INTENCLR>>

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 0 - BOD33 Ready

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 1 - BOD33 Detection

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 2 - BOD33 Synchronization Ready

pub fn vregrdy(&mut self) -> VREGRDY_W<'_>

Bit 8 - Voltage Regulator Ready

pub fn vcorerdy(&mut self) -> VCORERDY_W<'_>

Bit 10 - VDDCORE Ready

impl W<u32, Reg<u32, _INTENSET>>

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 0 - BOD33 Ready

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 1 - BOD33 Detection

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 2 - BOD33 Synchronization Ready

pub fn vregrdy(&mut self) -> VREGRDY_W<'_>

Bit 8 - Voltage Regulator Ready

pub fn vcorerdy(&mut self) -> VCORERDY_W<'_>

Bit 10 - VDDCORE Ready

impl W<u32, Reg<u32, _INTFLAG>>

pub fn bod33rdy(&mut self) -> BOD33RDY_W<'_>

Bit 0 - BOD33 Ready

pub fn bod33det(&mut self) -> BOD33DET_W<'_>

Bit 1 - BOD33 Detection

pub fn b33srdy(&mut self) -> B33SRDY_W<'_>

Bit 2 - BOD33 Synchronization Ready

pub fn vregrdy(&mut self) -> VREGRDY_W<'_>

Bit 8 - Voltage Regulator Ready

pub fn vcorerdy(&mut self) -> VCORERDY_W<'_>

Bit 10 - VDDCORE Ready

impl W<u32, Reg<u32, _BOD33>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn action(&mut self) -> ACTION_W<'_>

Bits 2:3 - Action when Threshold Crossed

pub fn stdbycfg(&mut self) -> STDBYCFG_W<'_>

Bit 4 - Configuration in Standby mode

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 5 - Run in Standby mode

pub fn runhib(&mut self) -> RUNHIB_W<'_>

Bit 6 - Run in Hibernate mode

pub fn runbkup(&mut self) -> RUNBKUP_W<'_>

Bit 7 - Run in Backup mode

pub fn hyst(&mut self) -> HYST_W<'_>

Bits 8:11 - Hysteresis value

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 12:14 - Prescaler Select

pub fn level(&mut self) -> LEVEL_W<'_>

Bits 16:23 - Threshold Level for VDD

pub fn vbatlevel(&mut self) -> VBATLEVEL_W<'_>

Bits 24:31 - Threshold Level in battery backup sleep mode for VBAT

impl W<u32, Reg<u32, _VREG>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn sel(&mut self) -> SEL_W<'_>

Bit 2 - Voltage Regulator Selection

pub fn runbkup(&mut self) -> RUNBKUP_W<'_>

Bit 7 - Run in Backup mode

pub fn vsen(&mut self) -> VSEN_W<'_>

Bit 16 - Voltage Scaling Enable

pub fn vsper(&mut self) -> VSPER_W<'_>

Bits 24:26 - Voltage Scaling Period

impl W<u32, Reg<u32, _VREF>>

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 1 - Temperature Sensor Output Enable

pub fn vrefoe(&mut self) -> VREFOE_W<'_>

Bit 2 - Voltage Reference Output Enable

pub fn tssel(&mut self) -> TSSEL_W<'_>

Bit 3 - Temperature Sensor Selection

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run during Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - On Demand Contrl

pub fn sel(&mut self) -> SEL_W<'_>

Bits 16:19 - Voltage Reference Selection

impl W<u32, Reg<u32, _BBPS>>

pub fn conf(&mut self) -> CONF_W<'_>

Bit 0 - Battery Backup Configuration

pub fn wakeen(&mut self) -> WAKEEN_W<'_>

Bit 2 - Wake Enable

impl W<u32, Reg<u32, _BKOUT>>

pub fn enout0(&mut self) -> ENOUT0_W<'_>

Bit 0 - Enable OUT0

pub fn enout1(&mut self) -> ENOUT1_W<'_>

Bit 1 - Enable OUT1

pub fn clrout0(&mut self) -> CLROUT0_W<'_>

Bit 8 - Clear OUT0

pub fn clrout1(&mut self) -> CLROUT1_W<'_>

Bit 9 - Clear OUT1

pub fn setout0(&mut self) -> SETOUT0_W<'_>

Bit 16 - Set OUT0

pub fn setout1(&mut self) -> SETOUT1_W<'_>

Bit 17 - Set OUT1

pub fn rtctglout0(&mut self) -> RTCTGLOUT0_W<'_>

Bit 24 - RTC Toggle OUT0

pub fn rtctglout1(&mut self) -> RTCTGLOUT1_W<'_>

Bit 25 - RTC Toggle OUT1

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Timer Counter Mode

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 4:5 - Prescaler and Counter Synchronization

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run during Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - Clock On Demand

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 11 - Auto Lock

pub fn capten0(&mut self) -> CAPTEN0_W<'_>

Bit 16 - Capture Channel 0 Enable

pub fn capten1(&mut self) -> CAPTEN1_W<'_>

Bit 17 - Capture Channel 1 Enable

pub fn copen0(&mut self) -> COPEN0_W<'_>

Bit 20 - Capture On Pin 0 Enable

pub fn copen1(&mut self) -> COPEN1_W<'_>

Bit 21 - Capture On Pin 1 Enable

pub fn captmode0(&mut self) -> CAPTMODE0_W<'_>

Bits 24:25 - Capture Mode Channel 0

pub fn captmode1(&mut self) -> CAPTMODE1_W<'_>

Bits 27:28 - Capture mode Channel 1

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Event Input Polarity

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - MC Event Output Enable 0

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - MC Event Output Enable 1

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Disable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Disable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Disable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Disable 1

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Enable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Enable 1

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Flag

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Flag

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Flag 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Flag 1

impl W<u8, Reg<u8, _STATUS>>

pub fn stop(&mut self) -> STOP_W<'_>

Bit 0 - Stop Status Flag

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Slave Status Flag

pub fn perbufv(&mut self) -> PERBUFV_W<'_>

Bit 3 - Synchronization Busy Status

pub fn ccbufv0(&mut self) -> CCBUFV0_W<'_>

Bit 4 - Compare channel buffer 0 valid

pub fn ccbufv1(&mut self) -> CCBUFV1_W<'_>

Bit 5 - Compare channel buffer 1 valid

impl W<u8, Reg<u8, _WAVE>>

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 0:1 - Waveform Generation Mode

impl W<u8, Reg<u8, _DRVCTRL>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform Invert Enable 0

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform Invert Enable 1

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u8, Reg<u8, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:7 - Counter Value

impl W<u8, Reg<u8, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:7 - Period Value

impl W<u8, Reg<u8, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:7 - Counter/Compare Value

impl W<u8, Reg<u8, _PERBUF>>

pub fn perbuf(&mut self) -> PERBUF_W<'_>

Bits 0:7 - Period Buffer Value

impl W<u8, Reg<u8, _CCBUF>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:7 - Counter/Compare Buffer Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Timer Counter Mode

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 4:5 - Prescaler and Counter Synchronization

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run during Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - Clock On Demand

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 11 - Auto Lock

pub fn capten0(&mut self) -> CAPTEN0_W<'_>

Bit 16 - Capture Channel 0 Enable

pub fn capten1(&mut self) -> CAPTEN1_W<'_>

Bit 17 - Capture Channel 1 Enable

pub fn copen0(&mut self) -> COPEN0_W<'_>

Bit 20 - Capture On Pin 0 Enable

pub fn copen1(&mut self) -> COPEN1_W<'_>

Bit 21 - Capture On Pin 1 Enable

pub fn captmode0(&mut self) -> CAPTMODE0_W<'_>

Bits 24:25 - Capture Mode Channel 0

pub fn captmode1(&mut self) -> CAPTMODE1_W<'_>

Bits 27:28 - Capture mode Channel 1

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Event Input Polarity

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - MC Event Output Enable 0

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - MC Event Output Enable 1

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Disable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Disable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Disable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Disable 1

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Enable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Enable 1

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Flag

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Flag

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Flag 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Flag 1

impl W<u8, Reg<u8, _STATUS>>

pub fn stop(&mut self) -> STOP_W<'_>

Bit 0 - Stop Status Flag

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Slave Status Flag

pub fn perbufv(&mut self) -> PERBUFV_W<'_>

Bit 3 - Synchronization Busy Status

pub fn ccbufv0(&mut self) -> CCBUFV0_W<'_>

Bit 4 - Compare channel buffer 0 valid

pub fn ccbufv1(&mut self) -> CCBUFV1_W<'_>

Bit 5 - Compare channel buffer 1 valid

impl W<u8, Reg<u8, _WAVE>>

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 0:1 - Waveform Generation Mode

impl W<u8, Reg<u8, _DRVCTRL>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform Invert Enable 0

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform Invert Enable 1

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u16, Reg<u16, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Counter Value

impl W<u16, Reg<u16, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:15 - Counter/Compare Value

impl W<u16, Reg<u16, _CCBUF>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:15 - Counter/Compare Buffer Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bits 2:3 - Timer Counter Mode

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 4:5 - Prescaler and Counter Synchronization

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run during Standby

pub fn ondemand(&mut self) -> ONDEMAND_W<'_>

Bit 7 - Clock On Demand

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 11 - Auto Lock

pub fn capten0(&mut self) -> CAPTEN0_W<'_>

Bit 16 - Capture Channel 0 Enable

pub fn capten1(&mut self) -> CAPTEN1_W<'_>

Bit 17 - Capture Channel 1 Enable

pub fn copen0(&mut self) -> COPEN0_W<'_>

Bit 20 - Capture On Pin 0 Enable

pub fn copen1(&mut self) -> COPEN1_W<'_>

Bit 21 - Capture On Pin 1 Enable

pub fn captmode0(&mut self) -> CAPTMODE0_W<'_>

Bits 24:25 - Capture Mode Channel 0

pub fn captmode1(&mut self) -> CAPTMODE1_W<'_>

Bits 27:28 - Capture mode Channel 1

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot on Counter

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - Command

impl W<u16, Reg<u16, _EVCTRL>>

pub fn evact(&mut self) -> EVACT_W<'_>

Bits 0:2 - Event Action

pub fn tcinv(&mut self) -> TCINV_W<'_>

Bit 4 - TC Event Input Polarity

pub fn tcei(&mut self) -> TCEI_W<'_>

Bit 5 - TC Event Enable

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Event Output Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 12 - MC Event Output Enable 0

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 13 - MC Event Output Enable 1

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Disable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Disable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Disable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Disable 1

impl W<u8, Reg<u8, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Enable 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Enable 1

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - OVF Interrupt Flag

pub fn err(&mut self) -> ERR_W<'_>

Bit 1 - ERR Interrupt Flag

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 4 - MC Interrupt Flag 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 5 - MC Interrupt Flag 1

impl W<u8, Reg<u8, _STATUS>>

pub fn stop(&mut self) -> STOP_W<'_>

Bit 0 - Stop Status Flag

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 1 - Slave Status Flag

pub fn perbufv(&mut self) -> PERBUFV_W<'_>

Bit 3 - Synchronization Busy Status

pub fn ccbufv0(&mut self) -> CCBUFV0_W<'_>

Bit 4 - Compare channel buffer 0 valid

pub fn ccbufv1(&mut self) -> CCBUFV1_W<'_>

Bit 5 - Compare channel buffer 1 valid

impl W<u8, Reg<u8, _WAVE>>

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 0:1 - Waveform Generation Mode

impl W<u8, Reg<u8, _DRVCTRL>>

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 0 - Output Waveform Invert Enable 0

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 1 - Output Waveform Invert Enable 1

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Run During Debug

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:31 - Counter Value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:31 - Counter/Compare Value

impl W<u32, Reg<u32, _CCBUF>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:31 - Counter/Compare Buffer Value

impl W<u32, Reg<u32, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn resolution(&mut self) -> RESOLUTION_W<'_>

Bits 5:6 - Enhanced Resolution

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 8:10 - Prescaler

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 11 - Run in Standby

pub fn prescsync(&mut self) -> PRESCSYNC_W<'_>

Bits 12:13 - Prescaler and Counter Synchronization Selection

pub fn alock(&mut self) -> ALOCK_W<'_>

Bit 14 - Auto Lock

pub fn msync(&mut self) -> MSYNC_W<'_>

Bit 15 - Master Synchronization (only for TCC Slave Instance)

pub fn dmaos(&mut self) -> DMAOS_W<'_>

Bit 23 - DMA One-shot Trigger Mode

pub fn cpten0(&mut self) -> CPTEN0_W<'_>

Bit 24 - Capture Channel 0 Enable

pub fn cpten1(&mut self) -> CPTEN1_W<'_>

Bit 25 - Capture Channel 1 Enable

pub fn cpten2(&mut self) -> CPTEN2_W<'_>

Bit 26 - Capture Channel 2 Enable

pub fn cpten3(&mut self) -> CPTEN3_W<'_>

Bit 27 - Capture Channel 3 Enable

pub fn cpten4(&mut self) -> CPTEN4_W<'_>

Bit 28 - Capture Channel 4 Enable

pub fn cpten5(&mut self) -> CPTEN5_W<'_>

Bit 29 - Capture Channel 5 Enable

impl W<u8, Reg<u8, _CTRLBCLR>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn idxcmd(&mut self) -> IDXCMD_W<'_>

Bits 3:4 - Ramp Index Command

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - TCC Command

impl W<u8, Reg<u8, _CTRLBSET>>

pub fn dir(&mut self) -> DIR_W<'_>

Bit 0 - Counter Direction

pub fn lupd(&mut self) -> LUPD_W<'_>

Bit 1 - Lock Update

pub fn oneshot(&mut self) -> ONESHOT_W<'_>

Bit 2 - One-Shot

pub fn idxcmd(&mut self) -> IDXCMD_W<'_>

Bits 3:4 - Ramp Index Command

pub fn cmd(&mut self) -> CMD_W<'_>

Bits 5:7 - TCC Command

impl W<u32, Reg<u32, _FCTRLA>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Fault A Source

pub fn keep(&mut self) -> KEEP_W<'_>

Bit 3 - Fault A Keeper

pub fn qual(&mut self) -> QUAL_W<'_>

Bit 4 - Fault A Qualification

pub fn blank(&mut self) -> BLANK_W<'_>

Bits 5:6 - Fault A Blanking Mode

pub fn restart(&mut self) -> RESTART_W<'_>

Bit 7 - Fault A Restart

pub fn halt(&mut self) -> HALT_W<'_>

Bits 8:9 - Fault A Halt Mode

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 10:11 - Fault A Capture Channel

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bits 12:14 - Fault A Capture Action

pub fn blankpresc(&mut self) -> BLANKPRESC_W<'_>

Bit 15 - Fault A Blanking Prescaler

pub fn blankval(&mut self) -> BLANKVAL_W<'_>

Bits 16:23 - Fault A Blanking Time

pub fn filterval(&mut self) -> FILTERVAL_W<'_>

Bits 24:27 - Fault A Filter Value

impl W<u32, Reg<u32, _FCTRLB>>

pub fn src(&mut self) -> SRC_W<'_>

Bits 0:1 - Fault B Source

pub fn keep(&mut self) -> KEEP_W<'_>

Bit 3 - Fault B Keeper

pub fn qual(&mut self) -> QUAL_W<'_>

Bit 4 - Fault B Qualification

pub fn blank(&mut self) -> BLANK_W<'_>

Bits 5:6 - Fault B Blanking Mode

pub fn restart(&mut self) -> RESTART_W<'_>

Bit 7 - Fault B Restart

pub fn halt(&mut self) -> HALT_W<'_>

Bits 8:9 - Fault B Halt Mode

pub fn chsel(&mut self) -> CHSEL_W<'_>

Bits 10:11 - Fault B Capture Channel

pub fn capture(&mut self) -> CAPTURE_W<'_>

Bits 12:14 - Fault B Capture Action

pub fn blankpresc(&mut self) -> BLANKPRESC_W<'_>

Bit 15 - Fault B Blanking Prescaler

pub fn blankval(&mut self) -> BLANKVAL_W<'_>

Bits 16:23 - Fault B Blanking Time

pub fn filterval(&mut self) -> FILTERVAL_W<'_>

Bits 24:27 - Fault B Filter Value

impl W<u32, Reg<u32, _WEXCTRL>>

pub fn otmx(&mut self) -> OTMX_W<'_>

Bits 0:1 - Output Matrix

pub fn dtien0(&mut self) -> DTIEN0_W<'_>

Bit 8 - Dead-time Insertion Generator 0 Enable

pub fn dtien1(&mut self) -> DTIEN1_W<'_>

Bit 9 - Dead-time Insertion Generator 1 Enable

pub fn dtien2(&mut self) -> DTIEN2_W<'_>

Bit 10 - Dead-time Insertion Generator 2 Enable

pub fn dtien3(&mut self) -> DTIEN3_W<'_>

Bit 11 - Dead-time Insertion Generator 3 Enable

pub fn dtls(&mut self) -> DTLS_W<'_>

Bits 16:23 - Dead-time Low Side Outputs Value

pub fn dths(&mut self) -> DTHS_W<'_>

Bits 24:31 - Dead-time High Side Outputs Value

impl W<u32, Reg<u32, _DRVCTRL>>

pub fn nre0(&mut self) -> NRE0_W<'_>

Bit 0 - Non-Recoverable State 0 Output Enable

pub fn nre1(&mut self) -> NRE1_W<'_>

Bit 1 - Non-Recoverable State 1 Output Enable

pub fn nre2(&mut self) -> NRE2_W<'_>

Bit 2 - Non-Recoverable State 2 Output Enable

pub fn nre3(&mut self) -> NRE3_W<'_>

Bit 3 - Non-Recoverable State 3 Output Enable

pub fn nre4(&mut self) -> NRE4_W<'_>

Bit 4 - Non-Recoverable State 4 Output Enable

pub fn nre5(&mut self) -> NRE5_W<'_>

Bit 5 - Non-Recoverable State 5 Output Enable

pub fn nre6(&mut self) -> NRE6_W<'_>

Bit 6 - Non-Recoverable State 6 Output Enable

pub fn nre7(&mut self) -> NRE7_W<'_>

Bit 7 - Non-Recoverable State 7 Output Enable

pub fn nrv0(&mut self) -> NRV0_W<'_>

Bit 8 - Non-Recoverable State 0 Output Value

pub fn nrv1(&mut self) -> NRV1_W<'_>

Bit 9 - Non-Recoverable State 1 Output Value

pub fn nrv2(&mut self) -> NRV2_W<'_>

Bit 10 - Non-Recoverable State 2 Output Value

pub fn nrv3(&mut self) -> NRV3_W<'_>

Bit 11 - Non-Recoverable State 3 Output Value

pub fn nrv4(&mut self) -> NRV4_W<'_>

Bit 12 - Non-Recoverable State 4 Output Value

pub fn nrv5(&mut self) -> NRV5_W<'_>

Bit 13 - Non-Recoverable State 5 Output Value

pub fn nrv6(&mut self) -> NRV6_W<'_>

Bit 14 - Non-Recoverable State 6 Output Value

pub fn nrv7(&mut self) -> NRV7_W<'_>

Bit 15 - Non-Recoverable State 7 Output Value

pub fn inven0(&mut self) -> INVEN0_W<'_>

Bit 16 - Output Waveform 0 Inversion

pub fn inven1(&mut self) -> INVEN1_W<'_>

Bit 17 - Output Waveform 1 Inversion

pub fn inven2(&mut self) -> INVEN2_W<'_>

Bit 18 - Output Waveform 2 Inversion

pub fn inven3(&mut self) -> INVEN3_W<'_>

Bit 19 - Output Waveform 3 Inversion

pub fn inven4(&mut self) -> INVEN4_W<'_>

Bit 20 - Output Waveform 4 Inversion

pub fn inven5(&mut self) -> INVEN5_W<'_>

Bit 21 - Output Waveform 5 Inversion

pub fn inven6(&mut self) -> INVEN6_W<'_>

Bit 22 - Output Waveform 6 Inversion

pub fn inven7(&mut self) -> INVEN7_W<'_>

Bit 23 - Output Waveform 7 Inversion

pub fn filterval0(&mut self) -> FILTERVAL0_W<'_>

Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value

pub fn filterval1(&mut self) -> FILTERVAL1_W<'_>

Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value

impl W<u8, Reg<u8, _DBGCTRL>>

pub fn dbgrun(&mut self) -> DBGRUN_W<'_>

Bit 0 - Debug Running Mode

pub fn fddbd(&mut self) -> FDDBD_W<'_>

Bit 2 - Fault Detection on Debug Break Detection

impl W<u32, Reg<u32, _EVCTRL>>

pub fn evact0(&mut self) -> EVACT0_W<'_>

Bits 0:2 - Timer/counter Input Event0 Action

pub fn evact1(&mut self) -> EVACT1_W<'_>

Bits 3:5 - Timer/counter Input Event1 Action

pub fn cntsel(&mut self) -> CNTSEL_W<'_>

Bits 6:7 - Timer/counter Output Event Mode

pub fn ovfeo(&mut self) -> OVFEO_W<'_>

Bit 8 - Overflow/Underflow Output Event Enable

pub fn trgeo(&mut self) -> TRGEO_W<'_>

Bit 9 - Retrigger Output Event Enable

pub fn cnteo(&mut self) -> CNTEO_W<'_>

Bit 10 - Timer/counter Output Event Enable

pub fn tcinv0(&mut self) -> TCINV0_W<'_>

Bit 12 - Inverted Event 0 Input Enable

pub fn tcinv1(&mut self) -> TCINV1_W<'_>

Bit 13 - Inverted Event 1 Input Enable

pub fn tcei0(&mut self) -> TCEI0_W<'_>

Bit 14 - Timer/counter Event 0 Input Enable

pub fn tcei1(&mut self) -> TCEI1_W<'_>

Bit 15 - Timer/counter Event 1 Input Enable

pub fn mcei0(&mut self) -> MCEI0_W<'_>

Bit 16 - Match or Capture Channel 0 Event Input Enable

pub fn mcei1(&mut self) -> MCEI1_W<'_>

Bit 17 - Match or Capture Channel 1 Event Input Enable

pub fn mcei2(&mut self) -> MCEI2_W<'_>

Bit 18 - Match or Capture Channel 2 Event Input Enable

pub fn mcei3(&mut self) -> MCEI3_W<'_>

Bit 19 - Match or Capture Channel 3 Event Input Enable

pub fn mcei4(&mut self) -> MCEI4_W<'_>

Bit 20 - Match or Capture Channel 4 Event Input Enable

pub fn mcei5(&mut self) -> MCEI5_W<'_>

Bit 21 - Match or Capture Channel 5 Event Input Enable

pub fn mceo0(&mut self) -> MCEO0_W<'_>

Bit 24 - Match or Capture Channel 0 Event Output Enable

pub fn mceo1(&mut self) -> MCEO1_W<'_>

Bit 25 - Match or Capture Channel 1 Event Output Enable

pub fn mceo2(&mut self) -> MCEO2_W<'_>

Bit 26 - Match or Capture Channel 2 Event Output Enable

pub fn mceo3(&mut self) -> MCEO3_W<'_>

Bit 27 - Match or Capture Channel 3 Event Output Enable

pub fn mceo4(&mut self) -> MCEO4_W<'_>

Bit 28 - Match or Capture Channel 4 Event Output Enable

pub fn mceo5(&mut self) -> MCEO5_W<'_>

Bit 29 - Match or Capture Channel 5 Event Output Enable

impl W<u32, Reg<u32, _INTENCLR>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger Interrupt Enable

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error Interrupt Enable

pub fn ufs(&mut self) -> UFS_W<'_>

Bit 10 - Non-Recoverable Update Fault Interrupt Enable

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault Interrupt Enable

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A Interrupt Enable

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B Interrupt Enable

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 Interrupt Enable

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture Channel 1 Interrupt Enable

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture Channel 2 Interrupt Enable

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture Channel 3 Interrupt Enable

pub fn mc4(&mut self) -> MC4_W<'_>

Bit 20 - Match or Capture Channel 4 Interrupt Enable

pub fn mc5(&mut self) -> MC5_W<'_>

Bit 21 - Match or Capture Channel 5 Interrupt Enable

impl W<u32, Reg<u32, _INTENSET>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow Interrupt Enable

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger Interrupt Enable

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter Interrupt Enable

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error Interrupt Enable

pub fn ufs(&mut self) -> UFS_W<'_>

Bit 10 - Non-Recoverable Update Fault Interrupt Enable

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault Interrupt Enable

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A Interrupt Enable

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B Interrupt Enable

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 Interrupt Enable

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 Interrupt Enable

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture Channel 0 Interrupt Enable

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture Channel 1 Interrupt Enable

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture Channel 2 Interrupt Enable

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture Channel 3 Interrupt Enable

pub fn mc4(&mut self) -> MC4_W<'_>

Bit 20 - Match or Capture Channel 4 Interrupt Enable

pub fn mc5(&mut self) -> MC5_W<'_>

Bit 21 - Match or Capture Channel 5 Interrupt Enable

impl W<u32, Reg<u32, _INTFLAG>>

pub fn ovf(&mut self) -> OVF_W<'_>

Bit 0 - Overflow

pub fn trg(&mut self) -> TRG_W<'_>

Bit 1 - Retrigger

pub fn cnt(&mut self) -> CNT_W<'_>

Bit 2 - Counter

pub fn err(&mut self) -> ERR_W<'_>

Bit 3 - Error

pub fn ufs(&mut self) -> UFS_W<'_>

Bit 10 - Non-Recoverable Update Fault

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 11 - Non-Recoverable Debug Fault

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1

pub fn mc0(&mut self) -> MC0_W<'_>

Bit 16 - Match or Capture 0

pub fn mc1(&mut self) -> MC1_W<'_>

Bit 17 - Match or Capture 1

pub fn mc2(&mut self) -> MC2_W<'_>

Bit 18 - Match or Capture 2

pub fn mc3(&mut self) -> MC3_W<'_>

Bit 19 - Match or Capture 3

pub fn mc4(&mut self) -> MC4_W<'_>

Bit 20 - Match or Capture 4

pub fn mc5(&mut self) -> MC5_W<'_>

Bit 21 - Match or Capture 5

impl W<u32, Reg<u32, _STATUS>>

pub fn stop(&mut self) -> STOP_W<'_>

Bit 0 - Stop

pub fn idx(&mut self) -> IDX_W<'_>

Bit 1 - Ramp

pub fn ufs(&mut self) -> UFS_W<'_>

Bit 2 - Non-recoverable Update Fault State

pub fn dfs(&mut self) -> DFS_W<'_>

Bit 3 - Non-Recoverable Debug Fault State

pub fn slave(&mut self) -> SLAVE_W<'_>

Bit 4 - Slave

pub fn pattbufv(&mut self) -> PATTBUFV_W<'_>

Bit 5 - Pattern Buffer Valid

pub fn perbufv(&mut self) -> PERBUFV_W<'_>

Bit 7 - Period Buffer Valid

pub fn faultain(&mut self) -> FAULTAIN_W<'_>

Bit 8 - Recoverable Fault A Input

pub fn faultbin(&mut self) -> FAULTBIN_W<'_>

Bit 9 - Recoverable Fault B Input

pub fn fault0in(&mut self) -> FAULT0IN_W<'_>

Bit 10 - Non-Recoverable Fault0 Input

pub fn fault1in(&mut self) -> FAULT1IN_W<'_>

Bit 11 - Non-Recoverable Fault1 Input

pub fn faulta(&mut self) -> FAULTA_W<'_>

Bit 12 - Recoverable Fault A State

pub fn faultb(&mut self) -> FAULTB_W<'_>

Bit 13 - Recoverable Fault B State

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 14 - Non-Recoverable Fault 0 State

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 15 - Non-Recoverable Fault 1 State

pub fn ccbufv0(&mut self) -> CCBUFV0_W<'_>

Bit 16 - Compare Channel 0 Buffer Valid

pub fn ccbufv1(&mut self) -> CCBUFV1_W<'_>

Bit 17 - Compare Channel 1 Buffer Valid

pub fn ccbufv2(&mut self) -> CCBUFV2_W<'_>

Bit 18 - Compare Channel 2 Buffer Valid

pub fn ccbufv3(&mut self) -> CCBUFV3_W<'_>

Bit 19 - Compare Channel 3 Buffer Valid

pub fn ccbufv4(&mut self) -> CCBUFV4_W<'_>

Bit 20 - Compare Channel 4 Buffer Valid

pub fn ccbufv5(&mut self) -> CCBUFV5_W<'_>

Bit 21 - Compare Channel 5 Buffer Valid

pub fn cmp0(&mut self) -> CMP0_W<'_>

Bit 24 - Compare Channel 0 Value

pub fn cmp1(&mut self) -> CMP1_W<'_>

Bit 25 - Compare Channel 1 Value

pub fn cmp2(&mut self) -> CMP2_W<'_>

Bit 26 - Compare Channel 2 Value

pub fn cmp3(&mut self) -> CMP3_W<'_>

Bit 27 - Compare Channel 3 Value

pub fn cmp4(&mut self) -> CMP4_W<'_>

Bit 28 - Compare Channel 4 Value

pub fn cmp5(&mut self) -> CMP5_W<'_>

Bit 29 - Compare Channel 5 Value

impl W<u32, Reg<u32, _COUNT>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH4_MODE>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 4:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH5_MODE>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 5:23 - Counter Value

impl W<u32, Reg<u32, _COUNT_DITH6_MODE>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 6:23 - Counter Value

impl W<u16, Reg<u16, _PATT>>

pub fn pge0(&mut self) -> PGE0_W<'_>

Bit 0 - Pattern Generator 0 Output Enable

pub fn pge1(&mut self) -> PGE1_W<'_>

Bit 1 - Pattern Generator 1 Output Enable

pub fn pge2(&mut self) -> PGE2_W<'_>

Bit 2 - Pattern Generator 2 Output Enable

pub fn pge3(&mut self) -> PGE3_W<'_>

Bit 3 - Pattern Generator 3 Output Enable

pub fn pge4(&mut self) -> PGE4_W<'_>

Bit 4 - Pattern Generator 4 Output Enable

pub fn pge5(&mut self) -> PGE5_W<'_>

Bit 5 - Pattern Generator 5 Output Enable

pub fn pge6(&mut self) -> PGE6_W<'_>

Bit 6 - Pattern Generator 6 Output Enable

pub fn pge7(&mut self) -> PGE7_W<'_>

Bit 7 - Pattern Generator 7 Output Enable

pub fn pgv0(&mut self) -> PGV0_W<'_>

Bit 8 - Pattern Generator 0 Output Value

pub fn pgv1(&mut self) -> PGV1_W<'_>

Bit 9 - Pattern Generator 1 Output Value

pub fn pgv2(&mut self) -> PGV2_W<'_>

Bit 10 - Pattern Generator 2 Output Value

pub fn pgv3(&mut self) -> PGV3_W<'_>

Bit 11 - Pattern Generator 3 Output Value

pub fn pgv4(&mut self) -> PGV4_W<'_>

Bit 12 - Pattern Generator 4 Output Value

pub fn pgv5(&mut self) -> PGV5_W<'_>

Bit 13 - Pattern Generator 5 Output Value

pub fn pgv6(&mut self) -> PGV6_W<'_>

Bit 14 - Pattern Generator 6 Output Value

pub fn pgv7(&mut self) -> PGV7_W<'_>

Bit 15 - Pattern Generator 7 Output Value

impl W<u32, Reg<u32, _WAVE>>

pub fn wavegen(&mut self) -> WAVEGEN_W<'_>

Bits 0:2 - Waveform Generation

pub fn ramp(&mut self) -> RAMP_W<'_>

Bits 4:5 - Ramp Mode

pub fn ciperen(&mut self) -> CIPEREN_W<'_>

Bit 7 - Circular period Enable

pub fn ciccen0(&mut self) -> CICCEN0_W<'_>

Bit 8 - Circular Channel 0 Enable

pub fn ciccen1(&mut self) -> CICCEN1_W<'_>

Bit 9 - Circular Channel 1 Enable

pub fn ciccen2(&mut self) -> CICCEN2_W<'_>

Bit 10 - Circular Channel 2 Enable

pub fn ciccen3(&mut self) -> CICCEN3_W<'_>

Bit 11 - Circular Channel 3 Enable

pub fn pol0(&mut self) -> POL0_W<'_>

Bit 16 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W<'_>

Bit 17 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W<'_>

Bit 18 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W<'_>

Bit 19 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W<'_>

Bit 20 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W<'_>

Bit 21 - Channel 5 Polarity

pub fn swap0(&mut self) -> SWAP0_W<'_>

Bit 24 - Swap DTI Output Pair 0

pub fn swap1(&mut self) -> SWAP1_W<'_>

Bit 25 - Swap DTI Output Pair 1

pub fn swap2(&mut self) -> SWAP2_W<'_>

Bit 26 - Swap DTI Output Pair 2

pub fn swap3(&mut self) -> SWAP3_W<'_>

Bit 27 - Swap DTI Output Pair 3

impl W<u32, Reg<u32, _PER>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH4_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:3 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 4:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH5_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:4 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 5:23 - Period Value

impl W<u32, Reg<u32, _PER_DITH6_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:5 - Dithering Cycle Number

pub fn per(&mut self) -> PER_W<'_>

Bits 6:23 - Period Value

impl W<u32, Reg<u32, _CC>>

pub fn cc(&mut self) -> CC_W<'_>

Bits 0:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH4_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:3 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 4:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH5_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:4 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 5:23 - Channel Compare/Capture Value

impl W<u32, Reg<u32, _CC_DITH6_MODE>>

pub fn dither(&mut self) -> DITHER_W<'_>

Bits 0:5 - Dithering Cycle Number

pub fn cc(&mut self) -> CC_W<'_>

Bits 6:23 - Channel Compare/Capture Value

impl W<u16, Reg<u16, _PATTBUF>>

pub fn pgeb0(&mut self) -> PGEB0_W<'_>

Bit 0 - Pattern Generator 0 Output Enable Buffer

pub fn pgeb1(&mut self) -> PGEB1_W<'_>

Bit 1 - Pattern Generator 1 Output Enable Buffer

pub fn pgeb2(&mut self) -> PGEB2_W<'_>

Bit 2 - Pattern Generator 2 Output Enable Buffer

pub fn pgeb3(&mut self) -> PGEB3_W<'_>

Bit 3 - Pattern Generator 3 Output Enable Buffer

pub fn pgeb4(&mut self) -> PGEB4_W<'_>

Bit 4 - Pattern Generator 4 Output Enable Buffer

pub fn pgeb5(&mut self) -> PGEB5_W<'_>

Bit 5 - Pattern Generator 5 Output Enable Buffer

pub fn pgeb6(&mut self) -> PGEB6_W<'_>

Bit 6 - Pattern Generator 6 Output Enable Buffer

pub fn pgeb7(&mut self) -> PGEB7_W<'_>

Bit 7 - Pattern Generator 7 Output Enable Buffer

pub fn pgvb0(&mut self) -> PGVB0_W<'_>

Bit 8 - Pattern Generator 0 Output Enable

pub fn pgvb1(&mut self) -> PGVB1_W<'_>

Bit 9 - Pattern Generator 1 Output Enable

pub fn pgvb2(&mut self) -> PGVB2_W<'_>

Bit 10 - Pattern Generator 2 Output Enable

pub fn pgvb3(&mut self) -> PGVB3_W<'_>

Bit 11 - Pattern Generator 3 Output Enable

pub fn pgvb4(&mut self) -> PGVB4_W<'_>

Bit 12 - Pattern Generator 4 Output Enable

pub fn pgvb5(&mut self) -> PGVB5_W<'_>

Bit 13 - Pattern Generator 5 Output Enable

pub fn pgvb6(&mut self) -> PGVB6_W<'_>

Bit 14 - Pattern Generator 6 Output Enable

pub fn pgvb7(&mut self) -> PGVB7_W<'_>

Bit 15 - Pattern Generator 7 Output Enable

impl W<u32, Reg<u32, _PERBUF>>

pub fn perbuf(&mut self) -> PERBUF_W<'_>

Bits 0:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERBUF_DITH4_MODE>>

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 0:3 - Dithering Buffer Cycle Number

pub fn perbuf(&mut self) -> PERBUF_W<'_>

Bits 4:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERBUF_DITH5_MODE>>

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 0:4 - Dithering Buffer Cycle Number

pub fn perbuf(&mut self) -> PERBUF_W<'_>

Bits 5:23 - Period Buffer Value

impl W<u32, Reg<u32, _PERBUF_DITH6_MODE>>

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 0:5 - Dithering Buffer Cycle Number

pub fn perbuf(&mut self) -> PERBUF_W<'_>

Bits 6:23 - Period Buffer Value

impl W<u32, Reg<u32, _CCBUF>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:23 - Channel Compare/Capture Buffer Value

impl W<u32, Reg<u32, _CCBUF_DITH4_MODE>>

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 0:3 - Channel Compare/Capture Buffer Value

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 4:23 - Dithering Buffer Cycle Number

impl W<u32, Reg<u32, _CCBUF_DITH5_MODE>>

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 0:4 - Dithering Buffer Cycle Number

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 5:23 - Channel Compare/Capture Buffer Value

impl W<u32, Reg<u32, _CCBUF_DITH6_MODE>>

pub fn ditherbuf(&mut self) -> DITHERBUF_W<'_>

Bits 0:5 - Dithering Buffer Cycle Number

pub fn ccbuf(&mut self) -> CCBUF_W<'_>

Bits 6:23 - Channel Compare/Capture Buffer Value

impl W<u8, Reg<u8, _CTRLA>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 6 - Run in Standby

impl W<u8, Reg<u8, _EVCTRL>>

pub fn datardyeo(&mut self) -> DATARDYEO_W<'_>

Bit 0 - Data Ready Event Output

impl W<u8, Reg<u8, _INTENCLR>>

pub fn datardy(&mut self) -> DATARDY_W<'_>

Bit 0 - Data Ready Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn datardy(&mut self) -> DATARDY_W<'_>

Bit 0 - Data Ready Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn datardy(&mut self) -> DATARDY_W<'_>

Bit 0 - Data Ready Interrupt Flag

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby Mode

pub fn mode(&mut self) -> MODE_W<'_>

Bit 7 - Operating Mode

impl W<u8, Reg<u8, _QOSCTRL>>

pub fn cqos(&mut self) -> CQOS_W<'_>

Bits 0:1 - Configuration Quality of Service

pub fn dqos(&mut self) -> DQOS_W<'_>

Bits 2:3 - Data Quality of Service

impl W<u16, Reg<u16, _CTRLB>>

pub fn detach(&mut self) -> DETACH_W<'_>

Bit 0 - Detach

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 1 - Upstream Resume

pub fn spdconf(&mut self) -> SPDCONF_W<'_>

Bits 2:3 - Speed Configuration

pub fn nreply(&mut self) -> NREPLY_W<'_>

Bit 4 - No Reply

pub fn tstj(&mut self) -> TSTJ_W<'_>

Bit 5 - Test mode J

pub fn tstk(&mut self) -> TSTK_W<'_>

Bit 6 - Test mode K

pub fn tstpckt(&mut self) -> TSTPCKT_W<'_>

Bit 7 - Test packet mode

pub fn opmode2(&mut self) -> OPMODE2_W<'_>

Bit 8 - Specific Operational Mode

pub fn gnak(&mut self) -> GNAK_W<'_>

Bit 9 - Global NAK

pub fn lpmhdsk(&mut self) -> LPMHDSK_W<'_>

Bits 10:11 - Link Power Management Handshake

impl W<u8, Reg<u8, _DADD>>

pub fn dadd(&mut self) -> DADD_W<'_>

Bits 0:6 - Device Address

pub fn adden(&mut self) -> ADDEN_W<'_>

Bit 7 - Device Address Enable

impl W<u16, Reg<u16, _INTENCLR>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend Interrupt Enable

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame Interrupt Enable

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset Interrupt Enable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Enable

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume Interrupt Enable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume Interrupt Enable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Enable

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet Interrupt Enable

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend Interrupt Enable

impl W<u16, Reg<u16, _INTENSET>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend Interrupt Enable

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame Interrupt Enable

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset Interrupt Enable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Enable

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume Interrupt Enable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume Interrupt Enable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Enable

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet Interrupt Enable

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 0 - Suspend

pub fn msof(&mut self) -> MSOF_W<'_>

Bit 1 - Micro Start of Frame in High Speed Mode

pub fn sof(&mut self) -> SOF_W<'_>

Bit 2 - Start Of Frame

pub fn eorst(&mut self) -> EORST_W<'_>

Bit 3 - End of Reset

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up

pub fn eorsm(&mut self) -> EORSM_W<'_>

Bit 5 - End Of Resume

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access

pub fn lpmnyet(&mut self) -> LPMNYET_W<'_>

Bit 8 - Link Power Management Not Yet

pub fn lpmsusp(&mut self) -> LPMSUSP_W<'_>

Bit 9 - Link Power Management Suspend

impl W<u32, Reg<u32, _DESCADD>>

pub fn descadd(&mut self) -> DESCADD_W<'_>

Bits 0:31 - Descriptor Address Value

impl W<u16, Reg<u16, _PADCAL>>

pub fn transp(&mut self) -> TRANSP_W<'_>

Bits 0:4 - USB Pad Transp calibration

pub fn transn(&mut self) -> TRANSN_W<'_>

Bits 6:10 - USB Pad Transn calibration

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 12:14 - USB Pad Trim calibration

impl W<u8, Reg<u8, _EPCFG>>

pub fn eptype0(&mut self) -> EPTYPE0_W<'_>

Bits 0:2 - End Point Type0

pub fn eptype1(&mut self) -> EPTYPE1_W<'_>

Bits 4:6 - End Point Type1

pub fn nyetdis(&mut self) -> NYETDIS_W<'_>

Bit 7 - NYET Token Disable

impl W<u8, Reg<u8, _EPSTATUSCLR>>

pub fn dtglout(&mut self) -> DTGLOUT_W<'_>

Bit 0 - Data Toggle OUT Clear

pub fn dtglin(&mut self) -> DTGLIN_W<'_>

Bit 1 - Data Toggle IN Clear

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Current Bank Clear

pub fn stallrq0(&mut self) -> STALLRQ0_W<'_>

Bit 4 - Stall 0 Request Clear

pub fn stallrq1(&mut self) -> STALLRQ1_W<'_>

Bit 5 - Stall 1 Request Clear

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Clear

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Clear

impl W<u8, Reg<u8, _EPSTATUSSET>>

pub fn dtglout(&mut self) -> DTGLOUT_W<'_>

Bit 0 - Data Toggle OUT Set

pub fn dtglin(&mut self) -> DTGLIN_W<'_>

Bit 1 - Data Toggle IN Set

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Current Bank Set

pub fn stallrq0(&mut self) -> STALLRQ0_W<'_>

Bit 4 - Stall 0 Request Set

pub fn stallrq1(&mut self) -> STALLRQ1_W<'_>

Bit 5 - Stall 1 Request Set

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Set

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Set

impl W<u8, Reg<u8, _EPINTFLAG>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/out

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/out

impl W<u8, Reg<u8, _EPINTENCLR>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Disable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Disable

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0 Interrupt Disable

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1 Interrupt Disable

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup Interrupt Disable

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/Out Interrupt Disable

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/Out Interrupt Disable

impl W<u8, Reg<u8, _EPINTENSET>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Enable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Enable

pub fn trfail0(&mut self) -> TRFAIL0_W<'_>

Bit 2 - Error Flow 0 Interrupt Enable

pub fn trfail1(&mut self) -> TRFAIL1_W<'_>

Bit 3 - Error Flow 1 Interrupt Enable

pub fn rxstp(&mut self) -> RXSTP_W<'_>

Bit 4 - Received Setup Interrupt Enable

pub fn stall0(&mut self) -> STALL0_W<'_>

Bit 5 - Stall 0 In/out Interrupt enable

pub fn stall1(&mut self) -> STALL1_W<'_>

Bit 6 - Stall 1 In/out Interrupt enable

impl W<u8, Reg<u8, _CTRLA>>

pub fn swrst(&mut self) -> SWRST_W<'_>

Bit 0 - Software Reset

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn runstdby(&mut self) -> RUNSTDBY_W<'_>

Bit 2 - Run in Standby Mode

pub fn mode(&mut self) -> MODE_W<'_>

Bit 7 - Operating Mode

impl W<u8, Reg<u8, _QOSCTRL>>

pub fn cqos(&mut self) -> CQOS_W<'_>

Bits 0:1 - Configuration Quality of Service

pub fn dqos(&mut self) -> DQOS_W<'_>

Bits 2:3 - Data Quality of Service

impl W<u16, Reg<u16, _CTRLB>>

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 1 - Send USB Resume

pub fn spdconf(&mut self) -> SPDCONF_W<'_>

Bits 2:3 - Speed Configuration for Host

pub fn autoresume(&mut self) -> AUTORESUME_W<'_>

Bit 4 - Auto Resume Enable

pub fn tstj(&mut self) -> TSTJ_W<'_>

Bit 5 - Test mode J

pub fn tstk(&mut self) -> TSTK_W<'_>

Bit 6 - Test mode K

pub fn sofe(&mut self) -> SOFE_W<'_>

Bit 8 - Start of Frame Generation Enable

pub fn busreset(&mut self) -> BUSRESET_W<'_>

Bit 9 - Send USB Reset

pub fn vbusok(&mut self) -> VBUSOK_W<'_>

Bit 10 - VBUS is OK

pub fn l1resume(&mut self) -> L1RESUME_W<'_>

Bit 11 - Send L1 Resume

impl W<u8, Reg<u8, _HSOFC>>

pub fn flenc(&mut self) -> FLENC_W<'_>

Bits 0:3 - Frame Length Control

pub fn flence(&mut self) -> FLENCE_W<'_>

Bit 7 - Frame Length Control Enable

impl W<u8, Reg<u8, _STATUS>>

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 2:3 - Speed Status

pub fn linestate(&mut self) -> LINESTATE_W<'_>

Bits 6:7 - USB Line State Status

impl W<u16, Reg<u16, _FNUM>>

pub fn mfnum(&mut self) -> MFNUM_W<'_>

Bits 0:2 - Micro Frame Number

pub fn fnum(&mut self) -> FNUM_W<'_>

Bits 3:13 - Frame Number

impl W<u16, Reg<u16, _INTENCLR>>

pub fn hsof(&mut self) -> HSOF_W<'_>

Bit 2 - Host Start Of Frame Interrupt Disable

pub fn rst(&mut self) -> RST_W<'_>

Bit 3 - BUS Reset Interrupt Disable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Disable

pub fn dnrsm(&mut self) -> DNRSM_W<'_>

Bit 5 - DownStream to Device Interrupt Disable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume from Device Interrupt Disable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Disable

pub fn dconn(&mut self) -> DCONN_W<'_>

Bit 8 - Device Connection Interrupt Disable

pub fn ddisc(&mut self) -> DDISC_W<'_>

Bit 9 - Device Disconnection Interrupt Disable

impl W<u16, Reg<u16, _INTENSET>>

pub fn hsof(&mut self) -> HSOF_W<'_>

Bit 2 - Host Start Of Frame Interrupt Enable

pub fn rst(&mut self) -> RST_W<'_>

Bit 3 - Bus Reset Interrupt Enable

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up Interrupt Enable

pub fn dnrsm(&mut self) -> DNRSM_W<'_>

Bit 5 - DownStream to the Device Interrupt Enable

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume fromthe device Interrupt Enable

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access Interrupt Enable

pub fn dconn(&mut self) -> DCONN_W<'_>

Bit 8 - Link Power Management Interrupt Enable

pub fn ddisc(&mut self) -> DDISC_W<'_>

Bit 9 - Device Disconnection Interrupt Enable

impl W<u16, Reg<u16, _INTFLAG>>

pub fn hsof(&mut self) -> HSOF_W<'_>

Bit 2 - Host Start Of Frame

pub fn rst(&mut self) -> RST_W<'_>

Bit 3 - Bus Reset

pub fn wakeup(&mut self) -> WAKEUP_W<'_>

Bit 4 - Wake Up

pub fn dnrsm(&mut self) -> DNRSM_W<'_>

Bit 5 - Downstream

pub fn uprsm(&mut self) -> UPRSM_W<'_>

Bit 6 - Upstream Resume from the Device

pub fn ramacer(&mut self) -> RAMACER_W<'_>

Bit 7 - Ram Access

pub fn dconn(&mut self) -> DCONN_W<'_>

Bit 8 - Device Connection

pub fn ddisc(&mut self) -> DDISC_W<'_>

Bit 9 - Device Disconnection

impl W<u32, Reg<u32, _DESCADD>>

pub fn descadd(&mut self) -> DESCADD_W<'_>

Bits 0:31 - Descriptor Address Value

impl W<u16, Reg<u16, _PADCAL>>

pub fn transp(&mut self) -> TRANSP_W<'_>

Bits 0:4 - USB Pad Transp calibration

pub fn transn(&mut self) -> TRANSN_W<'_>

Bits 6:10 - USB Pad Transn calibration

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 12:14 - USB Pad Trim calibration

impl W<u8, Reg<u8, _PCFG>>

pub fn ptoken(&mut self) -> PTOKEN_W<'_>

Bits 0:1 - Pipe Token

pub fn bk(&mut self) -> BK_W<'_>

Bit 2 - Pipe Bank

pub fn ptype(&mut self) -> PTYPE_W<'_>

Bits 3:5 - Pipe Type

impl W<u8, Reg<u8, _BINTERVAL>>

pub fn bitinterval(&mut self) -> BITINTERVAL_W<'_>

Bits 0:7 - Bit Interval

impl W<u8, Reg<u8, _PSTATUSCLR>>

pub fn dtgl(&mut self) -> DTGL_W<'_>

Bit 0 - Data Toggle clear

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Curren Bank clear

pub fn pfreeze(&mut self) -> PFREEZE_W<'_>

Bit 4 - Pipe Freeze Clear

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Clear

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Clear

impl W<u8, Reg<u8, _PSTATUSSET>>

pub fn dtgl(&mut self) -> DTGL_W<'_>

Bit 0 - Data Toggle Set

pub fn curbk(&mut self) -> CURBK_W<'_>

Bit 2 - Current Bank Set

pub fn pfreeze(&mut self) -> PFREEZE_W<'_>

Bit 4 - Pipe Freeze Set

pub fn bk0rdy(&mut self) -> BK0RDY_W<'_>

Bit 6 - Bank 0 Ready Set

pub fn bk1rdy(&mut self) -> BK1RDY_W<'_>

Bit 7 - Bank 1 Ready Set

impl W<u8, Reg<u8, _PINTFLAG>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Flag

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Flag

pub fn trfail(&mut self) -> TRFAIL_W<'_>

Bit 2 - Error Flow Interrupt Flag

pub fn perr(&mut self) -> PERR_W<'_>

Bit 3 - Pipe Error Interrupt Flag

pub fn txstp(&mut self) -> TXSTP_W<'_>

Bit 4 - Transmit Setup Interrupt Flag

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Stall Interrupt Flag

impl W<u8, Reg<u8, _PINTENCLR>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Disable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Disable

pub fn trfail(&mut self) -> TRFAIL_W<'_>

Bit 2 - Error Flow Interrupt Disable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 3 - Pipe Error Interrupt Disable

pub fn txstp(&mut self) -> TXSTP_W<'_>

Bit 4 - Transmit Setup Interrupt Disable

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Stall Inetrrupt Disable

impl W<u8, Reg<u8, _PINTENSET>>

pub fn trcpt0(&mut self) -> TRCPT0_W<'_>

Bit 0 - Transfer Complete 0 Interrupt Enable

pub fn trcpt1(&mut self) -> TRCPT1_W<'_>

Bit 1 - Transfer Complete 1 Interrupt Enable

pub fn trfail(&mut self) -> TRFAIL_W<'_>

Bit 2 - Error Flow Interrupt Enable

pub fn perr(&mut self) -> PERR_W<'_>

Bit 3 - Pipe Error Interrupt Enable

pub fn txstp(&mut self) -> TXSTP_W<'_>

Bit 4 - Transmit Setup Interrupt Enable

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Stall Interrupt Enable

impl W<u8, Reg<u8, _CTRLA>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 1 - Enable

pub fn wen(&mut self) -> WEN_W<'_>

Bit 2 - Watchdog Timer Window Mode Enable

pub fn alwayson(&mut self) -> ALWAYSON_W<'_>

Bit 7 - Always-On

impl W<u8, Reg<u8, _CONFIG>>

pub fn per(&mut self) -> PER_W<'_>

Bits 0:3 - Time-Out Period

pub fn window(&mut self) -> WINDOW_W<'_>

Bits 4:7 - Window Mode Time-Out Period

impl W<u8, Reg<u8, _EWCTRL>>

pub fn ewoffset(&mut self) -> EWOFFSET_W<'_>

Bits 0:3 - Early Warning Interrupt Time Offset

impl W<u8, Reg<u8, _INTENCLR>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning Interrupt Enable

impl W<u8, Reg<u8, _INTENSET>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning Interrupt Enable

impl W<u8, Reg<u8, _INTFLAG>>

pub fn ew(&mut self) -> EW_W<'_>

Bit 0 - Early Warning

impl W<u8, Reg<u8, _CLEAR>>

pub fn clear(&mut self) -> CLEAR_W<'_>

Bits 0:7 - Watchdog Clear

impl W<u32, Reg<u32, _DHCSR>>

pub fn c_debugen(&mut self) -> C_DEBUGEN_W<'_>

Bit 0

pub fn c_halt(&mut self) -> C_HALT_W<'_>

Bit 1

pub fn c_step(&mut self) -> C_STEP_W<'_>

Bit 2

pub fn c_maskints(&mut self) -> C_MASKINTS_W<'_>

Bit 3

pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W<'_>

Bit 5

pub fn dbgkey(&mut self) -> DBGKEY_W<'_>

Bits 16:31

impl W<u32, Reg<u32, _DCRSR>>

pub fn regsel(&mut self) -> REGSEL_W<'_>

Bits 0:4

pub fn regwn_r(&mut self) -> REGWNR_W<'_>

Bit 16

impl W<u32, Reg<u32, _DEMCR>>

pub fn vc_corereset(&mut self) -> VC_CORERESET_W<'_>

Bit 0

pub fn vc_mmerr(&mut self) -> VC_MMERR_W<'_>

Bit 4

pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W<'_>

Bit 5

pub fn vc_chkerr(&mut self) -> VC_CHKERR_W<'_>

Bit 6

pub fn vc_staterr(&mut self) -> VC_STATERR_W<'_>

Bit 7

pub fn vc_buserr(&mut self) -> VC_BUSERR_W<'_>

Bit 8

pub fn vc_interr(&mut self) -> VC_INTERR_W<'_>

Bit 9

pub fn vc_harderr(&mut self) -> VC_HARDERR_W<'_>

Bit 10

pub fn mon_en(&mut self) -> MON_EN_W<'_>

Bit 16

pub fn mon_pend(&mut self) -> MON_PEND_W<'_>

Bit 17

pub fn mon_step(&mut self) -> MON_STEP_W<'_>

Bit 18

pub fn mon_req(&mut self) -> MON_REQ_W<'_>

Bit 19

pub fn trcena(&mut self) -> TRCENA_W<'_>

Bit 24

impl W<u32, Reg<u32, _CR>>

pub fn etmpd(&mut self) -> ETMPD_W<'_>

Bit 0 - ETM Power Down

pub fn portsize(&mut self) -> PORTSIZE_W<'_>

Bits 4:6 - Port Size bits 2:0

pub fn stall(&mut self) -> STALL_W<'_>

Bit 7 - Stall Processor

pub fn brout(&mut self) -> BROUT_W<'_>

Bit 8 - Branch Output

pub fn dbgrq(&mut self) -> DBGRQ_W<'_>

Bit 9 - Debug Request Control

pub fn prog(&mut self) -> PROG_W<'_>

Bit 10 - ETM Programming

pub fn portsel(&mut self) -> PORTSEL_W<'_>

Bit 11 - ETM Port Select

pub fn portmode2(&mut self) -> PORTMODE2_W<'_>

Bit 13 - Port Mode bit 2

pub fn portmode(&mut self) -> PORTMODE_W<'_>

Bits 16:17 - Port Mode bits 1:0

pub fn portsize3(&mut self) -> PORTSIZE3_W<'_>

Bit 21 - Port Size bit 3

pub fn tsen(&mut self) -> TSEN_W<'_>

Bit 28 - TimeStamp Enable

impl W<u32, Reg<u32, _ITCTRL>>

pub fn integration(&mut self) -> INTEGRATION_W<'_>

Bit 0

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - SysTick Counter Enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick Exception Request Enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock Source 0=external, 1=processor

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - Timer counted to 0 since last read of register

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current value at the time the register is accessed

impl W<u32, Reg<u32, _ACTLR>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - Disable interruption of LDM/STM instructions

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - Disable wruite buffer use during default memory map accesses

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - Disable IT folding

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - Disable automatic update of CONTROL.FPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - Disable out-of-order FP instructions

impl W<u32, Reg<u32, _ICSR>>

pub fn vectactive(&mut self) -> VECTACTIVE_W<'_>

Bits 0:8 - Active exception number

pub fn rettobase(&mut self) -> RETTOBASE_W<'_>

Bit 11 - No preempted active exceptions to execute

pub fn vectpending(&mut self) -> VECTPENDING_W<'_>

Bits 12:17 - Exception number of the highest priority pending enabled exception

pub fn isrpending(&mut self) -> ISRPENDING_W<'_>

Bit 22 - Interrupt pending flag

pub fn isrpreempt(&mut self) -> ISRPREEMPT_W<'_>

Bit 23 - Debug only

pub fn pendstclr(&mut self) -> PENDSTCLR_W<'_>

Bit 25 - SysTick clear-pending bit

pub fn pendstset(&mut self) -> PENDSTSET_W<'_>

Bit 26 - SysTick set-pending bit

pub fn pendsvclr(&mut self) -> PENDSVCLR_W<'_>

Bit 27 - PendSV clear-pending bit

pub fn pendsvset(&mut self) -> PENDSVSET_W<'_>

Bit 28 - PendSV set-pending bit

pub fn nmipendset(&mut self) -> NMIPENDSET_W<'_>

Bit 31 - NMI set-pending bit

impl W<u32, Reg<u32, _VTOR>>

pub fn tbloff(&mut self) -> TBLOFF_W<'_>

Bits 7:31 - Vector table base offset

impl W<u32, Reg<u32, _AIRCR>>

pub fn vectreset(&mut self) -> VECTRESET_W<'_>

Bit 0 - Must write 0

pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<'_>

Bit 1 - Must write 0

pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<'_>

Bit 2 - System Reset Request

pub fn prigroup(&mut self) -> PRIGROUP_W<'_>

Bits 8:10 - Interrupt priority grouping

pub fn endianness(&mut self) -> ENDIANNESS_W<'_>

Bit 15 - Data endianness, 0=little, 1=big

pub fn vectkey(&mut self) -> VECTKEY_W<'_>

Bits 16:31 - Register key

impl W<u32, Reg<u32, _SCR>>

pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<'_>

Bit 1 - Sleep-on-exit on handler return

pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<'_>

Bit 2 - Deep Sleep used as low power mode

pub fn sevonpend(&mut self) -> SEVONPEND_W<'_>

Bit 4 - Send Event on Pending bit

impl W<u32, Reg<u32, _CCR>>

pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W<'_>

Bit 0 - Indicates how processor enters Thread mode

pub fn usersetmpend(&mut self) -> USERSETMPEND_W<'_>

Bit 1 - Enables unprivileged software access to STIR register

pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W<'_>

Bit 3 - Enables unaligned access traps

pub fn div_0_trp(&mut self) -> DIV_0_TRP_W<'_>

Bit 4 - Enables divide by 0 trap

pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W<'_>

Bit 8 - Ignore LDM/STM BusFault for -1/-2 priority handlers

pub fn stkalign(&mut self) -> STKALIGN_W<'_>

Bit 9 - Indicates stack alignment on exception entry

impl W<u32, Reg<u32, _SHPR1>>

pub fn pri_4(&mut self) -> PRI_4_W<'_>

Bits 0:7 - Priority of system handler 4, MemManage

pub fn pri_5(&mut self) -> PRI_5_W<'_>

Bits 8:15 - Priority of system handler 5, BusFault

pub fn pri_6(&mut self) -> PRI_6_W<'_>

Bits 16:23 - Priority of system handler 6, UsageFault

impl W<u32, Reg<u32, _SHPR2>>

pub fn pri_11(&mut self) -> PRI_11_W<'_>

Bits 24:31 - Priority of system handler 11, SVCall

impl W<u32, Reg<u32, _SHPR3>>

pub fn pri_14(&mut self) -> PRI_14_W<'_>

Bits 16:23 - Priority of system handler 14, PendSV

pub fn pri_15(&mut self) -> PRI_15_W<'_>

Bits 24:31 - Priority of system handler 15, SysTick exception

impl W<u32, Reg<u32, _SHCSR>>

pub fn memfaultact(&mut self) -> MEMFAULTACT_W<'_>

Bit 0 - MemManage exception active bit

pub fn busfaultact(&mut self) -> BUSFAULTACT_W<'_>

Bit 1 - BusFault exception active bit

pub fn usgfaultact(&mut self) -> USGFAULTACT_W<'_>

Bit 3 - UsageFault exception active bit

pub fn svcallact(&mut self) -> SVCALLACT_W<'_>

Bit 7 - SVCall active bit

pub fn monitoract(&mut self) -> MONITORACT_W<'_>

Bit 8 - DebugMonitor exception active bit

pub fn pendsvact(&mut self) -> PENDSVACT_W<'_>

Bit 10 - PendSV exception active bit

pub fn systickact(&mut self) -> SYSTICKACT_W<'_>

Bit 11 - SysTick exception active bit

pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W<'_>

Bit 12 - UsageFault exception pending bit

pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W<'_>

Bit 13 - MemManage exception pending bit

pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W<'_>

Bit 14 - BusFault exception pending bit

pub fn svcallpended(&mut self) -> SVCALLPENDED_W<'_>

Bit 15 - SVCall pending bit

pub fn memfaultena(&mut self) -> MEMFAULTENA_W<'_>

Bit 16 - MemManage enable bit

pub fn busfaultena(&mut self) -> BUSFAULTENA_W<'_>

Bit 17 - BusFault enable bit

pub fn usgfaultena(&mut self) -> USGFAULTENA_W<'_>

Bit 18 - UsageFault enable bit

impl W<u32, Reg<u32, _CFSR>>

pub fn iaccviol(&mut self) -> IACCVIOL_W<'_>

Bit 0 - Instruction access violation

pub fn daccviol(&mut self) -> DACCVIOL_W<'_>

Bit 1 - Data access violation

pub fn munstkerr(&mut self) -> MUNSTKERR_W<'_>

Bit 3 - MemManage Fault on unstacking for exception return

pub fn mstkerr(&mut self) -> MSTKERR_W<'_>

Bit 4 - MemManage Fault on stacking for exception entry

pub fn mlsperr(&mut self) -> MLSPERR_W<'_>

Bit 5 - MemManager Fault occured during FP lazy state preservation

pub fn mmarvalid(&mut self) -> MMARVALID_W<'_>

Bit 7 - MemManage Fault Address Register valid

pub fn ibuserr(&mut self) -> IBUSERR_W<'_>

Bit 8 - Instruction bus error

pub fn preciserr(&mut self) -> PRECISERR_W<'_>

Bit 9 - Precise data bus error

pub fn impreciserr(&mut self) -> IMPRECISERR_W<'_>

Bit 10 - Imprecise data bus error

pub fn unstkerr(&mut self) -> UNSTKERR_W<'_>

Bit 11 - BusFault on unstacking for exception return

pub fn stkerr(&mut self) -> STKERR_W<'_>

Bit 12 - BusFault on stacking for exception entry

pub fn lsperr(&mut self) -> LSPERR_W<'_>

Bit 13 - BusFault occured during FP lazy state preservation

pub fn bfarvalid(&mut self) -> BFARVALID_W<'_>

Bit 15 - BusFault Address Register valid

pub fn undefinstr(&mut self) -> UNDEFINSTR_W<'_>

Bit 16 - Undefined instruction UsageFault

pub fn invstate(&mut self) -> INVSTATE_W<'_>

Bit 17 - Invalid state UsageFault

pub fn invpc(&mut self) -> INVPC_W<'_>

Bit 18 - Invalid PC load UsageFault

pub fn nocp(&mut self) -> NOCP_W<'_>

Bit 19 - No coprocessor UsageFault

pub fn unaligned(&mut self) -> UNALIGNED_W<'_>

Bit 24 - Unaligned access UsageFault

pub fn divbyzero(&mut self) -> DIVBYZERO_W<'_>

Bit 25 - Divide by zero UsageFault

impl W<u32, Reg<u32, _HFSR>>

pub fn vecttbl(&mut self) -> VECTTBL_W<'_>

Bit 1 - BusFault on a Vector Table read during exception processing

pub fn forced(&mut self) -> FORCED_W<'_>

Bit 30 - Forced Hard Fault

pub fn debugevt(&mut self) -> DEBUGEVT_W<'_>

Bit 31 - Debug: always write 0

impl W<u32, Reg<u32, _DFSR>>

pub fn halted(&mut self) -> HALTED_W<'_>

Bit 0

pub fn bkpt(&mut self) -> BKPT_W<'_>

Bit 1

pub fn dwttrap(&mut self) -> DWTTRAP_W<'_>

Bit 2

pub fn vcatch(&mut self) -> VCATCH_W<'_>

Bit 3

pub fn external(&mut self) -> EXTERNAL_W<'_>

Bit 4

impl W<u32, Reg<u32, _MMFAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address that generated the MemManage fault

impl W<u32, Reg<u32, _BFAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address that generated the BusFault

impl W<u32, Reg<u32, _AFSR>>

pub fn impdef(&mut self) -> IMPDEF_W<'_>

Bits 0:31 - AUXFAULT input signals

impl W<u32, Reg<u32, _CPACR>>

pub fn cp10(&mut self) -> CP10_W<'_>

Bits 20:21 - Access privileges for coprocessor 10

pub fn cp11(&mut self) -> CP11_W<'_>

Bits 22:23 - Access privileges for coprocessor 11