pub type W = W<CTRLA_SPEC>;
Expand description
Register CTRLA
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn autows(&mut self) -> AUTOWS_W<'_, CTRLA_SPEC, 2>
pub fn autows(&mut self) -> AUTOWS_W<'_, CTRLA_SPEC, 2>
Bit 2 - Auto Wait State Enable
sourcepub fn suspen(&mut self) -> SUSPEN_W<'_, CTRLA_SPEC, 3>
pub fn suspen(&mut self) -> SUSPEN_W<'_, CTRLA_SPEC, 3>
Bit 3 - Suspend Enable
sourcepub fn wmode(&mut self) -> WMODE_W<'_, CTRLA_SPEC, 4>
pub fn wmode(&mut self) -> WMODE_W<'_, CTRLA_SPEC, 4>
Bits 4:5 - Write Mode
sourcepub fn prm(&mut self) -> PRM_W<'_, CTRLA_SPEC, 6>
pub fn prm(&mut self) -> PRM_W<'_, CTRLA_SPEC, 6>
Bits 6:7 - Power Reduction Mode during Sleep
sourcepub fn rws(&mut self) -> RWS_W<'_, CTRLA_SPEC, 8>
pub fn rws(&mut self) -> RWS_W<'_, CTRLA_SPEC, 8>
Bits 8:11 - NVM Read Wait States
sourcepub fn ahbns0(&mut self) -> AHBNS0_W<'_, CTRLA_SPEC, 12>
pub fn ahbns0(&mut self) -> AHBNS0_W<'_, CTRLA_SPEC, 12>
Bit 12 - Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated
sourcepub fn ahbns1(&mut self) -> AHBNS1_W<'_, CTRLA_SPEC, 13>
pub fn ahbns1(&mut self) -> AHBNS1_W<'_, CTRLA_SPEC, 13>
Bit 13 - Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated
sourcepub fn cachedis0(&mut self) -> CACHEDIS0_W<'_, CTRLA_SPEC, 14>
pub fn cachedis0(&mut self) -> CACHEDIS0_W<'_, CTRLA_SPEC, 14>
Bit 14 - AHB0 Cache Disable
sourcepub fn cachedis1(&mut self) -> CACHEDIS1_W<'_, CTRLA_SPEC, 15>
pub fn cachedis1(&mut self) -> CACHEDIS1_W<'_, CTRLA_SPEC, 15>
Bit 15 - AHB1 Cache Disable