#[repr(u8)]pub enum TRIGSRCSELECT_A {
Show 85 variants
DISABLE = 0,
RTC_TIMESTAMP = 1,
DSU_DCC0 = 2,
DSU_DCC1 = 3,
SERCOM0_RX = 4,
SERCOM0_TX = 5,
SERCOM1_RX = 6,
SERCOM1_TX = 7,
SERCOM2_RX = 8,
SERCOM2_TX = 9,
SERCOM3_RX = 10,
SERCOM3_TX = 11,
SERCOM4_RX = 12,
SERCOM4_TX = 13,
SERCOM5_RX = 14,
SERCOM5_TX = 15,
SERCOM6_RX = 16,
SERCOM6_TX = 17,
SERCOM7_RX = 18,
SERCOM7_TX = 19,
CAN0_DEBUG = 20,
CAN1_DEBUG = 21,
TCC0_OVF = 22,
TCC0_MC_0 = 23,
TCC0_MC_1 = 24,
TCC0_MC_2 = 25,
TCC0_MC_3 = 26,
TCC0_MC_4 = 27,
TCC0_MC_5 = 28,
TCC1_OVF = 29,
TCC1_MC_0 = 30,
TCC1_MC_1 = 31,
TCC1_MC_2 = 32,
TCC1_MC_3 = 33,
TCC2_OVF = 34,
TCC2_MC_0 = 35,
TCC2_MC_1 = 36,
TCC2_MC_2 = 37,
TCC3_OVF = 38,
TCC3_MC_0 = 39,
TCC3_MC_1 = 40,
TCC4_OVF = 41,
TCC4_MC_0 = 42,
TCC4_MC_1 = 43,
TC0_OVF = 44,
TC0_MC_0 = 45,
TC0_MC_1 = 46,
TC1_OVF = 47,
TC1_MC_0 = 48,
TC1_MC_1 = 49,
TC2_OVF = 50,
TC2_MC_0 = 51,
TC2_MC_1 = 52,
TC3_OVF = 53,
TC3_MC_0 = 54,
TC3_MC_1 = 55,
TC4_OVF = 56,
TC4_MC_0 = 57,
TC4_MC_1 = 58,
TC5_OVF = 59,
TC5_MC_0 = 60,
TC5_MC_1 = 61,
TC6_OVF = 62,
TC6_MC_0 = 63,
TC6_MC_1 = 64,
TC7_OVF = 65,
TC7_MC_0 = 66,
TC7_MC_1 = 67,
ADC0_RESRDY = 68,
ADC0_SEQ = 69,
ADC1_RESRDY = 70,
ADC1_SEQ = 71,
DAC_EMPTY_0 = 72,
DAC_EMPTY_1 = 73,
DAC_RESRDY_0 = 74,
DAC_RESRDY_1 = 75,
I2S_RX_0 = 76,
I2S_RX_1 = 77,
I2S_TX_0 = 78,
I2S_TX_1 = 79,
PCC_RX = 80,
AES_WR = 81,
AES_RD = 82,
QSPI_RX = 83,
QSPI_TX = 84,
}
Expand description
Trigger Source
Value on reset: 0
Variants§
DISABLE = 0
0: Only software/event triggers
RTC_TIMESTAMP = 1
1: DMA RTC timestamp trigger
DSU_DCC0 = 2
2: DMAC ID for DCC0 register
DSU_DCC1 = 3
3: DMAC ID for DCC1 register
SERCOM0_RX = 4
4: Index of DMA RX trigger
SERCOM0_TX = 5
5: Index of DMA TX trigger
SERCOM1_RX = 6
6: Index of DMA RX trigger
SERCOM1_TX = 7
7: Index of DMA TX trigger
SERCOM2_RX = 8
8: Index of DMA RX trigger
SERCOM2_TX = 9
9: Index of DMA TX trigger
SERCOM3_RX = 10
10: Index of DMA RX trigger
SERCOM3_TX = 11
11: Index of DMA TX trigger
SERCOM4_RX = 12
12: Index of DMA RX trigger
SERCOM4_TX = 13
13: Index of DMA TX trigger
SERCOM5_RX = 14
14: Index of DMA RX trigger
SERCOM5_TX = 15
15: Index of DMA TX trigger
SERCOM6_RX = 16
16: Index of DMA RX trigger
SERCOM6_TX = 17
17: Index of DMA TX trigger
SERCOM7_RX = 18
18: Index of DMA RX trigger
SERCOM7_TX = 19
19: Index of DMA TX trigger
CAN0_DEBUG = 20
20: DMA CAN Debug Req
CAN1_DEBUG = 21
21: DMA CAN Debug Req
TCC0_OVF = 22
22: DMA overflow/underflow/retrigger trigger
TCC0_MC_0 = 23
23: Indexes of DMA Match/Compare triggers
TCC0_MC_1 = 24
24: Indexes of DMA Match/Compare triggers
TCC0_MC_2 = 25
25: Indexes of DMA Match/Compare triggers
TCC0_MC_3 = 26
26: Indexes of DMA Match/Compare triggers
TCC0_MC_4 = 27
27: Indexes of DMA Match/Compare triggers
TCC0_MC_5 = 28
28: Indexes of DMA Match/Compare triggers
TCC1_OVF = 29
29: DMA overflow/underflow/retrigger trigger
TCC1_MC_0 = 30
30: Indexes of DMA Match/Compare triggers
TCC1_MC_1 = 31
31: Indexes of DMA Match/Compare triggers
TCC1_MC_2 = 32
32: Indexes of DMA Match/Compare triggers
TCC1_MC_3 = 33
33: Indexes of DMA Match/Compare triggers
TCC2_OVF = 34
34: DMA overflow/underflow/retrigger trigger
TCC2_MC_0 = 35
35: Indexes of DMA Match/Compare triggers
TCC2_MC_1 = 36
36: Indexes of DMA Match/Compare triggers
TCC2_MC_2 = 37
37: Indexes of DMA Match/Compare triggers
TCC3_OVF = 38
38: DMA overflow/underflow/retrigger trigger
TCC3_MC_0 = 39
39: Indexes of DMA Match/Compare triggers
TCC3_MC_1 = 40
40: Indexes of DMA Match/Compare triggers
TCC4_OVF = 41
41: DMA overflow/underflow/retrigger trigger
TCC4_MC_0 = 42
42: Indexes of DMA Match/Compare triggers
TCC4_MC_1 = 43
43: Indexes of DMA Match/Compare triggers
TC0_OVF = 44
44: Indexes of DMA Overflow trigger
TC0_MC_0 = 45
45: Indexes of DMA Match/Compare triggers
TC0_MC_1 = 46
46: Indexes of DMA Match/Compare triggers
TC1_OVF = 47
47: Indexes of DMA Overflow trigger
TC1_MC_0 = 48
48: Indexes of DMA Match/Compare triggers
TC1_MC_1 = 49
49: Indexes of DMA Match/Compare triggers
TC2_OVF = 50
50: Indexes of DMA Overflow trigger
TC2_MC_0 = 51
51: Indexes of DMA Match/Compare triggers
TC2_MC_1 = 52
52: Indexes of DMA Match/Compare triggers
TC3_OVF = 53
53: Indexes of DMA Overflow trigger
TC3_MC_0 = 54
54: Indexes of DMA Match/Compare triggers
TC3_MC_1 = 55
55: Indexes of DMA Match/Compare triggers
TC4_OVF = 56
56: Indexes of DMA Overflow trigger
TC4_MC_0 = 57
57: Indexes of DMA Match/Compare triggers
TC4_MC_1 = 58
58: Indexes of DMA Match/Compare triggers
TC5_OVF = 59
59: Indexes of DMA Overflow trigger
TC5_MC_0 = 60
60: Indexes of DMA Match/Compare triggers
TC5_MC_1 = 61
61: Indexes of DMA Match/Compare triggers
TC6_OVF = 62
62: Indexes of DMA Overflow trigger
TC6_MC_0 = 63
63: Indexes of DMA Match/Compare triggers
TC6_MC_1 = 64
64: Indexes of DMA Match/Compare triggers
TC7_OVF = 65
65: Indexes of DMA Overflow trigger
TC7_MC_0 = 66
66: Indexes of DMA Match/Compare triggers
TC7_MC_1 = 67
67: Indexes of DMA Match/Compare triggers
ADC0_RESRDY = 68
68: index of DMA RESRDY trigger
ADC0_SEQ = 69
69: Index of DMA SEQ trigger
ADC1_RESRDY = 70
70: Index of DMA RESRDY trigger
ADC1_SEQ = 71
71: Index of DMA SEQ trigger
DAC_EMPTY_0 = 72
72: DMA DAC Empty Req
DAC_EMPTY_1 = 73
73: DMA DAC Empty Req
DAC_RESRDY_0 = 74
74: DMA DAC Result Ready Req
DAC_RESRDY_1 = 75
75: DMA DAC Result Ready Req
I2S_RX_0 = 76
76: Indexes of DMA RX triggers
I2S_RX_1 = 77
77: Indexes of DMA RX triggers
I2S_TX_0 = 78
78: Indexes of DMA TX triggers
I2S_TX_1 = 79
79: Indexes of DMA TX triggers
PCC_RX = 80
80: Indexes of PCC RX trigger
AES_WR = 81
81: DMA DATA Write trigger
AES_RD = 82
82: DMA DATA Read trigger
QSPI_RX = 83
83: Indexes of QSPI RX trigger
QSPI_TX = 84
84: Indexes of QSPI TX trigger
Trait Implementations§
source§impl Clone for TRIGSRCSELECT_A
impl Clone for TRIGSRCSELECT_A
source§fn clone(&self) -> TRIGSRCSELECT_A
fn clone(&self) -> TRIGSRCSELECT_A
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Debug for TRIGSRCSELECT_A
impl Debug for TRIGSRCSELECT_A
source§impl From<TRIGSRCSELECT_A> for u8
impl From<TRIGSRCSELECT_A> for u8
source§fn from(variant: TRIGSRCSELECT_A) -> Self
fn from(variant: TRIGSRCSELECT_A) -> Self
source§impl PartialEq for TRIGSRCSELECT_A
impl PartialEq for TRIGSRCSELECT_A
source§fn eq(&self, other: &TRIGSRCSELECT_A) -> bool
fn eq(&self, other: &TRIGSRCSELECT_A) -> bool
self
and other
values to be equal, and is used
by ==
.