[−][src]Struct atsamd51j19a::dmac::RegisterBlock
Register block
Fields
ctrl: CTRL
0x00 - Control
crcctrl: CRCCTRL
0x02 - CRC Control
crcdatain: CRCDATAIN
0x04 - CRC Data Input
crcchksum: CRCCHKSUM
0x08 - CRC Checksum
crcstatus: CRCSTATUS
0x0c - CRC Status
dbgctrl: DBGCTRL
0x0d - Debug Control
swtrigctrl: SWTRIGCTRL
0x10 - Software Trigger Control
prictrl0: PRICTRL0
0x14 - Priority Control 0
intpend: INTPEND
0x20 - Interrupt Pending
intstatus: INTSTATUS
0x24 - Interrupt Status
busych: BUSYCH
0x28 - Busy Channels
pendch: PENDCH
0x2c - Pending Channels
active: ACTIVE
0x30 - Active Channel and Levels
baseaddr: BASEADDR
0x34 - Descriptor Memory Section Base Address
wrbaddr: WRBADDR
0x38 - Write-Back Memory Section Base Address
chctrla0: CHCTRLA
0x40 - Channel n Control A
chctrlb0: CHCTRLB
0x44 - Channel n Control B
chprilvl0: CHPRILVL
0x45 - Channel n Priority Level
chevctrl0: CHEVCTRL
0x46 - Channel n Event Control
chintenclr0: CHINTENCLR
0x4c - Channel n Interrupt Enable Clear
chintenset0: CHINTENSET
0x4d - Channel n Interrupt Enable Set
chintflag0: CHINTFLAG
0x4e - Channel n Interrupt Flag Status and Clear
chstatus0: CHSTATUS
0x4f - Channel n Status
chctrla1: CHCTRLA
0x50 - Channel n Control A
chctrlb1: CHCTRLB
0x54 - Channel n Control B
chprilvl1: CHPRILVL
0x55 - Channel n Priority Level
chevctrl1: CHEVCTRL
0x56 - Channel n Event Control
chintenclr1: CHINTENCLR
0x5c - Channel n Interrupt Enable Clear
chintenset1: CHINTENSET
0x5d - Channel n Interrupt Enable Set
chintflag1: CHINTFLAG
0x5e - Channel n Interrupt Flag Status and Clear
chstatus1: CHSTATUS
0x5f - Channel n Status
chctrla2: CHCTRLA
0x60 - Channel n Control A
chctrlb2: CHCTRLB
0x64 - Channel n Control B
chprilvl2: CHPRILVL
0x65 - Channel n Priority Level
chevctrl2: CHEVCTRL
0x66 - Channel n Event Control
chintenclr2: CHINTENCLR
0x6c - Channel n Interrupt Enable Clear
chintenset2: CHINTENSET
0x6d - Channel n Interrupt Enable Set
chintflag2: CHINTFLAG
0x6e - Channel n Interrupt Flag Status and Clear
chstatus2: CHSTATUS
0x6f - Channel n Status
chctrla3: CHCTRLA
0x70 - Channel n Control A
chctrlb3: CHCTRLB
0x74 - Channel n Control B
chprilvl3: CHPRILVL
0x75 - Channel n Priority Level
chevctrl3: CHEVCTRL
0x76 - Channel n Event Control
chintenclr3: CHINTENCLR
0x7c - Channel n Interrupt Enable Clear
chintenset3: CHINTENSET
0x7d - Channel n Interrupt Enable Set
chintflag3: CHINTFLAG
0x7e - Channel n Interrupt Flag Status and Clear
chstatus3: CHSTATUS
0x7f - Channel n Status
chctrla4: CHCTRLA
0x80 - Channel n Control A
chctrlb4: CHCTRLB
0x84 - Channel n Control B
chprilvl4: CHPRILVL
0x85 - Channel n Priority Level
chevctrl4: CHEVCTRL
0x86 - Channel n Event Control
chintenclr4: CHINTENCLR
0x8c - Channel n Interrupt Enable Clear
chintenset4: CHINTENSET
0x8d - Channel n Interrupt Enable Set
chintflag4: CHINTFLAG
0x8e - Channel n Interrupt Flag Status and Clear
chstatus4: CHSTATUS
0x8f - Channel n Status
chctrla5: CHCTRLA
0x90 - Channel n Control A
chctrlb5: CHCTRLB
0x94 - Channel n Control B
chprilvl5: CHPRILVL
0x95 - Channel n Priority Level
chevctrl5: CHEVCTRL
0x96 - Channel n Event Control
chintenclr5: CHINTENCLR
0x9c - Channel n Interrupt Enable Clear
chintenset5: CHINTENSET
0x9d - Channel n Interrupt Enable Set
chintflag5: CHINTFLAG
0x9e - Channel n Interrupt Flag Status and Clear
chstatus5: CHSTATUS
0x9f - Channel n Status
chctrla6: CHCTRLA
0xa0 - Channel n Control A
chctrlb6: CHCTRLB
0xa4 - Channel n Control B
chprilvl6: CHPRILVL
0xa5 - Channel n Priority Level
chevctrl6: CHEVCTRL
0xa6 - Channel n Event Control
chintenclr6: CHINTENCLR
0xac - Channel n Interrupt Enable Clear
chintenset6: CHINTENSET
0xad - Channel n Interrupt Enable Set
chintflag6: CHINTFLAG
0xae - Channel n Interrupt Flag Status and Clear
chstatus6: CHSTATUS
0xaf - Channel n Status
chctrla7: CHCTRLA
0xb0 - Channel n Control A
chctrlb7: CHCTRLB
0xb4 - Channel n Control B
chprilvl7: CHPRILVL
0xb5 - Channel n Priority Level
chevctrl7: CHEVCTRL
0xb6 - Channel n Event Control
chintenclr7: CHINTENCLR
0xbc - Channel n Interrupt Enable Clear
chintenset7: CHINTENSET
0xbd - Channel n Interrupt Enable Set
chintflag7: CHINTFLAG
0xbe - Channel n Interrupt Flag Status and Clear
chstatus7: CHSTATUS
0xbf - Channel n Status
chctrla8: CHCTRLA
0xc0 - Channel n Control A
chctrlb8: CHCTRLB
0xc4 - Channel n Control B
chprilvl8: CHPRILVL
0xc5 - Channel n Priority Level
chevctrl8: CHEVCTRL
0xc6 - Channel n Event Control
chintenclr8: CHINTENCLR
0xcc - Channel n Interrupt Enable Clear
chintenset8: CHINTENSET
0xcd - Channel n Interrupt Enable Set
chintflag8: CHINTFLAG
0xce - Channel n Interrupt Flag Status and Clear
chstatus8: CHSTATUS
0xcf - Channel n Status
chctrla9: CHCTRLA
0xd0 - Channel n Control A
chctrlb9: CHCTRLB
0xd4 - Channel n Control B
chprilvl9: CHPRILVL
0xd5 - Channel n Priority Level
chevctrl9: CHEVCTRL
0xd6 - Channel n Event Control
chintenclr9: CHINTENCLR
0xdc - Channel n Interrupt Enable Clear
chintenset9: CHINTENSET
0xdd - Channel n Interrupt Enable Set
chintflag9: CHINTFLAG
0xde - Channel n Interrupt Flag Status and Clear
chstatus9: CHSTATUS
0xdf - Channel n Status
chctrla10: CHCTRLA
0xe0 - Channel n Control A
chctrlb10: CHCTRLB
0xe4 - Channel n Control B
chprilvl10: CHPRILVL
0xe5 - Channel n Priority Level
chevctrl10: CHEVCTRL
0xe6 - Channel n Event Control
chintenclr10: CHINTENCLR
0xec - Channel n Interrupt Enable Clear
chintenset10: CHINTENSET
0xed - Channel n Interrupt Enable Set
chintflag10: CHINTFLAG
0xee - Channel n Interrupt Flag Status and Clear
chstatus10: CHSTATUS
0xef - Channel n Status
chctrla11: CHCTRLA
0xf0 - Channel n Control A
chctrlb11: CHCTRLB
0xf4 - Channel n Control B
chprilvl11: CHPRILVL
0xf5 - Channel n Priority Level
chevctrl11: CHEVCTRL
0xf6 - Channel n Event Control
chintenclr11: CHINTENCLR
0xfc - Channel n Interrupt Enable Clear
chintenset11: CHINTENSET
0xfd - Channel n Interrupt Enable Set
chintflag11: CHINTFLAG
0xfe - Channel n Interrupt Flag Status and Clear
chstatus11: CHSTATUS
0xff - Channel n Status
chctrla12: CHCTRLA
0x100 - Channel n Control A
chctrlb12: CHCTRLB
0x104 - Channel n Control B
chprilvl12: CHPRILVL
0x105 - Channel n Priority Level
chevctrl12: CHEVCTRL
0x106 - Channel n Event Control
chintenclr12: CHINTENCLR
0x10c - Channel n Interrupt Enable Clear
chintenset12: CHINTENSET
0x10d - Channel n Interrupt Enable Set
chintflag12: CHINTFLAG
0x10e - Channel n Interrupt Flag Status and Clear
chstatus12: CHSTATUS
0x10f - Channel n Status
chctrla13: CHCTRLA
0x110 - Channel n Control A
chctrlb13: CHCTRLB
0x114 - Channel n Control B
chprilvl13: CHPRILVL
0x115 - Channel n Priority Level
chevctrl13: CHEVCTRL
0x116 - Channel n Event Control
chintenclr13: CHINTENCLR
0x11c - Channel n Interrupt Enable Clear
chintenset13: CHINTENSET
0x11d - Channel n Interrupt Enable Set
chintflag13: CHINTFLAG
0x11e - Channel n Interrupt Flag Status and Clear
chstatus13: CHSTATUS
0x11f - Channel n Status
chctrla14: CHCTRLA
0x120 - Channel n Control A
chctrlb14: CHCTRLB
0x124 - Channel n Control B
chprilvl14: CHPRILVL
0x125 - Channel n Priority Level
chevctrl14: CHEVCTRL
0x126 - Channel n Event Control
chintenclr14: CHINTENCLR
0x12c - Channel n Interrupt Enable Clear
chintenset14: CHINTENSET
0x12d - Channel n Interrupt Enable Set
chintflag14: CHINTFLAG
0x12e - Channel n Interrupt Flag Status and Clear
chstatus14: CHSTATUS
0x12f - Channel n Status
chctrla15: CHCTRLA
0x130 - Channel n Control A
chctrlb15: CHCTRLB
0x134 - Channel n Control B
chprilvl15: CHPRILVL
0x135 - Channel n Priority Level
chevctrl15: CHEVCTRL
0x136 - Channel n Event Control
chintenclr15: CHINTENCLR
0x13c - Channel n Interrupt Enable Clear
chintenset15: CHINTENSET
0x13d - Channel n Interrupt Enable Set
chintflag15: CHINTFLAG
0x13e - Channel n Interrupt Flag Status and Clear
chstatus15: CHSTATUS
0x13f - Channel n Status
chctrla16: CHCTRLA
0x140 - Channel n Control A
chctrlb16: CHCTRLB
0x144 - Channel n Control B
chprilvl16: CHPRILVL
0x145 - Channel n Priority Level
chevctrl16: CHEVCTRL
0x146 - Channel n Event Control
chintenclr16: CHINTENCLR
0x14c - Channel n Interrupt Enable Clear
chintenset16: CHINTENSET
0x14d - Channel n Interrupt Enable Set
chintflag16: CHINTFLAG
0x14e - Channel n Interrupt Flag Status and Clear
chstatus16: CHSTATUS
0x14f - Channel n Status
chctrla17: CHCTRLA
0x150 - Channel n Control A
chctrlb17: CHCTRLB
0x154 - Channel n Control B
chprilvl17: CHPRILVL
0x155 - Channel n Priority Level
chevctrl17: CHEVCTRL
0x156 - Channel n Event Control
chintenclr17: CHINTENCLR
0x15c - Channel n Interrupt Enable Clear
chintenset17: CHINTENSET
0x15d - Channel n Interrupt Enable Set
chintflag17: CHINTFLAG
0x15e - Channel n Interrupt Flag Status and Clear
chstatus17: CHSTATUS
0x15f - Channel n Status
chctrla18: CHCTRLA
0x160 - Channel n Control A
chctrlb18: CHCTRLB
0x164 - Channel n Control B
chprilvl18: CHPRILVL
0x165 - Channel n Priority Level
chevctrl18: CHEVCTRL
0x166 - Channel n Event Control
chintenclr18: CHINTENCLR
0x16c - Channel n Interrupt Enable Clear
chintenset18: CHINTENSET
0x16d - Channel n Interrupt Enable Set
chintflag18: CHINTFLAG
0x16e - Channel n Interrupt Flag Status and Clear
chstatus18: CHSTATUS
0x16f - Channel n Status
chctrla19: CHCTRLA
0x170 - Channel n Control A
chctrlb19: CHCTRLB
0x174 - Channel n Control B
chprilvl19: CHPRILVL
0x175 - Channel n Priority Level
chevctrl19: CHEVCTRL
0x176 - Channel n Event Control
chintenclr19: CHINTENCLR
0x17c - Channel n Interrupt Enable Clear
chintenset19: CHINTENSET
0x17d - Channel n Interrupt Enable Set
chintflag19: CHINTFLAG
0x17e - Channel n Interrupt Flag Status and Clear
chstatus19: CHSTATUS
0x17f - Channel n Status
chctrla20: CHCTRLA
0x180 - Channel n Control A
chctrlb20: CHCTRLB
0x184 - Channel n Control B
chprilvl20: CHPRILVL
0x185 - Channel n Priority Level
chevctrl20: CHEVCTRL
0x186 - Channel n Event Control
chintenclr20: CHINTENCLR
0x18c - Channel n Interrupt Enable Clear
chintenset20: CHINTENSET
0x18d - Channel n Interrupt Enable Set
chintflag20: CHINTFLAG
0x18e - Channel n Interrupt Flag Status and Clear
chstatus20: CHSTATUS
0x18f - Channel n Status
chctrla21: CHCTRLA
0x190 - Channel n Control A
chctrlb21: CHCTRLB
0x194 - Channel n Control B
chprilvl21: CHPRILVL
0x195 - Channel n Priority Level
chevctrl21: CHEVCTRL
0x196 - Channel n Event Control
chintenclr21: CHINTENCLR
0x19c - Channel n Interrupt Enable Clear
chintenset21: CHINTENSET
0x19d - Channel n Interrupt Enable Set
chintflag21: CHINTFLAG
0x19e - Channel n Interrupt Flag Status and Clear
chstatus21: CHSTATUS
0x19f - Channel n Status
chctrla22: CHCTRLA
0x1a0 - Channel n Control A
chctrlb22: CHCTRLB
0x1a4 - Channel n Control B
chprilvl22: CHPRILVL
0x1a5 - Channel n Priority Level
chevctrl22: CHEVCTRL
0x1a6 - Channel n Event Control
chintenclr22: CHINTENCLR
0x1ac - Channel n Interrupt Enable Clear
chintenset22: CHINTENSET
0x1ad - Channel n Interrupt Enable Set
chintflag22: CHINTFLAG
0x1ae - Channel n Interrupt Flag Status and Clear
chstatus22: CHSTATUS
0x1af - Channel n Status
chctrla23: CHCTRLA
0x1b0 - Channel n Control A
chctrlb23: CHCTRLB
0x1b4 - Channel n Control B
chprilvl23: CHPRILVL
0x1b5 - Channel n Priority Level
chevctrl23: CHEVCTRL
0x1b6 - Channel n Event Control
chintenclr23: CHINTENCLR
0x1bc - Channel n Interrupt Enable Clear
chintenset23: CHINTENSET
0x1bd - Channel n Interrupt Enable Set
chintflag23: CHINTFLAG
0x1be - Channel n Interrupt Flag Status and Clear
chstatus23: CHSTATUS
0x1bf - Channel n Status
chctrla24: CHCTRLA
0x1c0 - Channel n Control A
chctrlb24: CHCTRLB
0x1c4 - Channel n Control B
chprilvl24: CHPRILVL
0x1c5 - Channel n Priority Level
chevctrl24: CHEVCTRL
0x1c6 - Channel n Event Control
chintenclr24: CHINTENCLR
0x1cc - Channel n Interrupt Enable Clear
chintenset24: CHINTENSET
0x1cd - Channel n Interrupt Enable Set
chintflag24: CHINTFLAG
0x1ce - Channel n Interrupt Flag Status and Clear
chstatus24: CHSTATUS
0x1cf - Channel n Status
chctrla25: CHCTRLA
0x1d0 - Channel n Control A
chctrlb25: CHCTRLB
0x1d4 - Channel n Control B
chprilvl25: CHPRILVL
0x1d5 - Channel n Priority Level
chevctrl25: CHEVCTRL
0x1d6 - Channel n Event Control
chintenclr25: CHINTENCLR
0x1dc - Channel n Interrupt Enable Clear
chintenset25: CHINTENSET
0x1dd - Channel n Interrupt Enable Set
chintflag25: CHINTFLAG
0x1de - Channel n Interrupt Flag Status and Clear
chstatus25: CHSTATUS
0x1df - Channel n Status
chctrla26: CHCTRLA
0x1e0 - Channel n Control A
chctrlb26: CHCTRLB
0x1e4 - Channel n Control B
chprilvl26: CHPRILVL
0x1e5 - Channel n Priority Level
chevctrl26: CHEVCTRL
0x1e6 - Channel n Event Control
chintenclr26: CHINTENCLR
0x1ec - Channel n Interrupt Enable Clear
chintenset26: CHINTENSET
0x1ed - Channel n Interrupt Enable Set
chintflag26: CHINTFLAG
0x1ee - Channel n Interrupt Flag Status and Clear
chstatus26: CHSTATUS
0x1ef - Channel n Status
chctrla27: CHCTRLA
0x1f0 - Channel n Control A
chctrlb27: CHCTRLB
0x1f4 - Channel n Control B
chprilvl27: CHPRILVL
0x1f5 - Channel n Priority Level
chevctrl27: CHEVCTRL
0x1f6 - Channel n Event Control
chintenclr27: CHINTENCLR
0x1fc - Channel n Interrupt Enable Clear
chintenset27: CHINTENSET
0x1fd - Channel n Interrupt Enable Set
chintflag27: CHINTFLAG
0x1fe - Channel n Interrupt Flag Status and Clear
chstatus27: CHSTATUS
0x1ff - Channel n Status
chctrla28: CHCTRLA
0x200 - Channel n Control A
chctrlb28: CHCTRLB
0x204 - Channel n Control B
chprilvl28: CHPRILVL
0x205 - Channel n Priority Level
chevctrl28: CHEVCTRL
0x206 - Channel n Event Control
chintenclr28: CHINTENCLR
0x20c - Channel n Interrupt Enable Clear
chintenset28: CHINTENSET
0x20d - Channel n Interrupt Enable Set
chintflag28: CHINTFLAG
0x20e - Channel n Interrupt Flag Status and Clear
chstatus28: CHSTATUS
0x20f - Channel n Status
chctrla29: CHCTRLA
0x210 - Channel n Control A
chctrlb29: CHCTRLB
0x214 - Channel n Control B
chprilvl29: CHPRILVL
0x215 - Channel n Priority Level
chevctrl29: CHEVCTRL
0x216 - Channel n Event Control
chintenclr29: CHINTENCLR
0x21c - Channel n Interrupt Enable Clear
chintenset29: CHINTENSET
0x21d - Channel n Interrupt Enable Set
chintflag29: CHINTFLAG
0x21e - Channel n Interrupt Flag Status and Clear
chstatus29: CHSTATUS
0x21f - Channel n Status
chctrla30: CHCTRLA
0x220 - Channel n Control A
chctrlb30: CHCTRLB
0x224 - Channel n Control B
chprilvl30: CHPRILVL
0x225 - Channel n Priority Level
chevctrl30: CHEVCTRL
0x226 - Channel n Event Control
chintenclr30: CHINTENCLR
0x22c - Channel n Interrupt Enable Clear
chintenset30: CHINTENSET
0x22d - Channel n Interrupt Enable Set
chintflag30: CHINTFLAG
0x22e - Channel n Interrupt Flag Status and Clear
chstatus30: CHSTATUS
0x22f - Channel n Status
chctrla31: CHCTRLA
0x230 - Channel n Control A
chctrlb31: CHCTRLB
0x234 - Channel n Control B
chprilvl31: CHPRILVL
0x235 - Channel n Priority Level
chevctrl31: CHEVCTRL
0x236 - Channel n Event Control
chintenclr31: CHINTENCLR
0x23c - Channel n Interrupt Enable Clear
chintenset31: CHINTENSET
0x23d - Channel n Interrupt Enable Set
chintflag31: CHINTFLAG
0x23e - Channel n Interrupt Flag Status and Clear
chstatus31: CHSTATUS
0x23f - Channel n Status
Auto Trait Implementations
impl Send for RegisterBlock
impl !Sync for RegisterBlock
Blanket Implementations
impl<T, U> TryFrom for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T> From for T
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impl<T, U> TryInto for T where
U: TryFrom<T>,
[src]
U: TryFrom<T>,
type Error = <U as TryFrom<T>>::Error
The type returned in the event of a conversion error.
fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>
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impl<T, U> Into for T where
U: From<T>,
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U: From<T>,
impl<T> Borrow for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,