Module atsamd21_hal::target_device::dmac
[−]
[src]
Direct Memory Access Controller
Modules
active |
Active Channel and Levels |
baseaddr |
Descriptor Memory Section Base Address |
busych |
Busy Channels |
chctrla |
Channel Control A |
chctrlb |
Channel Control B |
chid |
Channel ID |
chintenclr |
Channel Interrupt Enable Clear |
chintenset |
Channel Interrupt Enable Set |
chintflag |
Channel Interrupt Flag Status and Clear |
chstatus |
Channel Status |
crcchksum |
CRC Checksum |
crcctrl |
CRC Control |
crcdatain |
CRC Data Input |
crcstatus |
CRC Status |
ctrl |
Control |
dbgctrl |
Debug Control |
intpend |
Interrupt Pending |
intstatus |
Interrupt Status |
pendch |
Pending Channels |
prictrl0 |
Priority Control 0 |
qosctrl |
QOS Control |
swtrigctrl |
Software Trigger Control |
wrbaddr |
Write-Back Memory Section Base Address |
Structs
ACTIVE |
Active Channel and Levels |
BASEADDR |
Descriptor Memory Section Base Address |
BUSYCH |
Busy Channels |
CHCTRLA |
Channel Control A |
CHCTRLB |
Channel Control B |
CHID |
Channel ID |
CHINTENCLR |
Channel Interrupt Enable Clear |
CHINTENSET |
Channel Interrupt Enable Set |
CHINTFLAG |
Channel Interrupt Flag Status and Clear |
CHSTATUS |
Channel Status |
CRCCHKSUM |
CRC Checksum |
CRCCTRL |
CRC Control |
CRCDATAIN |
CRC Data Input |
CRCSTATUS |
CRC Status |
CTRL |
Control |
DBGCTRL |
Debug Control |
INTPEND |
Interrupt Pending |
INTSTATUS |
Interrupt Status |
PENDCH |
Pending Channels |
PRICTRL0 |
Priority Control 0 |
QOSCTRL |
QOS Control |
RegisterBlock |
Register block |
SWTRIGCTRL |
Software Trigger Control |
WRBADDR |
Write-Back Memory Section Base Address |