Struct atsam4sd32c_pac::tc0::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 38 fields
pub ccr0: CCR0,
pub smmr0: SMMR0,
pub cv0: CV0,
pub ra0: RA0,
pub rb0: RB0,
pub rc0: RC0,
pub sr0: SR0,
pub ier0: IER0,
pub idr0: IDR0,
pub imr0: IMR0,
pub ccr1: CCR1,
pub smmr1: SMMR1,
pub cv1: CV1,
pub ra1: RA1,
pub rb1: RB1,
pub rc1: RC1,
pub sr1: SR1,
pub ier1: IER1,
pub idr1: IDR1,
pub imr1: IMR1,
pub ccr2: CCR2,
pub smmr2: SMMR2,
pub cv2: CV2,
pub ra2: RA2,
pub rb2: RB2,
pub rc2: RC2,
pub sr2: SR2,
pub ier2: IER2,
pub idr2: IDR2,
pub imr2: IMR2,
pub bcr: BCR,
pub bmr: BMR,
pub qier: QIER,
pub qidr: QIDR,
pub qimr: QIMR,
pub qisr: QISR,
pub fmr: FMR,
pub wpmr: WPMR,
/* private fields */
}
Expand description
Register block
Fields§
§ccr0: CCR0
0x00 - Channel Control Register (channel = 0)
smmr0: SMMR0
0x08 - Stepper Motor Mode Register (channel = 0)
cv0: CV0
0x10 - Counter Value (channel = 0)
ra0: RA0
0x14 - Register A (channel = 0)
rb0: RB0
0x18 - Register B (channel = 0)
rc0: RC0
0x1c - Register C (channel = 0)
sr0: SR0
0x20 - Status Register (channel = 0)
ier0: IER0
0x24 - Interrupt Enable Register (channel = 0)
idr0: IDR0
0x28 - Interrupt Disable Register (channel = 0)
imr0: IMR0
0x2c - Interrupt Mask Register (channel = 0)
ccr1: CCR1
0x40 - Channel Control Register (channel = 1)
smmr1: SMMR1
0x48 - Stepper Motor Mode Register (channel = 1)
cv1: CV1
0x50 - Counter Value (channel = 1)
ra1: RA1
0x54 - Register A (channel = 1)
rb1: RB1
0x58 - Register B (channel = 1)
rc1: RC1
0x5c - Register C (channel = 1)
sr1: SR1
0x60 - Status Register (channel = 1)
ier1: IER1
0x64 - Interrupt Enable Register (channel = 1)
idr1: IDR1
0x68 - Interrupt Disable Register (channel = 1)
imr1: IMR1
0x6c - Interrupt Mask Register (channel = 1)
ccr2: CCR2
0x80 - Channel Control Register (channel = 2)
smmr2: SMMR2
0x88 - Stepper Motor Mode Register (channel = 2)
cv2: CV2
0x90 - Counter Value (channel = 2)
ra2: RA2
0x94 - Register A (channel = 2)
rb2: RB2
0x98 - Register B (channel = 2)
rc2: RC2
0x9c - Register C (channel = 2)
sr2: SR2
0xa0 - Status Register (channel = 2)
ier2: IER2
0xa4 - Interrupt Enable Register (channel = 2)
idr2: IDR2
0xa8 - Interrupt Disable Register (channel = 2)
imr2: IMR2
0xac - Interrupt Mask Register (channel = 2)
bcr: BCR
0xc0 - Block Control Register
bmr: BMR
0xc4 - Block Mode Register
qier: QIER
0xc8 - QDEC Interrupt Enable Register
qidr: QIDR
0xcc - QDEC Interrupt Disable Register
qimr: QIMR
0xd0 - QDEC Interrupt Mask Register
qisr: QISR
0xd4 - QDEC Interrupt Status Register
fmr: FMR
0xd8 - Fault Mode Register
wpmr: WPMR
0xe4 - Write Protection Mode Register
Implementations§
source§impl RegisterBlock
impl RegisterBlock
sourcepub const fn wave_eq_1_cmr0_wave_eq_1(&self) -> &WAVE_EQ_1_CMR0_WAVE_EQ_1
pub const fn wave_eq_1_cmr0_wave_eq_1(&self) -> &WAVE_EQ_1_CMR0_WAVE_EQ_1
0x04 - Channel Mode Register (channel = 0)
sourcepub const fn wave_eq_1_cmr1_wave_eq_1(&self) -> &WAVE_EQ_1_CMR1_WAVE_EQ_1
pub const fn wave_eq_1_cmr1_wave_eq_1(&self) -> &WAVE_EQ_1_CMR1_WAVE_EQ_1
0x44 - Channel Mode Register (channel = 1)
sourcepub const fn wave_eq_1_cmr2_wave_eq_1(&self) -> &WAVE_EQ_1_CMR2_WAVE_EQ_1
pub const fn wave_eq_1_cmr2_wave_eq_1(&self) -> &WAVE_EQ_1_CMR2_WAVE_EQ_1
0x84 - Channel Mode Register (channel = 2)