Struct atsam4n8b_pac::tc0::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 44 fields
pub ccr0: Reg<CCR0_SPEC>,
pub smmr0: Reg<SMMR0_SPEC>,
pub cv0: Reg<CV0_SPEC>,
pub ra0: Reg<RA0_SPEC>,
pub rb0: Reg<RB0_SPEC>,
pub rc0: Reg<RC0_SPEC>,
pub sr0: Reg<SR0_SPEC>,
pub ier0: Reg<IER0_SPEC>,
pub idr0: Reg<IDR0_SPEC>,
pub imr0: Reg<IMR0_SPEC>,
pub ccr1: Reg<CCR1_SPEC>,
pub smmr1: Reg<SMMR1_SPEC>,
pub cv1: Reg<CV1_SPEC>,
pub ra1: Reg<RA1_SPEC>,
pub rb1: Reg<RB1_SPEC>,
pub rc1: Reg<RC1_SPEC>,
pub sr1: Reg<SR1_SPEC>,
pub ier1: Reg<IER1_SPEC>,
pub idr1: Reg<IDR1_SPEC>,
pub imr1: Reg<IMR1_SPEC>,
pub ccr2: Reg<CCR2_SPEC>,
pub smmr2: Reg<SMMR2_SPEC>,
pub cv2: Reg<CV2_SPEC>,
pub ra2: Reg<RA2_SPEC>,
pub rb2: Reg<RB2_SPEC>,
pub rc2: Reg<RC2_SPEC>,
pub sr2: Reg<SR2_SPEC>,
pub ier2: Reg<IER2_SPEC>,
pub idr2: Reg<IDR2_SPEC>,
pub imr2: Reg<IMR2_SPEC>,
pub bcr: Reg<BCR_SPEC>,
pub bmr: Reg<BMR_SPEC>,
pub qier: Reg<QIER_SPEC>,
pub qidr: Reg<QIDR_SPEC>,
pub qimr: Reg<QIMR_SPEC>,
pub qisr: Reg<QISR_SPEC>,
pub fmr: Reg<FMR_SPEC>,
pub wpmr: Reg<WPMR_SPEC>,
pub rpr2: Reg<RPR2_SPEC>,
pub rcr2: Reg<RCR2_SPEC>,
pub rnpr2: Reg<RNPR2_SPEC>,
pub rncr2: Reg<RNCR2_SPEC>,
pub ptcr2: Reg<PTCR2_SPEC>,
pub ptsr2: Reg<PTSR2_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
ccr0: Reg<CCR0_SPEC>
0x00 - Channel Control Register (channel = 0)
smmr0: Reg<SMMR0_SPEC>
0x08 - Stepper Motor Mode Register (channel = 0)
cv0: Reg<CV0_SPEC>
0x10 - Counter Value (channel = 0)
ra0: Reg<RA0_SPEC>
0x14 - Register A (channel = 0)
rb0: Reg<RB0_SPEC>
0x18 - Register B (channel = 0)
rc0: Reg<RC0_SPEC>
0x1c - Register C (channel = 0)
sr0: Reg<SR0_SPEC>
0x20 - Status Register (channel = 0)
ier0: Reg<IER0_SPEC>
0x24 - Interrupt Enable Register (channel = 0)
idr0: Reg<IDR0_SPEC>
0x28 - Interrupt Disable Register (channel = 0)
imr0: Reg<IMR0_SPEC>
0x2c - Interrupt Mask Register (channel = 0)
ccr1: Reg<CCR1_SPEC>
0x40 - Channel Control Register (channel = 1)
smmr1: Reg<SMMR1_SPEC>
0x48 - Stepper Motor Mode Register (channel = 1)
cv1: Reg<CV1_SPEC>
0x50 - Counter Value (channel = 1)
ra1: Reg<RA1_SPEC>
0x54 - Register A (channel = 1)
rb1: Reg<RB1_SPEC>
0x58 - Register B (channel = 1)
rc1: Reg<RC1_SPEC>
0x5c - Register C (channel = 1)
sr1: Reg<SR1_SPEC>
0x60 - Status Register (channel = 1)
ier1: Reg<IER1_SPEC>
0x64 - Interrupt Enable Register (channel = 1)
idr1: Reg<IDR1_SPEC>
0x68 - Interrupt Disable Register (channel = 1)
imr1: Reg<IMR1_SPEC>
0x6c - Interrupt Mask Register (channel = 1)
ccr2: Reg<CCR2_SPEC>
0x80 - Channel Control Register (channel = 2)
smmr2: Reg<SMMR2_SPEC>
0x88 - Stepper Motor Mode Register (channel = 2)
cv2: Reg<CV2_SPEC>
0x90 - Counter Value (channel = 2)
ra2: Reg<RA2_SPEC>
0x94 - Register A (channel = 2)
rb2: Reg<RB2_SPEC>
0x98 - Register B (channel = 2)
rc2: Reg<RC2_SPEC>
0x9c - Register C (channel = 2)
sr2: Reg<SR2_SPEC>
0xa0 - Status Register (channel = 2)
ier2: Reg<IER2_SPEC>
0xa4 - Interrupt Enable Register (channel = 2)
idr2: Reg<IDR2_SPEC>
0xa8 - Interrupt Disable Register (channel = 2)
imr2: Reg<IMR2_SPEC>
0xac - Interrupt Mask Register (channel = 2)
bcr: Reg<BCR_SPEC>
0xc0 - Block Control Register
bmr: Reg<BMR_SPEC>
0xc4 - Block Mode Register
qier: Reg<QIER_SPEC>
0xc8 - QDEC Interrupt Enable Register
qidr: Reg<QIDR_SPEC>
0xcc - QDEC Interrupt Disable Register
qimr: Reg<QIMR_SPEC>
0xd0 - QDEC Interrupt Mask Register
qisr: Reg<QISR_SPEC>
0xd4 - QDEC Interrupt Status Register
fmr: Reg<FMR_SPEC>
0xd8 - Fault Mode Register
wpmr: Reg<WPMR_SPEC>
0xe4 - Write Protect Mode Register
rpr2: Reg<RPR2_SPEC>
0x180 - Receive Pointer Register (pdc = 2)
rcr2: Reg<RCR2_SPEC>
0x184 - Receive Counter Register (pdc = 2)
rnpr2: Reg<RNPR2_SPEC>
0x190 - Receive Next Pointer Register (pdc = 2)
rncr2: Reg<RNCR2_SPEC>
0x194 - Receive Next Counter Register (pdc = 2)
ptcr2: Reg<PTCR2_SPEC>
0x1a0 - Transfer Control Register (pdc = 2)
ptsr2: Reg<PTSR2_SPEC>
0x1a4 - Transfer Status Register (pdc = 2)
Implementations
0x04 - Channel Mode Register (channel = 0)
0x44 - Channel Mode Register (channel = 1)
0x84 - Channel Mode Register (channel = 2)