Struct atsam4lc8a_pac::scif::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 36 fields
pub ier: Reg<IER_SPEC>,
pub idr: Reg<IDR_SPEC>,
pub imr: Reg<IMR_SPEC>,
pub isr: Reg<ISR_SPEC>,
pub icr: Reg<ICR_SPEC>,
pub pclksr: Reg<PCLKSR_SPEC>,
pub unlock: Reg<UNLOCK_SPEC>,
pub cscr: Reg<CSCR_SPEC>,
pub oscctrl0: Reg<OSCCTRL0_SPEC>,
pub pll: Reg<PLL_SPEC>,
pub dfll0conf: Reg<DFLL0CONF_SPEC>,
pub dfll0val: Reg<DFLL0VAL_SPEC>,
pub dfll0mul: Reg<DFLL0MUL_SPEC>,
pub dfll0step: Reg<DFLL0STEP_SPEC>,
pub dfll0ssg: Reg<DFLL0SSG_SPEC>,
pub dfll0ratio: Reg<DFLL0RATIO_SPEC>,
pub dfll0sync: Reg<DFLL0SYNC_SPEC>,
pub rccr: Reg<RCCR_SPEC>,
pub rcfastcfg: Reg<RCFASTCFG_SPEC>,
pub rcfastsr: Reg<RCFASTSR_SPEC>,
pub rc80mcr: Reg<RC80MCR_SPEC>,
pub hrpcr: Reg<HRPCR_SPEC>,
pub fpcr: Reg<FPCR_SPEC>,
pub fpmul: Reg<FPMUL_SPEC>,
pub fpdiv: Reg<FPDIV_SPEC>,
pub gcctrl: [Reg<GCCTRL_SPEC>; 12],
pub rcfastversion: Reg<RCFASTVERSION_SPEC>,
pub gclkprescversion: Reg<GCLKPRESCVERSION_SPEC>,
pub pllifaversion: Reg<PLLIFAVERSION_SPEC>,
pub oscifaversion: Reg<OSCIFAVERSION_SPEC>,
pub dfllifbversion: Reg<DFLLIFBVERSION_SPEC>,
pub rcoscifaversion: Reg<RCOSCIFAVERSION_SPEC>,
pub floversion: Reg<FLOVERSION_SPEC>,
pub rc80mversion: Reg<RC80MVERSION_SPEC>,
pub gclkifversion: Reg<GCLKIFVERSION_SPEC>,
pub version: Reg<VERSION_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
ier: Reg<IER_SPEC>
0x00 - Interrupt Enable Register
idr: Reg<IDR_SPEC>
0x04 - Interrupt Disable Register
imr: Reg<IMR_SPEC>
0x08 - Interrupt Mask Register
isr: Reg<ISR_SPEC>
0x0c - Interrupt Status Register
icr: Reg<ICR_SPEC>
0x10 - Interrupt Clear Register
pclksr: Reg<PCLKSR_SPEC>
0x14 - Power and Clocks Status Register
unlock: Reg<UNLOCK_SPEC>
0x18 - Unlock Register
cscr: Reg<CSCR_SPEC>
0x1c - Chip Specific Configuration Register
oscctrl0: Reg<OSCCTRL0_SPEC>
0x20 - Oscillator Control Register
pll: Reg<PLL_SPEC>
0x24 - PLL0 Control Register
dfll0conf: Reg<DFLL0CONF_SPEC>
0x28 - DFLL0 Config Register
dfll0val: Reg<DFLL0VAL_SPEC>
0x2c - DFLL Value Register
dfll0mul: Reg<DFLL0MUL_SPEC>
0x30 - DFLL0 Multiplier Register
dfll0step: Reg<DFLL0STEP_SPEC>
0x34 - DFLL0 Step Register
dfll0ssg: Reg<DFLL0SSG_SPEC>
0x38 - DFLL0 Spread Spectrum Generator Control Register
dfll0ratio: Reg<DFLL0RATIO_SPEC>
0x3c - DFLL0 Ratio Registe
dfll0sync: Reg<DFLL0SYNC_SPEC>
0x40 - DFLL0 Synchronization Register
rccr: Reg<RCCR_SPEC>
0x44 - System RC Oscillator Calibration Register
rcfastcfg: Reg<RCFASTCFG_SPEC>
0x48 - 4/8/12 MHz RC Oscillator Configuration Register
rcfastsr: Reg<RCFASTSR_SPEC>
0x4c - 4/8/12 MHz RC Oscillator Status Register
rc80mcr: Reg<RC80MCR_SPEC>
0x50 - 80 MHz RC Oscillator Register
hrpcr: Reg<HRPCR_SPEC>
0x64 - High Resolution Prescaler Control Register
fpcr: Reg<FPCR_SPEC>
0x68 - Fractional Prescaler Control Register
fpmul: Reg<FPMUL_SPEC>
0x6c - Fractional Prescaler Multiplier Register
fpdiv: Reg<FPDIV_SPEC>
0x70 - Fractional Prescaler DIVIDER Register
gcctrl: [Reg<GCCTRL_SPEC>; 12]
0x74..0xa4 - Generic Clock Control
rcfastversion: Reg<RCFASTVERSION_SPEC>
0x3d8 - 4/8/12 MHz RC Oscillator Version Register
gclkprescversion: Reg<GCLKPRESCVERSION_SPEC>
0x3dc - Generic Clock Prescaler Version Register
pllifaversion: Reg<PLLIFAVERSION_SPEC>
0x3e0 - PLL Version Register
oscifaversion: Reg<OSCIFAVERSION_SPEC>
0x3e4 - Oscillator 0 Version Register
dfllifbversion: Reg<DFLLIFBVERSION_SPEC>
0x3e8 - DFLL Version Register
rcoscifaversion: Reg<RCOSCIFAVERSION_SPEC>
0x3ec - System RC Oscillator Version Register
floversion: Reg<FLOVERSION_SPEC>
0x3f0 - Frequency Locked Oscillator Version Register
rc80mversion: Reg<RC80MVERSION_SPEC>
0x3f4 - 80MHz RC Oscillator Version Register
gclkifversion: Reg<GCLKIFVERSION_SPEC>
0x3f8 - Generic Clock Version Register
version: Reg<VERSION_SPEC>
0x3fc - SCIF Version Register