Type Definition atsam4lc8a_pac::twim0::idr::W [−][src]
type W = W<u32, IDR>;
Writer for register IDR
Implementations
impl W
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pub fn rxrdy(&mut self) -> RXRDY_W<'_>
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Bit 0 - RHR Data Ready
pub fn txrdy(&mut self) -> TXRDY_W<'_>
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Bit 1 - THR Data Ready
pub fn crdy(&mut self) -> CRDY_W<'_>
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Bit 2 - Ready for More Commands
pub fn ccomp(&mut self) -> CCOMP_W<'_>
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Bit 3 - Command Complete
pub fn idle(&mut self) -> IDLE_W<'_>
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Bit 4 - Master Interface is Idle
pub fn busfree(&mut self) -> BUSFREE_W<'_>
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Bit 5 - Two-wire Bus is Free
pub fn anak(&mut self) -> ANAK_W<'_>
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Bit 8 - NAK in Address Phase Received
pub fn dnak(&mut self) -> DNAK_W<'_>
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Bit 9 - NAK in Data Phase Received
pub fn arblst(&mut self) -> ARBLST_W<'_>
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Bit 10 - Arbitration Lost
pub fn smbalert(&mut self) -> SMBALERT_W<'_>
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Bit 11 - SMBus Alert
pub fn tout(&mut self) -> TOUT_W<'_>
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Bit 12 - Timeout
pub fn pecerr(&mut self) -> PECERR_W<'_>
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Bit 13 - PEC Error
pub fn stop(&mut self) -> STOP_W<'_>
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Bit 14 - Stop Request Accepted
pub fn hsmcack(&mut self) -> HSMCACK_W<'_>
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Bit 17 - ACK in HS-mode Master Code Phase Received