Struct atsam4e8e_pac::dmac::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub gcfg: Reg<GCFG_SPEC>,
    pub en: Reg<EN_SPEC>,
    pub sreq: Reg<SREQ_SPEC>,
    pub creq: Reg<CREQ_SPEC>,
    pub last: Reg<LAST_SPEC>,
    pub ebcier: Reg<EBCIER_SPEC>,
    pub ebcidr: Reg<EBCIDR_SPEC>,
    pub ebcimr: Reg<EBCIMR_SPEC>,
    pub ebcisr: Reg<EBCISR_SPEC>,
    pub cher: Reg<CHER_SPEC>,
    pub chdr: Reg<CHDR_SPEC>,
    pub chsr: Reg<CHSR_SPEC>,
    pub saddr0: Reg<SADDR0_SPEC>,
    pub daddr0: Reg<DADDR0_SPEC>,
    pub dscr0: Reg<DSCR0_SPEC>,
    pub ctrla0: Reg<CTRLA0_SPEC>,
    pub ctrlb0: Reg<CTRLB0_SPEC>,
    pub cfg0: Reg<CFG0_SPEC>,
    pub saddr1: Reg<SADDR1_SPEC>,
    pub daddr1: Reg<DADDR1_SPEC>,
    pub dscr1: Reg<DSCR1_SPEC>,
    pub ctrla1: Reg<CTRLA1_SPEC>,
    pub ctrlb1: Reg<CTRLB1_SPEC>,
    pub cfg1: Reg<CFG1_SPEC>,
    pub saddr2: Reg<SADDR2_SPEC>,
    pub daddr2: Reg<DADDR2_SPEC>,
    pub dscr2: Reg<DSCR2_SPEC>,
    pub ctrla2: Reg<CTRLA2_SPEC>,
    pub ctrlb2: Reg<CTRLB2_SPEC>,
    pub cfg2: Reg<CFG2_SPEC>,
    pub saddr3: Reg<SADDR3_SPEC>,
    pub daddr3: Reg<DADDR3_SPEC>,
    pub dscr3: Reg<DSCR3_SPEC>,
    pub ctrla3: Reg<CTRLA3_SPEC>,
    pub ctrlb3: Reg<CTRLB3_SPEC>,
    pub cfg3: Reg<CFG3_SPEC>,
    pub wpmr: Reg<WPMR_SPEC>,
    pub wpsr: Reg<WPSR_SPEC>,
    /* private fields */
}

Register block

Fields

gcfg: Reg<GCFG_SPEC>

0x00 - DMAC Global Configuration Register

en: Reg<EN_SPEC>

0x04 - DMAC Enable Register

sreq: Reg<SREQ_SPEC>

0x08 - DMAC Software Single Request Register

creq: Reg<CREQ_SPEC>

0x0c - DMAC Software Chunk Transfer Request Register

last: Reg<LAST_SPEC>

0x10 - DMAC Software Last Transfer Flag Register

ebcier: Reg<EBCIER_SPEC>

0x18 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.

ebcidr: Reg<EBCIDR_SPEC>

0x1c - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.

ebcimr: Reg<EBCIMR_SPEC>

0x20 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.

ebcisr: Reg<EBCISR_SPEC>

0x24 - DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.

cher: Reg<CHER_SPEC>

0x28 - DMAC Channel Handler Enable Register

chdr: Reg<CHDR_SPEC>

0x2c - DMAC Channel Handler Disable Register

chsr: Reg<CHSR_SPEC>

0x30 - DMAC Channel Handler Status Register

saddr0: Reg<SADDR0_SPEC>

0x3c - DMAC Channel Source Address Register (ch_num = 0)

daddr0: Reg<DADDR0_SPEC>

0x40 - DMAC Channel Destination Address Register (ch_num = 0)

dscr0: Reg<DSCR0_SPEC>

0x44 - DMAC Channel Descriptor Address Register (ch_num = 0)

ctrla0: Reg<CTRLA0_SPEC>

0x48 - DMAC Channel Control A Register (ch_num = 0)

ctrlb0: Reg<CTRLB0_SPEC>

0x4c - DMAC Channel Control B Register (ch_num = 0)

cfg0: Reg<CFG0_SPEC>

0x50 - DMAC Channel Configuration Register (ch_num = 0)

saddr1: Reg<SADDR1_SPEC>

0x64 - DMAC Channel Source Address Register (ch_num = 1)

daddr1: Reg<DADDR1_SPEC>

0x68 - DMAC Channel Destination Address Register (ch_num = 1)

dscr1: Reg<DSCR1_SPEC>

0x6c - DMAC Channel Descriptor Address Register (ch_num = 1)

ctrla1: Reg<CTRLA1_SPEC>

0x70 - DMAC Channel Control A Register (ch_num = 1)

ctrlb1: Reg<CTRLB1_SPEC>

0x74 - DMAC Channel Control B Register (ch_num = 1)

cfg1: Reg<CFG1_SPEC>

0x78 - DMAC Channel Configuration Register (ch_num = 1)

saddr2: Reg<SADDR2_SPEC>

0x8c - DMAC Channel Source Address Register (ch_num = 2)

daddr2: Reg<DADDR2_SPEC>

0x90 - DMAC Channel Destination Address Register (ch_num = 2)

dscr2: Reg<DSCR2_SPEC>

0x94 - DMAC Channel Descriptor Address Register (ch_num = 2)

ctrla2: Reg<CTRLA2_SPEC>

0x98 - DMAC Channel Control A Register (ch_num = 2)

ctrlb2: Reg<CTRLB2_SPEC>

0x9c - DMAC Channel Control B Register (ch_num = 2)

cfg2: Reg<CFG2_SPEC>

0xa0 - DMAC Channel Configuration Register (ch_num = 2)

saddr3: Reg<SADDR3_SPEC>

0xb4 - DMAC Channel Source Address Register (ch_num = 3)

daddr3: Reg<DADDR3_SPEC>

0xb8 - DMAC Channel Destination Address Register (ch_num = 3)

dscr3: Reg<DSCR3_SPEC>

0xbc - DMAC Channel Descriptor Address Register (ch_num = 3)

ctrla3: Reg<CTRLA3_SPEC>

0xc0 - DMAC Channel Control A Register (ch_num = 3)

ctrlb3: Reg<CTRLB3_SPEC>

0xc4 - DMAC Channel Control B Register (ch_num = 3)

cfg3: Reg<CFG3_SPEC>

0xc8 - DMAC Channel Configuration Register (ch_num = 3)

wpmr: Reg<WPMR_SPEC>

0x1e4 - DMAC Write Protect Mode Register

wpsr: Reg<WPSR_SPEC>

0x1e8 - DMAC Write Protect Status Register