Struct Assembler 

pub struct Assembler<'a> { /* private fields */ }

Implementations

impl<'a> Assembler<'a>

pub fn new(buffer: &'a mut CodeBuffer) -> Self

pub fn try_new(buffer: &'a mut CodeBuffer) -> Result<Self, AsmError>

pub fn environment(&self) -> &Environment

Returns the environment (arch/mode) this assembler targets.

pub fn is_32bit(&self) -> bool

Tests whether the assembler targets a 32-bit mode (always false for A64).

pub fn is_64bit(&self) -> bool

Tests whether the assembler targets a 64-bit mode (always true for A64).

pub fn get_label(&mut self) -> Label

pub fn bind_label(&mut self, label: Label)

pub fn try_bind_label(&mut self, label: Label) -> Result<(), AsmError>

pub fn load_constant<DST, SRC>(&mut self, dst: DST, src: SRC)

where Self: LoadConstantEmitter<DST, SRC>,

A helper to load a constant address into a register.

Supported variants are:

+------------------+
|  DST  |  SRC     |
+------------------+
|  Gp   | Label    |
|  Gp   | Sym      |
|  Gp   | Constant |
+------------------+

Note that Sym is loaded based on self.buffer.pic() and its distance. If PIC is enabled then GOT is always used. Otherwise, if symbol is near it uses adrp + add combination, and for far symbols Abs8 reloc is used and data is embedded right into code.

pub fn emit_n(&mut self, id: impl Into<u32>, ops: &[&Operand])

pub fn try_emit_n( &mut self, id: impl Into<u32>, ops: &[&Operand], ) -> Result<(), AsmError>

pub fn data(&self) -> &[u8]

pub fn relocs(&self) -> &[AsmReloc]

pub fn error(&self) -> Option<&AsmError>

pub fn reserve_patch_block( &mut self, size: CodeOffset, align: CodeOffset, ) -> Result<PatchableBlock, AsmError>

Reserve a nop-filled island for later custom rewriting.

pub fn patchable_b(&mut self, label: Label) -> PatchableSite

pub fn patchable_bl(&mut self, label: Label) -> PatchableSite

pub fn patchable_mov(&mut self, rd: Gp, imm: impl Into<u64>) -> PatchableBlock

Patchable immediate materialization via a fixed movz/movk sequence.

64-bit destinations use 16 bytes (4 insns); 32-bit destinations use 8 bytes (2 insns). Rewrite with encode_patchable_mov_imm + PatchableBlock::rewrite, or PatchableBlock::repatch_u64 is not used here (the block covers whole instructions).

impl Assembler<'_>

pub fn adc<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: AdcEmitter<T0, T1, T2>,

Emits the ADC instruction. Assembly forms: ADC WD, WN, WM; ADC XD, XN, XM. Operands: rd, rn, rm.

pub fn adcs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: AdcsEmitter<T0, T1, T2>,

Emits the ADCS instruction. Assembly forms: ADCS WD, WN, WM; ADCS XD, XN, XM. Operands: rd, rn, rm.

pub fn add<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: AddEmitter<T0, T1, T2>,

Emits the ADD instruction. Assembly forms: ADD WD, WN, WM, {LSL|LSR|ASR #N}; ADD XD, XN, XM, {LSL|LSR|ASR #N}; ADD WD|WSP, WN|WSP, WM, {EXTEND #N}; ADD XD|SP, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm.

pub fn add_4<T0, T1, T2, T3>( &mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3, )

where Self: Add4Emitter<T0, T1, T2, T3>,

Emits the ADD_4 instruction. Assembly forms: ADD WD, WN, WM, {LSL|LSR|ASR #N}; ADD XD, XN, XM, {LSL|LSR|ASR #N}; ADD WD|WSP, WN|WSP, WM, {EXTEND #N}; ADD XD|SP, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm, shift.

pub fn adds<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: AddsEmitter<T0, T1, T2>,

Emits the ADDS instruction. Assembly forms: ADDS WD, WN, WM, {LSL|LSR|ASR #N}; ADDS XD, XN, XM, {LSL|LSR|ASR #N}; ADDS WD, WN|WSP, WM, {EXTEND #N}; ADDS XD, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm.

pub fn adds_4<T0, T1, T2, T3>( &mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3, )

where Self: Adds4Emitter<T0, T1, T2, T3>,

Emits the ADDS_4 instruction. Assembly forms: ADDS WD, WN, WM, {LSL|LSR|ASR #N}; ADDS XD, XN, XM, {LSL|LSR|ASR #N}; ADDS WD, WN|WSP, WM, {EXTEND #N}; ADDS XD, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm, shift.

pub fn adr<T0, T1>(&mut self, rd: T0, target: T1)

where Self: AdrEmitter<T0, T1>,

Emits the ADR instruction. Assembly forms: ADR XD, #RELS. Operands: rd, target.

pub fn adrp<T0, T1>(&mut self, rd: T0, target: T1)

where Self: AdrpEmitter<T0, T1>,

Emits the ADRP instruction. Assembly forms: ADRP XD, #RELS. Operands: rd, target.

pub fn and_<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: AndEmitter<T0, T1, T2>,

Emits the AND_ instruction. Assembly forms: AND WD|WSP, WN, WM, {SOP #N}; AND XD|SP, XN, XM, {SOP #N}; AND WD|WSP, WN, #IMM; AND XD|SP, XN, #IMM (and related forms). Operands: rd, rn, rm_or_imm.

pub fn and__4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: And4Emitter<T0, T1, T2, T3>,

Emits the AND__4 instruction. Assembly forms: AND WD|WSP, WN, WM, {SOP #N}; AND XD|SP, XN, XM, {SOP #N}; AND WD|WSP, WN, #IMM; AND XD|SP, XN, #IMM (and related forms). Operands: rd, rn, rm, shift.

pub fn ands<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: AndsEmitter<T0, T1, T2>,

Emits the ANDS instruction. Assembly forms: ANDS WD|WSP, WN, WM, {SOP #N}; ANDS XD|SP, XN, XM, {SOP #N}; ANDS WD|WSP, WN, #IMM; ANDS XD|SP, XN, #IMM. Operands: rd, rn, rm_or_imm.

pub fn ands_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Ands4Emitter<T0, T1, T2, T3>,

Emits the ANDS_4 instruction. Assembly forms: ANDS WD|WSP, WN, WM, {SOP #N}; ANDS XD|SP, XN, XM, {SOP #N}; ANDS WD|WSP, WN, #IMM; ANDS XD|SP, XN, #IMM. Operands: rd, rn, rm, shift.

pub fn asr<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: AsrEmitter<T0, T1, T2>,

Emits the ASR instruction. Assembly forms: ASR|ASRV WD, WN, WM; ASR|ASRV XD, XN, XM; ASR WD, WN, #N; ASR XD, XN, #N. Operands: rd, rn, rm_or_shift.

pub fn asrv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: AsrvEmitter<T0, T1, T2>,

Emits the ASRV instruction. Assembly forms: ASR|ASRV WD, WN, WM; ASR|ASRV XD, XN, XM. Operands: rd, rn, rm.

pub fn at<T0, T1>(&mut self, at_op: T0, rt: T1)

where Self: AtEmitter<T0, T1>,

Emits the AT instruction. Assembly forms: AT #AT_OP, XT. Operands: at_op, rt.

pub fn bfc<T0, T1, T2>(&mut self, rd: T0, lsb: T1, width: T2)

where Self: BfcEmitter<T0, T1, T2>,

Emits the BFC instruction. Assembly forms: BFC WD, #LSB, #WIDTH; BFC XD, #LSB, #WIDTH. Operands: rd, lsb, width.

pub fn bfi<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: BfiEmitter<T0, T1, T2, T3>,

Emits the BFI instruction. Assembly forms: BFI WD, WN, #LSB, #WIDTH; BFI XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn bfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)

where Self: BfmEmitter<T0, T1, T2, T3>,

Emits the BFM instruction. Assembly forms: BFM WD, WN, #IMMR, #IMMS; BFM XD, XN, #IMMR, #IMMS. Operands: rd, rn, imm, imm_2.

pub fn bfxil<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: BfxilEmitter<T0, T1, T2, T3>,

Emits the BFXIL instruction. Assembly forms: BFXIL WD, WN, #LSB, #WIDTH; BFXIL XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn bic<T0, T1, T2>(&mut self, rd: T0, rn_or_imm: T1, rm_or_shift: T2)

where Self: BicEmitter<T0, T1, T2>,

Emits the BIC instruction. Assembly forms: BIC WD, WN, WM, {SOP #N}; BIC XD, XN, XM, {SOP #N}; BIC VD.8B, VN.8B, VM.8B; BIC VD.16B, VN.16B, VM.16B (and related forms). Operands: rd, rn_or_imm, rm_or_shift.

pub fn bic_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Bic4Emitter<T0, T1, T2, T3>,

Emits the BIC_4 instruction. Assembly forms: BIC WD, WN, WM, {SOP #N}; BIC XD, XN, XM, {SOP #N}; BIC VD.8B, VN.8B, VM.8B; BIC VD.16B, VN.16B, VM.16B (and related forms). Operands: rd, rn, rm, shift.

pub fn bics<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: BicsEmitter<T0, T1, T2>,

Emits the BICS instruction. Assembly forms: BICS WD, WN, WM, {SOP #N}; BICS XD, XN, XM, {SOP #N}. Operands: rd, rn, rm.

pub fn bics_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Bics4Emitter<T0, T1, T2, T3>,

Emits the BICS_4 instruction. Assembly forms: BICS WD, WN, WM, {SOP #N}; BICS XD, XN, XM, {SOP #N}. Operands: rd, rn, rm, shift.

pub fn brk<T0>(&mut self, imm: T0)

where Self: BrkEmitter<T0>,

Emits the BRK instruction. Assembly forms: BRK #IMM. Operands: imm.

pub fn ccmn<T0, T1, T2, T3>( &mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3, )

where Self: CcmnEmitter<T0, T1, T2, T3>,

Emits the CCMN instruction. Assembly forms: CCMN WN, WM, #NZCV, #COND; CCMN XN, XM, #NZCV, #COND; CCMN WN, #IMM, #NZCV, #COND; CCMN XN, #IMM, #NZCV, #COND. Operands: rn, rm_or_imm, flags, condition.

pub fn ccmp<T0, T1, T2, T3>( &mut self, rn: T0, rm_or_imm: T1, flags: T2, condition: T3, )

where Self: CcmpEmitter<T0, T1, T2, T3>,

Emits the CCMP instruction. Assembly forms: CCMP WN, WM, #NZCV, #COND; CCMP XN, XM, #NZCV, #COND; CCMP WN, #IMM, #NZCV, #COND; CCMP XN, #IMM, #NZCV, #COND. Operands: rn, rm_or_imm, flags, condition.

pub fn cinc<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)

where Self: CincEmitter<T0, T1, T2>,

Emits the CINC instruction. Assembly forms: CINC WD, WN, #COND; CINC XD, XN, #COND. Operands: rd, rn, condition.

pub fn cinv<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)

where Self: CinvEmitter<T0, T1, T2>,

Emits the CINV instruction. Assembly forms: CINV WD, WN, #COND; CINV XD, XN, #COND. Operands: rd, rn, condition.

pub fn clrex<T0>(&mut self, imm: T0)

where Self: ClrexEmitter<T0>,

Emits the CLREX instruction. Assembly forms: CLREX {#IMM=15}. Operands: imm.

pub fn cls<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: ClsEmitter<T0, T1>,

Emits the CLS instruction. Assembly forms: CLS WD, WN; CLS XD, XN; CLS VD.T, VN.T; CLS VD.T, VN.T. Operands: rd, rn.

pub fn clz<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: ClzEmitter<T0, T1>,

Emits the CLZ instruction. Assembly forms: CLZ WD, WN; CLZ XD, XN; CLZ VD.T, VN.T; CLZ VD.T, VN.T. Operands: rd, rn.

pub fn cmn<T0, T1>(&mut self, rn: T0, imm_or_rm: T1)

where Self: CmnEmitter<T0, T1>,

Emits the CMN instruction. Assembly forms: CMN WN|WSP, #IMM, {LSL #N=0|12}; CMN XN|SP, #IMM, {LSL #N=0|12}; CMN WN|WSP, WM, {EXTEND #N}; CMN XN|SP, RM, {EXTEND #N} (and related forms). Operands: rn, imm_or_rm.

pub fn cmn_3<T0, T1, T2>(&mut self, rn: T0, imm_or_rm: T1, shift: T2)

where Self: Cmn3Emitter<T0, T1, T2>,

Emits the CMN_3 instruction. Assembly forms: CMN WN|WSP, #IMM, {LSL #N=0|12}; CMN XN|SP, #IMM, {LSL #N=0|12}; CMN WN|WSP, WM, {EXTEND #N}; CMN XN|SP, RM, {EXTEND #N} (and related forms). Operands: rn, imm_or_rm, shift.

pub fn cmp<T0, T1>(&mut self, rn: T0, rm_or_imm: T1)

where Self: CmpEmitter<T0, T1>,

Emits the CMP instruction. Assembly forms: CMP WN, WM, {LSL|LSR|ASR #N}; CMP XN, XM, {LSL|LSR|ASR #N}; CMP WN|WSP, WM, {EXTEND #N}; CMP XN|SP, RM, {EXTEND #N} (and related forms). Operands: rn, rm_or_imm.

pub fn cmp_3<T0, T1, T2>(&mut self, rn: T0, rm_or_imm: T1, shift: T2)

where Self: Cmp3Emitter<T0, T1, T2>,

Emits the CMP_3 instruction. Assembly forms: CMP WN, WM, {LSL|LSR|ASR #N}; CMP XN, XM, {LSL|LSR|ASR #N}; CMP WN|WSP, WM, {EXTEND #N}; CMP XN|SP, RM, {EXTEND #N} (and related forms). Operands: rn, rm_or_imm, shift.

pub fn cneg<T0, T1, T2>(&mut self, rd: T0, rn: T1, condition: T2)

where Self: CnegEmitter<T0, T1, T2>,

Emits the CNEG instruction. Assembly forms: CNEG WD, WN, #COND; CNEG XD, XN, #COND. Operands: rd, rn, condition.

pub fn csel<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)

where Self: CselEmitter<T0, T1, T2, T3>,

Emits the CSEL instruction. Assembly forms: CSEL WD, WN, WM, #COND; CSEL XD, XN, XM, #COND. Operands: rd, rn, rm, condition.

pub fn cset<T0, T1>(&mut self, rd: T0, condition: T1)

where Self: CsetEmitter<T0, T1>,

Emits the CSET instruction. Assembly forms: CSET WD, #COND; CSET XD, #COND. Operands: rd, condition.

pub fn csetm<T0, T1>(&mut self, rd: T0, condition: T1)

where Self: CsetmEmitter<T0, T1>,

Emits the CSETM instruction. Assembly forms: CSETM WD, #COND; CSETM XD, #COND. Operands: rd, condition.

pub fn csinc<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)

where Self: CsincEmitter<T0, T1, T2, T3>,

Emits the CSINC instruction. Assembly forms: CSINC WD, WN, WM, #COND; CSINC XD, XN, XM, #COND. Operands: rd, rn, rm, condition.

pub fn csinv<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)

where Self: CsinvEmitter<T0, T1, T2, T3>,

Emits the CSINV instruction. Assembly forms: CSINV WD, WN, WM, #COND; CSINV XD, XN, XM, #COND. Operands: rd, rn, rm, condition.

pub fn csneg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)

where Self: CsnegEmitter<T0, T1, T2, T3>,

Emits the CSNEG instruction. Assembly forms: CSNEG WD, WN, WM, #COND; CSNEG XD, XN, XM, #COND. Operands: rd, rn, rm, condition.

pub fn dc<T0, T1>(&mut self, dc_op: T0, rt: T1)

where Self: DcEmitter<T0, T1>,

Emits the DC instruction. Assembly forms: DC #DC_OP, XT. Operands: dc_op, rt.

pub fn dmb<T0>(&mut self, barrier_op: T0)

where Self: DmbEmitter<T0>,

Emits the DMB instruction. Assembly forms: DMB #BARRIER_OP. Operands: barrier_op.

pub fn dsb<T0>(&mut self, barrier_op: T0)

where Self: DsbEmitter<T0>,

Emits the DSB instruction. Assembly forms: DSB #BARRIER_OP. Operands: barrier_op.

pub fn drps(&mut self)

where Self: DrpsEmitter,

Emits the DRPS instruction. Assembly forms: DRPS.

pub fn eon<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: EonEmitter<T0, T1, T2>,

Emits the EON instruction. Assembly forms: EON WD, WN, WM, {SOP #N}; EON XD, XN, XM, {SOP #N}. Operands: rd, rn, rm.

pub fn eon_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Eon4Emitter<T0, T1, T2, T3>,

Emits the EON_4 instruction. Assembly forms: EON WD, WN, WM, {SOP #N}; EON XD, XN, XM, {SOP #N}. Operands: rd, rn, rm, shift.

pub fn eor<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: EorEmitter<T0, T1, T2>,

Emits the EOR instruction. Assembly forms: EOR WD, WN, WM, {SOP #N}; EOR XD, XN, XM, {SOP #N}; EOR WD|WSP, WN, #IMM; EOR XD|SP, XN, #IMM (and related forms). Operands: rd, rn, rm_or_imm.

pub fn eor_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Eor4Emitter<T0, T1, T2, T3>,

Emits the EOR_4 instruction. Assembly forms: EOR WD, WN, WM, {SOP #N}; EOR XD, XN, XM, {SOP #N}; EOR WD|WSP, WN, #IMM; EOR XD|SP, XN, #IMM (and related forms). Operands: rd, rn, rm, shift.

pub fn eret(&mut self)

where Self: EretEmitter,

Emits the ERET instruction. Assembly forms: ERET.

pub fn esb(&mut self)

where Self: EsbEmitter,

Emits the ESB instruction. Assembly forms: ESB.

pub fn extr<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, imm: T3)

where Self: ExtrEmitter<T0, T1, T2, T3>,

Emits the EXTR instruction. Assembly forms: EXTR WD, WN, WM, #IMM; EXTR XD, XN, XM, #IMM. Operands: rd, rn, rm, imm.

pub fn hlt<T0>(&mut self, imm: T0)

where Self: HltEmitter<T0>,

Emits the HLT instruction. Assembly forms: HLT #IMM. Operands: imm.

pub fn hvc<T0>(&mut self, imm: T0)

where Self: HvcEmitter<T0>,

Emits the HVC instruction. Assembly forms: HVC #IMM. Operands: imm.

pub fn ic<T0, T1>(&mut self, ic_op: T0, rt: T1)

where Self: IcEmitter<T0, T1>,

Emits the IC instruction. Assembly forms: IC #IC_OP; IC #IC_OP, XT. Operands: ic_op, rt.

pub fn isb<T0>(&mut self, isb_op: T0)

where Self: IsbEmitter<T0>,

Emits the ISB instruction. Assembly forms: ISB {#ISB_OP=15}. Operands: isb_op.

pub fn lsl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: LslEmitter<T0, T1, T2>,

Emits the LSL instruction. Assembly forms: LSL|LSLV WD, WN, WM; LSL|LSLV XD, XN, XM; LSL WD, WN, #N; LSL XD, XN, #N. Operands: rd, rn, rm_or_shift.

pub fn lslv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: LslvEmitter<T0, T1, T2>,

Emits the LSLV instruction. Assembly forms: LSL|LSLV WD, WN, WM; LSL|LSLV XD, XN, XM. Operands: rd, rn, rm.

pub fn lsr<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: LsrEmitter<T0, T1, T2>,

Emits the LSR instruction. Assembly forms: LSR|LSRV WD, WN, WM; LSR|LSRV XD, XN, XM; LSR WD, WN, #N; LSR XD, XN, #N. Operands: rd, rn, rm_or_shift.

pub fn lsrv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: LsrvEmitter<T0, T1, T2>,

Emits the LSRV instruction. Assembly forms: LSR|LSRV WD, WN, WM; LSR|LSRV XD, XN, XM. Operands: rd, rn, rm.

pub fn madd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: MaddEmitter<T0, T1, T2, T3>,

Emits the MADD instruction. Assembly forms: MADD WD, WN, WM, WA; MADD XD, XN, XM, XA. Operands: rd, rn, rm, operand_4.

pub fn mneg<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: MnegEmitter<T0, T1, T2>,

Emits the MNEG instruction. Assembly forms: MNEG WD, WN, WM; MNEG XD, XN, XM. Operands: rd, rn, rm.

pub fn mov<T0, T1>(&mut self, rd: T0, rm_or_rn_or_imm_or_log_imm: T1)

where Self: MovEmitter<T0, T1>,

Emits the MOV instruction. Assembly forms: MOV WD, WM; MOV XD, XM; MOV WD|WSP, WN|WSP; MOV XD|SP, XN|SP (and related forms). Operands: rd, rm_or_rn_or_imm_or_log_imm.

pub fn movk<T0, T1>(&mut self, rd: T0, imm: T1)

where Self: MovkEmitter<T0, T1>,

Emits the MOVK instruction. Assembly forms: MOVK WD, #IMM, {LSL #N}; MOVK XD, #IMM, {LSL #N}. Operands: rd, imm.

pub fn movk_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)

where Self: Movk3Emitter<T0, T1, T2>,

Emits the MOVK_3 instruction. Assembly forms: MOVK WD, #IMM, {LSL #N}; MOVK XD, #IMM, {LSL #N}. Operands: rd, imm, shift.

pub fn movn<T0, T1>(&mut self, rd: T0, imm: T1)

where Self: MovnEmitter<T0, T1>,

Emits the MOVN instruction. Assembly forms: MOVN WD, #IMM, {LSL #N}; MOVN XD, #IMM, {LSL #N}. Operands: rd, imm.

pub fn movn_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)

where Self: Movn3Emitter<T0, T1, T2>,

Emits the MOVN_3 instruction. Assembly forms: MOVN WD, #IMM, {LSL #N}; MOVN XD, #IMM, {LSL #N}. Operands: rd, imm, shift.

pub fn movz<T0, T1>(&mut self, rd: T0, imm: T1)

where Self: MovzEmitter<T0, T1>,

Emits the MOVZ instruction. Assembly forms: MOVZ WD, #IMM, {LSL #N}; MOVZ XD, #IMM, {LSL #N}. Operands: rd, imm.

pub fn movz_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)

where Self: Movz3Emitter<T0, T1, T2>,

Emits the MOVZ_3 instruction. Assembly forms: MOVZ WD, #IMM, {LSL #N}; MOVZ XD, #IMM, {LSL #N}. Operands: rd, imm, shift.

pub fn mrs<T0, T1>(&mut self, rd: T0, sysreg: T1)

where Self: MrsEmitter<T0, T1>,

Emits the MRS instruction. Assembly forms: MRS XD, #SYSREG. Operands: rd, sysreg.

pub fn msr<T0, T1>(&mut self, sysreg_or_pstatefield: T0, rs_or_imm: T1)

where Self: MsrEmitter<T0, T1>,

Emits the MSR instruction. Assembly forms: MSR #SYSREG, XS; MSR #PSTATEFIELD, #IMM. Operands: sysreg_or_pstatefield, rs_or_imm.

pub fn msub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: MsubEmitter<T0, T1, T2, T3>,

Emits the MSUB instruction. Assembly forms: MSUB WD, WN, WM, WA; MSUB XD, XN, XM, XA. Operands: rd, rn, rm, operand_4.

pub fn mul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: MulEmitter<T0, T1, T2>,

Emits the MUL instruction. Assembly forms: MUL WD, WN, WM; MUL XD, XN, XM; MUL VD.T, VN.T, VM.T; MUL VD.T, VN.T, VM.T (and related forms). Operands: rd, rn, rm.

pub fn mvn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: MvnEmitter<T0, T1>,

Emits the MVN instruction. Assembly forms: MVN WD, WN, {SOP #N}; MVN XD, XN, {SOP #N}; NOT|MVN VD.8B, VN.8B; NOT|MVN VD.16B, VN.16B. Operands: rd, rn.

pub fn mvn_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: Mvn3Emitter<T0, T1, T2>,

Emits the MVN_3 instruction. Assembly forms: MVN WD, WN, {SOP #N}; MVN XD, XN, {SOP #N}; NOT|MVN VD.8B, VN.8B; NOT|MVN VD.16B, VN.16B. Operands: rd, rn, shift.

pub fn mvn_<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Mvn_Emitter<T0, T1>,

Emits the MVN_ instruction. Assembly forms: MVN WD, WN, {SOP #N}; MVN XD, XN, {SOP #N}; NOT|MVN VD.8B, VN.8B; NOT|MVN VD.16B, VN.16B. Operands: rd, rn.

pub fn mvn__3<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: Mvn_3Emitter<T0, T1, T2>,

Emits the MVN__3 instruction. Assembly forms: MVN WD, WN, {SOP #N}; MVN XD, XN, {SOP #N}; NOT|MVN VD.8B, VN.8B; NOT|MVN VD.16B, VN.16B. Operands: rd, rn, shift.

pub fn neg<T0, T1>(&mut self, rd: T0, rm_or_rn: T1)

where Self: NegEmitter<T0, T1>,

Emits the NEG instruction. Assembly forms: NEG WD, WM, {LSL|LSR|ASR #N}; NEG XD, XM, {LSL|LSR|ASR #N}; NEG DD, DN; NEG VD.T, VN.T (and related forms). Operands: rd, rm_or_rn.

pub fn neg_3<T0, T1, T2>(&mut self, rd: T0, rm: T1, shift: T2)

where Self: Neg3Emitter<T0, T1, T2>,

Emits the NEG_3 instruction. Assembly forms: NEG WD, WM, {LSL|LSR|ASR #N}; NEG XD, XM, {LSL|LSR|ASR #N}; NEG DD, DN; NEG VD.T, VN.T (and related forms). Operands: rd, rm, shift.

pub fn negs<T0, T1>(&mut self, rd: T0, rm: T1)

where Self: NegsEmitter<T0, T1>,

Emits the NEGS instruction. Assembly forms: NEGS WD, WM, {LSL|LSR|ASR #N}; NEGS XD, XM, {LSL|LSR|ASR #N}. Operands: rd, rm.

pub fn negs_3<T0, T1, T2>(&mut self, rd: T0, rm: T1, shift: T2)

where Self: Negs3Emitter<T0, T1, T2>,

Emits the NEGS_3 instruction. Assembly forms: NEGS WD, WM, {LSL|LSR|ASR #N}; NEGS XD, XM, {LSL|LSR|ASR #N}. Operands: rd, rm, shift.

pub fn ngc<T0, T1>(&mut self, rd: T0, rm: T1)

where Self: NgcEmitter<T0, T1>,

Emits the NGC instruction. Assembly forms: NGC WD, WM; NGC XD, XM. Operands: rd, rm.

pub fn ngcs<T0, T1>(&mut self, rd: T0, rm: T1)

where Self: NgcsEmitter<T0, T1>,

Emits the NGCS instruction. Assembly forms: NGCS WD, WM; NGCS XD, XM. Operands: rd, rm.

pub fn orn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: OrnEmitter<T0, T1, T2>,

Emits the ORN instruction. Assembly forms: ORN WD, WN, WM, {SOP #N}; ORN XD, XN, XM, {SOP #N}; ORN VD.8B, VN.8B, VM.8B; ORN VD.16B, VN.16B, VM.16B. Operands: rd, rn, rm.

pub fn orn_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Orn4Emitter<T0, T1, T2, T3>,

Emits the ORN_4 instruction. Assembly forms: ORN WD, WN, WM, {SOP #N}; ORN XD, XN, XM, {SOP #N}; ORN VD.8B, VN.8B, VM.8B; ORN VD.16B, VN.16B, VM.16B. Operands: rd, rn, rm, shift.

pub fn orr<T0, T1, T2>( &mut self, rd: T0, rn_or_imm: T1, rm_or_log_imm_or_shift: T2, )

where Self: OrrEmitter<T0, T1, T2>,

Emits the ORR instruction. Assembly forms: ORR WD, WN, WM, {SOP #N}; ORR XD, XN, XM, {SOP #N}; ORR WD|WSP, WN, #LOG_IMM; ORR XD|SP, XN, #LOG_IMM (and related forms). Operands: rd, rn_or_imm, rm_or_log_imm_or_shift.

pub fn orr_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, shift: T3)

where Self: Orr4Emitter<T0, T1, T2, T3>,

Emits the ORR_4 instruction. Assembly forms: ORR WD, WN, WM, {SOP #N}; ORR XD, XN, XM, {SOP #N}; ORR WD|WSP, WN, #LOG_IMM; ORR XD|SP, XN, #LOG_IMM (and related forms). Operands: rd, rn, rm, shift.

pub fn rbit<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: RbitEmitter<T0, T1>,

Emits the RBIT instruction. Assembly forms: RBIT WD, WN; RBIT XD, XN; RBIT VD.8B, VN.8B; RBIT VD.16B, VN.16B. Operands: rd, rn.

pub fn ret<T0>(&mut self, rn: T0)

where Self: RetEmitter<T0>,

Emits the RET instruction. Assembly forms: RET XN. Operands: rn.

pub fn rev<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: RevEmitter<T0, T1>,

Emits the REV instruction. Assembly forms: REV WD, WN; REV|REV64 XD, XN. Operands: rd, rn.

pub fn rev16<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Rev16Emitter<T0, T1>,

Emits the REV16 instruction. Assembly forms: REV16 WD, WN; REV16 XD, XN; REV16 VD.8B, VN.8B; REV16 VD.16B, VN.16B. Operands: rd, rn.

pub fn rev32<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Rev32Emitter<T0, T1>,

Emits the REV32 instruction. Assembly forms: REV32 XD, XN; REV32 VD.T, VN.T; REV32 VD.T, VN.T. Operands: rd, rn.

pub fn rev64<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Rev64Emitter<T0, T1>,

Emits the REV64 instruction. Assembly forms: REV|REV64 XD, XN; REV64 VD.T, VN.T; REV64 VD.T, VN.T. Operands: rd, rn.

pub fn ror<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: RorEmitter<T0, T1, T2>,

Emits the ROR instruction. Assembly forms: ROR|RORV WD, WN, WM; ROR|RORV XD, XN, XM; ROR WD, WN, #N; ROR XD, XN, #N. Operands: rd, rn, rm_or_shift.

pub fn rorv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: RorvEmitter<T0, T1, T2>,

Emits the RORV instruction. Assembly forms: ROR|RORV WD, WN, WM; ROR|RORV XD, XN, XM. Operands: rd, rn, rm.

pub fn sbc<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SbcEmitter<T0, T1, T2>,

Emits the SBC instruction. Assembly forms: SBC WD, WN, WM; SBC XD, XN, XM. Operands: rd, rn, rm.

pub fn sbcs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SbcsEmitter<T0, T1, T2>,

Emits the SBCS instruction. Assembly forms: SBCS WD, WN, WM; SBCS XD, XN, XM. Operands: rd, rn, rm.

pub fn sbfiz<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: SbfizEmitter<T0, T1, T2, T3>,

Emits the SBFIZ instruction. Assembly forms: SBFIZ WD, WN, #LSB, #WIDTH; SBFIZ XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn sbfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)

where Self: SbfmEmitter<T0, T1, T2, T3>,

Emits the SBFM instruction. Assembly forms: SBFM WD, WN, #IMMR, #IMMS; SBFM XD, XN, #IMMR, #IMMS. Operands: rd, rn, imm, imm_2.

pub fn sbfx<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: SbfxEmitter<T0, T1, T2, T3>,

Emits the SBFX instruction. Assembly forms: SBFX WD, WN, #LSB, #WIDTH; SBFX XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn sdiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SdivEmitter<T0, T1, T2>,

Emits the SDIV instruction. Assembly forms: SDIV WD, WN, WM; SDIV XD, XN, XM. Operands: rd, rn, rm.

pub fn smaddl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: SmaddlEmitter<T0, T1, T2, T3>,

Emits the SMADDL instruction. Assembly forms: SMADDL XD, WN, WM, XA. Operands: rd, rn, rm, operand_4.

pub fn smc<T0>(&mut self, imm: T0)

where Self: SmcEmitter<T0>,

Emits the SMC instruction. Assembly forms: SMC #IMMZ. Operands: imm.

pub fn smnegl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SmneglEmitter<T0, T1, T2>,

Emits the SMNEGL instruction. Assembly forms: SMNEGL XD, WN, WM. Operands: rd, rn, rm.

pub fn smsubl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: SmsublEmitter<T0, T1, T2, T3>,

Emits the SMSUBL instruction. Assembly forms: SMSUBL XD, WN, WM, XA. Operands: rd, rn, rm, operand_4.

pub fn smulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SmulhEmitter<T0, T1, T2>,

Emits the SMULH instruction. Assembly forms: SMULH XD, XN, XM. Operands: rd, rn, rm.

pub fn smull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SmullEmitter<T0, T1, T2>,

Emits the SMULL instruction. Assembly forms: SMULL XD, WN, WM; SMULL VD.TA, VN.TB, VM.TB; SMULL VD.4S, VN.4H, VM.H[#IDX]; SMULL VD.2D, VN.2S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn sub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: SubEmitter<T0, T1, T2>,

Emits the SUB instruction. Assembly forms: SUB WD, WN, WM, {LSL|LSR|ASR #N}; SUB XD, XN, XM, {LSL|LSR|ASR #N}; SUB WD|WSP, WN|WSP, WM, {EXTEND #N}; SUB XD|SP, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm.

pub fn sub_4<T0, T1, T2, T3>( &mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3, )

where Self: Sub4Emitter<T0, T1, T2, T3>,

Emits the SUB_4 instruction. Assembly forms: SUB WD, WN, WM, {LSL|LSR|ASR #N}; SUB XD, XN, XM, {LSL|LSR|ASR #N}; SUB WD|WSP, WN|WSP, WM, {EXTEND #N}; SUB XD|SP, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm, shift.

pub fn subs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: SubsEmitter<T0, T1, T2>,

Emits the SUBS instruction. Assembly forms: SUBS WD, WN, WM, {LSL|LSR|ASR #N}; SUBS XD, XN, XM, {LSL|LSR|ASR #N}; SUBS WD, WN|WSP, WM, {EXTEND #N}; SUBS XD, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm.

pub fn subs_4<T0, T1, T2, T3>( &mut self, rd: T0, rn: T1, rm_or_imm: T2, shift: T3, )

where Self: Subs4Emitter<T0, T1, T2, T3>,

Emits the SUBS_4 instruction. Assembly forms: SUBS WD, WN, WM, {LSL|LSR|ASR #N}; SUBS XD, XN, XM, {LSL|LSR|ASR #N}; SUBS WD, WN|WSP, WM, {EXTEND #N}; SUBS XD, XN|SP, RM, {EXTEND #N} (and related forms). Operands: rd, rn, rm_or_imm, shift.

pub fn svc<T0>(&mut self, imm: T0)

where Self: SvcEmitter<T0>,

Emits the SVC instruction. Assembly forms: SVC #IMMZ. Operands: imm.

pub fn sxtb<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SxtbEmitter<T0, T1>,

Emits the SXTB instruction. Assembly forms: SXTB WD, WN; SXTB XD, WN. Operands: rd, rn.

pub fn sxth<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SxthEmitter<T0, T1>,

Emits the SXTH instruction. Assembly forms: SXTH WD, WN; SXTH XD, WN. Operands: rd, rn.

pub fn sxtw<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SxtwEmitter<T0, T1>,

Emits the SXTW instruction. Assembly forms: SXTW XD, WN. Operands: rd, rn.

pub fn sys<T0, T1, T2, T3>( &mut self, system_op1: T0, cn: T1, cm: T2, system_op2: T3, )

where Self: SysEmitter<T0, T1, T2, T3>,

Emits the SYS instruction. Assembly forms: SYS #OP1, #CN, #CM, #OP2; SYS #OP1, #CN, #CM, #OP2, XT. Operands: system_op1, cn, cm, system_op2.

pub fn sys_5<T0, T1, T2, T3, T4>( &mut self, system_op1: T0, cn: T1, cm: T2, system_op2: T3, rt: T4, )

where Self: Sys5Emitter<T0, T1, T2, T3, T4>,

Emits the SYS_5 instruction. Assembly forms: SYS #OP1, #CN, #CM, #OP2; SYS #OP1, #CN, #CM, #OP2, XT. Operands: system_op1, cn, cm, system_op2, rt.

pub fn tlbi<T0, T1>(&mut self, tlbi_op: T0, rt: T1)

where Self: TlbiEmitter<T0, T1>,

Emits the TLBI instruction. Assembly forms: TLBI #TLBI_OP; TLBI #TLBI_OP, XT. Operands: tlbi_op, rt.

pub fn tst<T0, T1>(&mut self, rn: T0, rm_or_imm: T1)

where Self: TstEmitter<T0, T1>,

Emits the TST instruction. Assembly forms: TST WN, WM, {SOP #N}; TST XN, XM, {SOP #N}; TST WN, #IMM; TST XN, #IMM. Operands: rn, rm_or_imm.

pub fn tst_3<T0, T1, T2>(&mut self, rn: T0, rm: T1, shift: T2)

where Self: Tst3Emitter<T0, T1, T2>,

Emits the TST_3 instruction. Assembly forms: TST WN, WM, {SOP #N}; TST XN, XM, {SOP #N}; TST WN, #IMM; TST XN, #IMM. Operands: rn, rm, shift.

pub fn udiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UdivEmitter<T0, T1, T2>,

Emits the UDIV instruction. Assembly forms: UDIV WD, WN, WM; UDIV XD, XN, XM. Operands: rd, rn, rm.

pub fn ubfiz<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: UbfizEmitter<T0, T1, T2, T3>,

Emits the UBFIZ instruction. Assembly forms: UBFIZ WD, WN, #LSB, #WIDTH; UBFIZ XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn ubfm<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm: T2, imm_2: T3)

where Self: UbfmEmitter<T0, T1, T2, T3>,

Emits the UBFM instruction. Assembly forms: UBFM WD, WN, #IMMR, #IMMS; UBFM XD, XN, #IMMR, #IMMS. Operands: rd, rn, imm, imm_2.

pub fn ubfx<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, lsb: T2, width: T3)

where Self: UbfxEmitter<T0, T1, T2, T3>,

Emits the UBFX instruction. Assembly forms: UBFX WD, WN, #LSB, #WIDTH; UBFX XD, XN, #LSB, #WIDTH. Operands: rd, rn, lsb, width.

pub fn umaddl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: UmaddlEmitter<T0, T1, T2, T3>,

Emits the UMADDL instruction. Assembly forms: UMADDL XD, WN, WM, XA. Operands: rd, rn, rm, operand_4.

pub fn umnegl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmneglEmitter<T0, T1, T2>,

Emits the UMNEGL instruction. Assembly forms: UMNEGL XD, WN, WM. Operands: rd, rn, rm.

pub fn umsubl<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: UmsublEmitter<T0, T1, T2, T3>,

Emits the UMSUBL instruction. Assembly forms: UMSUBL XD, WN, WM, XA. Operands: rd, rn, rm, operand_4.

pub fn umull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmullEmitter<T0, T1, T2>,

Emits the UMULL instruction. Assembly forms: UMULL XD, WN, WM; UMULL VD.TA, VN.TB, VM.TB; UMULL VD.4S, VN.4H, VM.H[#IDX]; UMULL VD.2D, VN.2S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn umulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmulhEmitter<T0, T1, T2>,

Emits the UMULH instruction. Assembly forms: UMULH XD, XN, XM. Operands: rd, rn, rm.

pub fn uxtb<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UxtbEmitter<T0, T1>,

Emits the UXTB instruction. Assembly forms: UXTB WD, WN. Operands: rd, rn.

pub fn uxth<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UxthEmitter<T0, T1>,

Emits the UXTH instruction. Assembly forms: UXTH WD, WN. Operands: rd, rn.

pub fn csdb(&mut self)

where Self: CsdbEmitter,

Emits the CSDB instruction. Assembly forms: CSDB.

pub fn dcps1<T0>(&mut self, imm: T0)

where Self: Dcps1Emitter<T0>,

Emits the DCPS1 instruction. Assembly forms: DCPS1 {#IMM}. Operands: imm.

pub fn dcps2<T0>(&mut self, imm: T0)

where Self: Dcps2Emitter<T0>,

Emits the DCPS2 instruction. Assembly forms: DCPS2 {#IMM}. Operands: imm.

pub fn dcps3<T0>(&mut self, imm: T0)

where Self: Dcps3Emitter<T0>,

Emits the DCPS3 instruction. Assembly forms: DCPS3 {#IMM}. Operands: imm.

pub fn pssbb(&mut self)

where Self: PssbbEmitter,

Emits the PSSBB instruction. Assembly forms: PSSBB.

pub fn ssbb(&mut self)

where Self: SsbbEmitter,

Emits the SSBB instruction. Assembly forms: SSBB.

pub fn udf<T0>(&mut self, imm: T0)

where Self: UdfEmitter<T0>,

Emits the UDF instruction. Assembly forms: UDF #IMM. Operands: imm.

pub fn b<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_eq<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_ne<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_cs<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_hs<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_cc<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_lo<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_mi<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_pl<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_vs<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_vc<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_hi<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_ls<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_ge<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_lt<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_gt<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_le<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn b_al<T0>(&mut self, target: T0)

where Self: BEmitter<T0>,

Emits the B instruction. Assembly forms: B #RELS*4; B.<COND> #RELS*4. Operands: target.

pub fn bl<T0>(&mut self, target: T0)

where Self: BlEmitter<T0>,

Emits the BL instruction. Assembly forms: BL #RELS*4. Operands: target.

pub fn blr<T0>(&mut self, rn: T0)

where Self: BlrEmitter<T0>,

Emits the BLR instruction. Assembly forms: BLR XN. Operands: rn.

pub fn br<T0>(&mut self, rn: T0)

where Self: BrEmitter<T0>,

Emits the BR instruction. Assembly forms: BR XN. Operands: rn.

pub fn cbz<T0, T1>(&mut self, rn: T0, target: T1)

where Self: CbzEmitter<T0, T1>,

Emits the CBZ instruction. Assembly forms: CBZ WN, #RELS*4; CBZ XN, #RELS*4. Operands: rn, target.

pub fn cbnz<T0, T1>(&mut self, rn: T0, target: T1)

where Self: CbnzEmitter<T0, T1>,

Emits the CBNZ instruction. Assembly forms: CBNZ WN, #RELS*4; CBNZ XN, #RELS*4. Operands: rn, target.

pub fn tbnz<T0, T1, T2>(&mut self, rt: T0, imm: T1, target: T2)

where Self: TbnzEmitter<T0, T1, T2>,

Emits the TBNZ instruction. Assembly forms: TBNZ WT, #IMM, #RELS*4; TBNZ XT, #IMM, #RELS*4. Operands: rt, imm, target.

pub fn tbz<T0, T1, T2>(&mut self, rt: T0, imm: T1, target: T2)

where Self: TbzEmitter<T0, T1, T2>,

Emits the TBZ instruction. Assembly forms: TBZ WT, #IMM, #RELS*4; TBZ XT, #IMM, #RELS*4. Operands: rt, imm, target.

pub fn cas<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasEmitter<T0, T1, T2>,

Emits the CAS instruction. Assembly forms: CAS WS, WD, [XN|SP]; CAS XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn casa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasaEmitter<T0, T1, T2>,

Emits the CASA instruction. Assembly forms: CASA WS, WD, [XN|SP]; CASA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn casab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasabEmitter<T0, T1, T2>,

Emits the CASAB instruction. Assembly forms: CASAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasahEmitter<T0, T1, T2>,

Emits the CASAH instruction. Assembly forms: CASAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasalEmitter<T0, T1, T2>,

Emits the CASAL instruction. Assembly forms: CASAL WS, WD, [XN|SP]; CASAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn casalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasalbEmitter<T0, T1, T2>,

Emits the CASALB instruction. Assembly forms: CASALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasalhEmitter<T0, T1, T2>,

Emits the CASALH instruction. Assembly forms: CASALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CasbEmitter<T0, T1, T2>,

Emits the CASB instruction. Assembly forms: CASB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn cash<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CashEmitter<T0, T1, T2>,

Emits the CASH instruction. Assembly forms: CASH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CaslEmitter<T0, T1, T2>,

Emits the CASL instruction. Assembly forms: CASL WS, WD, [XN|SP]; CASL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn caslb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CaslbEmitter<T0, T1, T2>,

Emits the CASLB instruction. Assembly forms: CASLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn caslh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: CaslhEmitter<T0, T1, T2>,

Emits the CASLH instruction. Assembly forms: CASLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn casp<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: CaspEmitter<T0, T1, T2, T3, T4>,

Emits the CASP instruction. Assembly forms: CASP 2X{WS}+, 2X{WD}+, [XN|SP]; CASP 2X{XS}+, 2X{XD}+, [XN|SP]. Operands: rd, rn, rm1, rm2, addr.

pub fn caspa<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: CaspaEmitter<T0, T1, T2, T3, T4>,

Emits the CASPA instruction. Assembly forms: CASPA 2X{WS}+, 2X{WD}+, [XN|SP]; CASPA 2X{XS}+, 2X{XD}+, [XN|SP]. Operands: rd, rn, rm1, rm2, addr.

pub fn caspal<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: CaspalEmitter<T0, T1, T2, T3, T4>,

Emits the CASPAL instruction. Assembly forms: CASPAL 2X{WS}+, 2X{WD}+, [XN|SP]; CASPAL 2X{XS}+, 2X{XD}+, [XN|SP]. Operands: rd, rn, rm1, rm2, addr.

pub fn caspl<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: CasplEmitter<T0, T1, T2, T3, T4>,

Emits the CASPL instruction. Assembly forms: CASPL 2X{WS}+, 2X{WD}+, [XN|SP]; CASPL 2X{XS}+, 2X{XD}+, [XN|SP]. Operands: rd, rn, rm1, rm2, addr.

pub fn ldadd<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddEmitter<T0, T1, T2>,

Emits the LDADD instruction. Assembly forms: LDADD WS, WD, [XN|SP]; LDADD XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldadda<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddaEmitter<T0, T1, T2>,

Emits the LDADDA instruction. Assembly forms: LDADDA WS, WD, [XN|SP]; LDADDA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddabEmitter<T0, T1, T2>,

Emits the LDADDAB instruction. Assembly forms: LDADDAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddahEmitter<T0, T1, T2>,

Emits the LDADDAH instruction. Assembly forms: LDADDAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddalEmitter<T0, T1, T2>,

Emits the LDADDAL instruction. Assembly forms: LDADDAL WS, WD, [XN|SP]; LDADDAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddalbEmitter<T0, T1, T2>,

Emits the LDADDALB instruction. Assembly forms: LDADDALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddalhEmitter<T0, T1, T2>,

Emits the LDADDALH instruction. Assembly forms: LDADDALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddbEmitter<T0, T1, T2>,

Emits the LDADDB instruction. Assembly forms: LDADDB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddhEmitter<T0, T1, T2>,

Emits the LDADDH instruction. Assembly forms: LDADDH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddlEmitter<T0, T1, T2>,

Emits the LDADDL instruction. Assembly forms: LDADDL WS, WD, [XN|SP]; LDADDL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddlbEmitter<T0, T1, T2>,

Emits the LDADDLB instruction. Assembly forms: LDADDLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldaddlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdaddlhEmitter<T0, T1, T2>,

Emits the LDADDLH instruction. Assembly forms: LDADDLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldar<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdarEmitter<T0, T1>,

Emits the LDAR instruction. Assembly forms: LDAR WD, [XN|SP]; LDAR XD, [XN|SP]. Operands: rd, addr.

pub fn ldarb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdarbEmitter<T0, T1>,

Emits the LDARB instruction. Assembly forms: LDARB WD, [XN|SP]. Operands: rd, addr.

pub fn ldarh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdarhEmitter<T0, T1>,

Emits the LDARH instruction. Assembly forms: LDARH WD, [XN|SP]. Operands: rd, addr.

pub fn ldaxr<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdaxrEmitter<T0, T1>,

Emits the LDAXR instruction. Assembly forms: LDAXR WD, [XN|SP]; LDAXR XD, [XN|SP]. Operands: rd, addr.

pub fn ldaxrb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdaxrbEmitter<T0, T1>,

Emits the LDAXRB instruction. Assembly forms: LDAXRB WD, [XN|SP]. Operands: rd, addr.

pub fn ldaxrh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdaxrhEmitter<T0, T1>,

Emits the LDAXRH instruction. Assembly forms: LDAXRH XD, [XN|SP]. Operands: rd, addr.

pub fn ldclr<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrEmitter<T0, T1, T2>,

Emits the LDCLR instruction. Assembly forms: LDCLR WS, WD, [XN|SP]; LDCLR XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclra<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclraEmitter<T0, T1, T2>,

Emits the LDCLRA instruction. Assembly forms: LDCLRA WS, WD, [XN|SP]; LDCLRA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrabEmitter<T0, T1, T2>,

Emits the LDCLRAB instruction. Assembly forms: LDCLRAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrahEmitter<T0, T1, T2>,

Emits the LDCLRAH instruction. Assembly forms: LDCLRAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclral<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclralEmitter<T0, T1, T2>,

Emits the LDCLRAL instruction. Assembly forms: LDCLRAL WS, WD, [XN|SP]; LDCLRAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclralb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclralbEmitter<T0, T1, T2>,

Emits the LDCLRALB instruction. Assembly forms: LDCLRALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclralh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclralhEmitter<T0, T1, T2>,

Emits the LDCLRALH instruction. Assembly forms: LDCLRALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrbEmitter<T0, T1, T2>,

Emits the LDCLRB instruction. Assembly forms: LDCLRB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrhEmitter<T0, T1, T2>,

Emits the LDCLRH instruction. Assembly forms: LDCLRH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrlEmitter<T0, T1, T2>,

Emits the LDCLRL instruction. Assembly forms: LDCLRL WS, WD, [XN|SP]; LDCLRL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrlbEmitter<T0, T1, T2>,

Emits the LDCLRLB instruction. Assembly forms: LDCLRLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldclrlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdclrlhEmitter<T0, T1, T2>,

Emits the LDCLRLH instruction. Assembly forms: LDCLRLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeor<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorEmitter<T0, T1, T2>,

Emits the LDEOR instruction. Assembly forms: LDEOR WS, WD, [XN|SP]; LDEOR XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeora<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeoraEmitter<T0, T1, T2>,

Emits the LDEORA instruction. Assembly forms: LDEORA WS, WD, [XN|SP]; LDEORA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorabEmitter<T0, T1, T2>,

Emits the LDEORAB instruction. Assembly forms: LDEORAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorahEmitter<T0, T1, T2>,

Emits the LDEORAH instruction. Assembly forms: LDEORAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeoral<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeoralEmitter<T0, T1, T2>,

Emits the LDEORAL instruction. Assembly forms: LDEORAL WS, WD, [XN|SP]; LDEORAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeoralb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeoralbEmitter<T0, T1, T2>,

Emits the LDEORALB instruction. Assembly forms: LDEORALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeoralh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeoralhEmitter<T0, T1, T2>,

Emits the LDEORALH instruction. Assembly forms: LDEORALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorbEmitter<T0, T1, T2>,

Emits the LDEORB instruction. Assembly forms: LDEORB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorhEmitter<T0, T1, T2>,

Emits the LDEORH instruction. Assembly forms: LDEORH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorlEmitter<T0, T1, T2>,

Emits the LDEORL instruction. Assembly forms: LDEORL WS, WD, [XN|SP]; LDEORL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorlbEmitter<T0, T1, T2>,

Emits the LDEORLB instruction. Assembly forms: LDEORLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldeorlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdeorlhEmitter<T0, T1, T2>,

Emits the LDEORLH instruction. Assembly forms: LDEORLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldlar<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdlarEmitter<T0, T1>,

Emits the LDLAR instruction. Assembly forms: LDLAR WD, [XN|SP]; LDLAR XD, [XN|SP]. Operands: rd, addr.

pub fn ldlarb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdlarbEmitter<T0, T1>,

Emits the LDLARB instruction. Assembly forms: LDLARB WD, [XN|SP]. Operands: rd, addr.

pub fn ldlarh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdlarhEmitter<T0, T1>,

Emits the LDLARH instruction. Assembly forms: LDLARH WD, [XN|SP]. Operands: rd, addr.

pub fn ldnp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)

where Self: LdnpEmitter<T0, T1, T2>,

Emits the LDNP instruction. Assembly forms: LDNP WD, WD2, [XN|SP, #OFFS*4]; LDNP XD, XD2, [XN|SP, #OFFS*8]; LDNP SD, SD2, [XN|SP, #OFFS*4]; LDNP DD, DD2, [XN|SP, #OFFS*8] (and related forms). Operands: rd, rd2, addr.

pub fn ldp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)

where Self: LdpEmitter<T0, T1, T2>,

Emits the LDP instruction. Assembly forms: LDP WD, WD2, [XN|SP, #OFFS*4]{@}{!}; LDP XD, XD2, [XN|SP, #OFFS*8]{@}{!}; LDP SD, SD2, [XN|SP, #OFFS*4]{@}{!}; LDP DD, DD2, [XN|SP, #OFFS*8]{@}{!} (and related forms). Operands: rd, rd2, addr.

pub fn ldpsw<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)

where Self: LdpswEmitter<T0, T1, T2>,

Emits the LDPSW instruction. Assembly forms: LDPSW XD, XD2, [XN|SP, #OFFS*4]{@}{!}. Operands: rd, rd2, addr.

pub fn ldr<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrEmitter<T0, T1>,

Emits the LDR instruction. Assembly forms: LDR WD, [XN|SP, #OFFZ*4]; LDR XD, [XN|SP, #OFFZ*8]; LDR WD, [XN|SP, #OFFS*4]@; LDR XD, [XN|SP, #OFFS*8]@ (and related forms). Operands: rd, addr.

pub fn ldrb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrbEmitter<T0, T1>,

Emits the LDRB instruction. Assembly forms: LDRB WD, [XN|SP, #OFFZ]; LDRB WD, [XN|SP, #OFFS]@; LDRB WD, [XN|SP, #OFFS]!; LDRB WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]. Operands: rd, addr.

pub fn ldrh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrhEmitter<T0, T1>,

Emits the LDRH instruction. Assembly forms: LDRH WD, [XN|SP, #OFFZ*2]; LDRH WD, [XN|SP, #OFFS*2]@; LDRH WD, [XN|SP, #OFFS*2]!; LDRH WD, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]. Operands: rd, addr.

pub fn ldrsb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrsbEmitter<T0, T1>,

Emits the LDRSB instruction. Assembly forms: LDRSB WD, [XN|SP, #OFFZ]; LDRSB XD, [XN|SP, #OFFZ]; LDRSB WD, [XN|SP, #OFFS]@; LDRSB XD, [XN|SP, #OFFS]@ (and related forms). Operands: rd, addr.

pub fn ldrsh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrshEmitter<T0, T1>,

Emits the LDRSH instruction. Assembly forms: LDRSH WD, [XN|SP, #OFFZ*2]; LDRSH XD, [XN|SP, #OFFZ*2]; LDRSH WD, [XN|SP, #OFFS*2]@; LDRSH XD, [XN|SP, #OFFS*2]@ (and related forms). Operands: rd, addr.

pub fn ldrsw<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrswEmitter<T0, T1>,

Emits the LDRSW instruction. Assembly forms: LDRSW XD, [XN|SP, #OFFZ*4]; LDRSW XD, [XN|SP, #OFFS*4]@; LDRSW XD, [XN|SP, #OFFS*4]!; LDRSW XD, [PC, #OFFS*4] (and related forms). Operands: rd, addr.

pub fn ldset<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetEmitter<T0, T1, T2>,

Emits the LDSET instruction. Assembly forms: LDSET WS, WD, [XN|SP]; LDSET XS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldseta<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetaEmitter<T0, T1, T2>,

Emits the LDSETA instruction. Assembly forms: LDSETA WS, WD, [XN|SP]; LDSETA XS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetabEmitter<T0, T1, T2>,

Emits the LDSETAB instruction. Assembly forms: LDSETAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetahEmitter<T0, T1, T2>,

Emits the LDSETAH instruction. Assembly forms: LDSETAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetalEmitter<T0, T1, T2>,

Emits the LDSETAL instruction. Assembly forms: LDSETAL WS, WD, [XN|SP]; LDSETAL XS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetalbEmitter<T0, T1, T2>,

Emits the LDSETALB instruction. Assembly forms: LDSETALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetalhEmitter<T0, T1, T2>,

Emits the LDSETALH instruction. Assembly forms: LDSETALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetbEmitter<T0, T1, T2>,

Emits the LDSETB instruction. Assembly forms: LDSETB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldseth<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsethEmitter<T0, T1, T2>,

Emits the LDSETH instruction. Assembly forms: LDSETH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetlEmitter<T0, T1, T2>,

Emits the LDSETL instruction. Assembly forms: LDSETL WS, WD, [XN|SP]; LDSETL XS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetlbEmitter<T0, T1, T2>,

Emits the LDSETLB instruction. Assembly forms: LDSETLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsetlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsetlhEmitter<T0, T1, T2>,

Emits the LDSETLH instruction. Assembly forms: LDSETLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmax<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxEmitter<T0, T1, T2>,

Emits the LDSMAX instruction. Assembly forms: LDSMAX WS, WD, [XN|SP]; LDSMAX XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxaEmitter<T0, T1, T2>,

Emits the LDSMAXA instruction. Assembly forms: LDSMAXA WS, WD, [XN|SP]; LDSMAXA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxabEmitter<T0, T1, T2>,

Emits the LDSMAXAB instruction. Assembly forms: LDSMAXAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxahEmitter<T0, T1, T2>,

Emits the LDSMAXAH instruction. Assembly forms: LDSMAXAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxalEmitter<T0, T1, T2>,

Emits the LDSMAXAL instruction. Assembly forms: LDSMAXAL WS, WD, [XN|SP]; LDSMAXAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxalbEmitter<T0, T1, T2>,

Emits the LDSMAXALB instruction. Assembly forms: LDSMAXALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxalhEmitter<T0, T1, T2>,

Emits the LDSMAXALH instruction. Assembly forms: LDSMAXALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxbEmitter<T0, T1, T2>,

Emits the LDSMAXB instruction. Assembly forms: LDSMAXB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxhEmitter<T0, T1, T2>,

Emits the LDSMAXH instruction. Assembly forms: LDSMAXH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxlEmitter<T0, T1, T2>,

Emits the LDSMAXL instruction. Assembly forms: LDSMAXL WS, WD, [XN|SP]; LDSMAXL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxlbEmitter<T0, T1, T2>,

Emits the LDSMAXLB instruction. Assembly forms: LDSMAXLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmaxlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsmaxlhEmitter<T0, T1, T2>,

Emits the LDSMAXLH instruction. Assembly forms: LDSMAXLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmin<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminEmitter<T0, T1, T2>,

Emits the LDSMIN instruction. Assembly forms: LDSMIN WS, WD, [XN|SP]; LDSMIN XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsmina<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminaEmitter<T0, T1, T2>,

Emits the LDSMINA instruction. Assembly forms: LDSMINA WS, WD, [XN|SP]; LDSMINA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminabEmitter<T0, T1, T2>,

Emits the LDSMINAB instruction. Assembly forms: LDSMINAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminahEmitter<T0, T1, T2>,

Emits the LDSMINAH instruction. Assembly forms: LDSMINAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminalEmitter<T0, T1, T2>,

Emits the LDSMINAL instruction. Assembly forms: LDSMINAL WS, WD, [XN|SP]; LDSMINAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminalbEmitter<T0, T1, T2>,

Emits the LDSMINALB instruction. Assembly forms: LDSMINALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminalhEmitter<T0, T1, T2>,

Emits the LDSMINALH instruction. Assembly forms: LDSMINALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminbEmitter<T0, T1, T2>,

Emits the LDSMINB instruction. Assembly forms: LDSMINB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminhEmitter<T0, T1, T2>,

Emits the LDSMINH instruction. Assembly forms: LDSMINH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminlEmitter<T0, T1, T2>,

Emits the LDSMINL instruction. Assembly forms: LDSMINL WS, WD, [XN|SP]; LDSMINL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminlbEmitter<T0, T1, T2>,

Emits the LDSMINLB instruction. Assembly forms: LDSMINLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldsminlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdsminlhEmitter<T0, T1, T2>,

Emits the LDSMINLH instruction. Assembly forms: LDSMINLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldtr<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrEmitter<T0, T1>,

Emits the LDTR instruction. Assembly forms: LDTR WD, [XN|SP, #OFFS]; LDTR XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldtrb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrbEmitter<T0, T1>,

Emits the LDTRB instruction. Assembly forms: LDTRB WD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldtrh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrhEmitter<T0, T1>,

Emits the LDTRH instruction. Assembly forms: LDTRH WD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldtrsb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrsbEmitter<T0, T1>,

Emits the LDTRSB instruction. Assembly forms: LDTRSB WD, [XN|SP, #OFFS]; LDTRSB XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldtrsh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrshEmitter<T0, T1>,

Emits the LDTRSH instruction. Assembly forms: LDTRSH WD, [XN|SP, #OFFS]; LDTRSH XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldtrsw<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdtrswEmitter<T0, T1>,

Emits the LDTRSW instruction. Assembly forms: LDTRSW XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldumax<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxEmitter<T0, T1, T2>,

Emits the LDUMAX instruction. Assembly forms: LDUMAX WS, WD, [XN|SP]; LDUMAX XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxaEmitter<T0, T1, T2>,

Emits the LDUMAXA instruction. Assembly forms: LDUMAXA WS, WD, [XN|SP]; LDUMAXA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxabEmitter<T0, T1, T2>,

Emits the LDUMAXAB instruction. Assembly forms: LDUMAXAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxahEmitter<T0, T1, T2>,

Emits the LDUMAXAH instruction. Assembly forms: LDUMAXAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxalEmitter<T0, T1, T2>,

Emits the LDUMAXAL instruction. Assembly forms: LDUMAXAL WS, WD, [XN|SP]; LDUMAXAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxalbEmitter<T0, T1, T2>,

Emits the LDUMAXALB instruction. Assembly forms: LDUMAXALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxalhEmitter<T0, T1, T2>,

Emits the LDUMAXALH instruction. Assembly forms: LDUMAXALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxbEmitter<T0, T1, T2>,

Emits the LDUMAXB instruction. Assembly forms: LDUMAXB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxhEmitter<T0, T1, T2>,

Emits the LDUMAXH instruction. Assembly forms: LDUMAXH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxlEmitter<T0, T1, T2>,

Emits the LDUMAXL instruction. Assembly forms: LDUMAXL WS, WD, [XN|SP]; LDUMAXL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxlbEmitter<T0, T1, T2>,

Emits the LDUMAXLB instruction. Assembly forms: LDUMAXLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumaxlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LdumaxlhEmitter<T0, T1, T2>,

Emits the LDUMAXLH instruction. Assembly forms: LDUMAXLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumin<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminEmitter<T0, T1, T2>,

Emits the LDUMIN instruction. Assembly forms: LDUMIN WS, WD, [XN|SP]; LDUMIN XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldumina<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminaEmitter<T0, T1, T2>,

Emits the LDUMINA instruction. Assembly forms: LDUMINA WS, WD, [XN|SP]; LDUMINA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminabEmitter<T0, T1, T2>,

Emits the LDUMINAB instruction. Assembly forms: LDUMINAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminahEmitter<T0, T1, T2>,

Emits the LDUMINAH instruction. Assembly forms: LDUMINAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminalEmitter<T0, T1, T2>,

Emits the LDUMINAL instruction. Assembly forms: LDUMINAL WS, WD, [XN|SP]; LDUMINAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminalbEmitter<T0, T1, T2>,

Emits the LDUMINALB instruction. Assembly forms: LDUMINALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminalhEmitter<T0, T1, T2>,

Emits the LDUMINALH instruction. Assembly forms: LDUMINALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminbEmitter<T0, T1, T2>,

Emits the LDUMINB instruction. Assembly forms: LDUMINB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminhEmitter<T0, T1, T2>,

Emits the LDUMINH instruction. Assembly forms: LDUMINH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminlEmitter<T0, T1, T2>,

Emits the LDUMINL instruction. Assembly forms: LDUMINL WS, WD, [XN|SP]; LDUMINL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminlb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminlbEmitter<T0, T1, T2>,

Emits the LDUMINLB instruction. Assembly forms: LDUMINLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn lduminlh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: LduminlhEmitter<T0, T1, T2>,

Emits the LDUMINLH instruction. Assembly forms: LDUMINLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn ldur<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdurEmitter<T0, T1>,

Emits the LDUR instruction. Assembly forms: LDUR WD, [XN|SP, #OFFS]; LDUR XD, [XN|SP, #OFFS]; LDUR BD, [XN|SP, #OFFS]; LDUR HD, [XN|SP, #OFFS] (and related forms). Operands: rd, addr.

pub fn ldurb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdurbEmitter<T0, T1>,

Emits the LDURB instruction. Assembly forms: LDURB WD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldurh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdurhEmitter<T0, T1>,

Emits the LDURH instruction. Assembly forms: LDURH WD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldursb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdursbEmitter<T0, T1>,

Emits the LDURSB instruction. Assembly forms: LDURSB WD, [XN|SP, #OFFS]; LDURSB XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldursh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdurshEmitter<T0, T1>,

Emits the LDURSH instruction. Assembly forms: LDURSH WD, [XN|SP, #OFFS]; LDURSH XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldursw<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdurswEmitter<T0, T1>,

Emits the LDURSW instruction. Assembly forms: LDURSW XD, [XN|SP, #OFFS]. Operands: rd, addr.

pub fn ldxp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)

where Self: LdxpEmitter<T0, T1, T2>,

Emits the LDXP instruction. Assembly forms: LDXP WD, WD2, [XN|SP, #OFFS*4]; LDXP XD, XD2, [XN|SP, #OFFS*8]. Operands: rd, rd2, addr.

pub fn ldaxp<T0, T1, T2>(&mut self, rd: T0, rd2: T1, addr: T2)

where Self: LdaxpEmitter<T0, T1, T2>,

Emits the LDAXP instruction. Assembly forms: LDAXP WD, WD2, [XN|SP]; LDAXP XD, XD2, [XN|SP]. Operands: rd, rd2, addr.

pub fn ldxr<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdxrEmitter<T0, T1>,

Emits the LDXR instruction. Assembly forms: LDXR WD, [XN|SP]; LDXR XD, [XN|SP]. Operands: rd, addr.

pub fn ldxrb<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdxrbEmitter<T0, T1>,

Emits the LDXRB instruction. Assembly forms: LDXRB WD, [XN|SP]. Operands: rd, addr.

pub fn ldxrh<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdxrhEmitter<T0, T1>,

Emits the LDXRH instruction. Assembly forms: LDXRH WD, [XN|SP]. Operands: rd, addr.

pub fn prfm<T0, T1>(&mut self, prf_op: T0, addr: T1)

where Self: PrfmEmitter<T0, T1>,

Emits the PRFM instruction. Assembly forms: PRFM #PRF_OP, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N*8}]; PRFM #PRF_OP, [XN|SP, #OFFZ]; PRFM #PRF_OP, [PC, #OFFS*4]. Operands: prf_op, addr.

pub fn stadd<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddEmitter<T0, T1>,

Emits the STADD instruction. Assembly forms: STADD WS, [XN|SP]; STADD XS, [XN|SP]. Operands: rs, addr.

pub fn staddb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddbEmitter<T0, T1>,

Emits the STADDB instruction. Assembly forms: STADDB WS, [XN|SP]. Operands: rs, addr.

pub fn staddh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddhEmitter<T0, T1>,

Emits the STADDH instruction. Assembly forms: STADDH WS, [XN|SP]. Operands: rs, addr.

pub fn staddl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddlEmitter<T0, T1>,

Emits the STADDL instruction. Assembly forms: STADDL WS, [XN|SP]; STADDL XS, [XN|SP]. Operands: rs, addr.

pub fn staddlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddlbEmitter<T0, T1>,

Emits the STADDLB instruction. Assembly forms: STADDLB WS, [XN|SP]. Operands: rs, addr.

pub fn staddlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StaddlhEmitter<T0, T1>,

Emits the STADDLH instruction. Assembly forms: STADDLH WS, [XN|SP]. Operands: rs, addr.

pub fn stclr<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrEmitter<T0, T1>,

Emits the STCLR instruction. Assembly forms: STCLR WS, [XN|SP]; STCLR XS, [XN|SP]. Operands: rs, addr.

pub fn stclrb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrbEmitter<T0, T1>,

Emits the STCLRB instruction. Assembly forms: STCLRB WS, [XN|SP]. Operands: rs, addr.

pub fn stclrh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrhEmitter<T0, T1>,

Emits the STCLRH instruction. Assembly forms: STCLRH WS, [XN|SP]. Operands: rs, addr.

pub fn stclrl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrlEmitter<T0, T1>,

Emits the STCLRL instruction. Assembly forms: STCLRL WS, [XN|SP]; STCLRL XS, [XN|SP]. Operands: rs, addr.

pub fn stclrlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrlbEmitter<T0, T1>,

Emits the STCLRLB instruction. Assembly forms: STCLRLB WS, [XN|SP]. Operands: rs, addr.

pub fn stclrlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StclrlhEmitter<T0, T1>,

Emits the STCLRLH instruction. Assembly forms: STCLRLH WS, [XN|SP]. Operands: rs, addr.

pub fn steor<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorEmitter<T0, T1>,

Emits the STEOR instruction. Assembly forms: STEOR WS, [XN|SP]; STEOR XS, [XN|SP]. Operands: rs, addr.

pub fn steorb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorbEmitter<T0, T1>,

Emits the STEORB instruction. Assembly forms: STEORB WS, [XN|SP]. Operands: rs, addr.

pub fn steorh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorhEmitter<T0, T1>,

Emits the STEORH instruction. Assembly forms: STEORH WS, [XN|SP]. Operands: rs, addr.

pub fn steorl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorlEmitter<T0, T1>,

Emits the STEORL instruction. Assembly forms: STEORL WS, [XN|SP]; STEORL XS, [XN|SP]. Operands: rs, addr.

pub fn steorlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorlbEmitter<T0, T1>,

Emits the STEORLB instruction. Assembly forms: STEORLB WS, [XN|SP]. Operands: rs, addr.

pub fn steorlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SteorlhEmitter<T0, T1>,

Emits the STEORLH instruction. Assembly forms: STEORLH WS, [XN|SP]. Operands: rs, addr.

pub fn stllr<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StllrEmitter<T0, T1>,

Emits the STLLR instruction. Assembly forms: STLLR WS, [XN|SP]; STLLR XS, [XN|SP]. Operands: rs, addr.

pub fn stllrb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StllrbEmitter<T0, T1>,

Emits the STLLRB instruction. Assembly forms: STLLRB WS, [XN|SP]. Operands: rs, addr.

pub fn stllrh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StllrhEmitter<T0, T1>,

Emits the STLLRH instruction. Assembly forms: STLLRH WS, [XN|SP]. Operands: rs, addr.

pub fn stlr<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StlrEmitter<T0, T1>,

Emits the STLR instruction. Assembly forms: STLR WS, [XN|SP]; STLR XS, [XN|SP]. Operands: rs, addr.

pub fn stlrb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StlrbEmitter<T0, T1>,

Emits the STLRB instruction. Assembly forms: STLRB WS, [XN|SP]. Operands: rs, addr.

pub fn stlrh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StlrhEmitter<T0, T1>,

Emits the STLRH instruction. Assembly forms: STLRH WS, [XN|SP]. Operands: rs, addr.

pub fn stlxr<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StlxrEmitter<T0, T1, T2>,

Emits the STLXR instruction. Assembly forms: STLXR WD, WS, [XN|SP]; STLXR WD, XS, [XN|SP]. Operands: rd, rs, addr.

pub fn stlxrb<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StlxrbEmitter<T0, T1, T2>,

Emits the STLXRB instruction. Assembly forms: STLXRB WD, WS, [XN|SP]. Operands: rd, rs, addr.

pub fn stlxrh<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StlxrhEmitter<T0, T1, T2>,

Emits the STLXRH instruction. Assembly forms: STLXRH WD, XS, [XN|SP]. Operands: rd, rs, addr.

pub fn stnp<T0, T1, T2>(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2)

where Self: StnpEmitter<T0, T1, T2>,

Emits the STNP instruction. Assembly forms: STNP WS, WS2, [XN|SP, #OFFS*4]; STNP XS, XS2, [XN|SP, #OFFS*8]; STNP SD, SD2, [XN|SP, #OFFS*4]; STNP DD, DD2, [XN|SP, #OFFS*8] (and related forms). Operands: rs_or_rd, rs2_or_rd2, addr.

pub fn stp<T0, T1, T2>(&mut self, rs_or_rd: T0, rs2_or_rd2: T1, addr: T2)

where Self: StpEmitter<T0, T1, T2>,

Emits the STP instruction. Assembly forms: STP WS, WS2, [XN|SP, #OFFS*4]{@}{!}; STP XS, XS2, [XN|SP, #OFFS*8]{@}{!}; STP SD, SD2, [XN|SP, #OFFS*4]{@}{!}; STP DD, DD2, [XN|SP, #OFFS*8]{@}{!} (and related forms). Operands: rs_or_rd, rs2_or_rd2, addr.

pub fn str<T0, T1>(&mut self, rs_or_rd: T0, addr: T1)

where Self: StrEmitter<T0, T1>,

Emits the STR instruction. Assembly forms: STR WS, [XN|SP, #OFFZ*4]; STR XS, [XN|SP, #OFFZ*8]; STR WS, [XN|SP, #OFFS*4]@; STR XS, [XN|SP, #OFFS*8]@ (and related forms). Operands: rs_or_rd, addr.

pub fn strb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StrbEmitter<T0, T1>,

Emits the STRB instruction. Assembly forms: STRB WS, [XN|SP, #OFFZ]; STRB WS, [XN|SP, #OFFS]@; STRB WS, [XN|SP, #OFFS]!; STRB WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]. Operands: rs, addr.

pub fn strh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StrhEmitter<T0, T1>,

Emits the STRH instruction. Assembly forms: STRH WS, [XN|SP, #OFFZ*2]; STRH WS, [XN|SP, #OFFS*2]@; STRH WS, [XN|SP, #OFFS*2]!; STRH WS, [XN|SP, RM, {UXTW|LSL|SXTW|SXTX #N}]. Operands: rs, addr.

pub fn stset<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsetEmitter<T0, T1>,

Emits the STSET instruction. Assembly forms: STSET WS, [XN|SP]; STSET XS, [XN|SP]. Operands: rs, addr.

pub fn stsetb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsetbEmitter<T0, T1>,

Emits the STSETB instruction. Assembly forms: STSETB WS, [XN|SP]. Operands: rs, addr.

pub fn stseth<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsethEmitter<T0, T1>,

Emits the STSETH instruction. Assembly forms: STSETH WS, [XN|SP]. Operands: rs, addr.

pub fn stsetl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsetlEmitter<T0, T1>,

Emits the STSETL instruction. Assembly forms: STSETL WS, [XN|SP]; STSETL XS, [XN|SP]. Operands: rs, addr.

pub fn stsetlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsetlbEmitter<T0, T1>,

Emits the STSETLB instruction. Assembly forms: STSETLB WS, [XN|SP]. Operands: rs, addr.

pub fn stsetlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsetlhEmitter<T0, T1>,

Emits the STSETLH instruction. Assembly forms: STSETLH WS, [XN|SP]. Operands: rs, addr.

pub fn stsmax<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxEmitter<T0, T1>,

Emits the STSMAX instruction. Assembly forms: STSMAX WS, [XN|SP]; STSMAX XS, [XN|SP]. Operands: rs, addr.

pub fn stsmaxb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxbEmitter<T0, T1>,

Emits the STSMAXB instruction. Assembly forms: STSMAXB WS, [XN|SP]. Operands: rs, addr.

pub fn stsmaxh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxhEmitter<T0, T1>,

Emits the STSMAXH instruction. Assembly forms: STSMAXH WS, [XN|SP]. Operands: rs, addr.

pub fn stsmaxl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxlEmitter<T0, T1>,

Emits the STSMAXL instruction. Assembly forms: STSMAXL WS, [XN|SP]; STSMAXL XS, [XN|SP]. Operands: rs, addr.

pub fn stsmaxlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxlbEmitter<T0, T1>,

Emits the STSMAXLB instruction. Assembly forms: STSMAXLB WS, [XN|SP]. Operands: rs, addr.

pub fn stsmaxlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsmaxlhEmitter<T0, T1>,

Emits the STSMAXLH instruction. Assembly forms: STSMAXLH WS, [XN|SP]. Operands: rs, addr.

pub fn stsmin<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminEmitter<T0, T1>,

Emits the STSMIN instruction. Assembly forms: STSMIN WS, [XN|SP]; STSMIN XS, [XN|SP]. Operands: rs, addr.

pub fn stsminb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminbEmitter<T0, T1>,

Emits the STSMINB instruction. Assembly forms: STSMINB WS, [XN|SP]. Operands: rs, addr.

pub fn stsminh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminhEmitter<T0, T1>,

Emits the STSMINH instruction. Assembly forms: STSMINH WS, [XN|SP]. Operands: rs, addr.

pub fn stsminl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminlEmitter<T0, T1>,

Emits the STSMINL instruction. Assembly forms: STSMINL WS, [XN|SP]; STSMINL XS, [XN|SP]. Operands: rs, addr.

pub fn stsminlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminlbEmitter<T0, T1>,

Emits the STSMINLB instruction. Assembly forms: STSMINLB WS, [XN|SP]. Operands: rs, addr.

pub fn stsminlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StsminlhEmitter<T0, T1>,

Emits the STSMINLH instruction. Assembly forms: STSMINLH WS, [XN|SP]. Operands: rs, addr.

pub fn sttr<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SttrEmitter<T0, T1>,

Emits the STTR instruction. Assembly forms: STTR WS, [XN|SP, #OFFS]; STTR XS, [XN|SP, #OFFS]. Operands: rs, addr.

pub fn sttrb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SttrbEmitter<T0, T1>,

Emits the STTRB instruction. Assembly forms: STTRB WS, [XN|SP, #OFFS]. Operands: rs, addr.

pub fn sttrh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SttrhEmitter<T0, T1>,

Emits the STTRH instruction. Assembly forms: STTRH WS, [XN|SP, #OFFS]. Operands: rs, addr.

pub fn stumax<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxEmitter<T0, T1>,

Emits the STUMAX instruction. Assembly forms: STUMAX WS, [XN|SP]; STUMAX XS, [XN|SP]. Operands: rs, addr.

pub fn stumaxb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxbEmitter<T0, T1>,

Emits the STUMAXB instruction. Assembly forms: STUMAXB WS, [XN|SP]. Operands: rs, addr.

pub fn stumaxh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxhEmitter<T0, T1>,

Emits the STUMAXH instruction. Assembly forms: STUMAXH WS, [XN|SP]. Operands: rs, addr.

pub fn stumaxl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxlEmitter<T0, T1>,

Emits the STUMAXL instruction. Assembly forms: STUMAXL WS, [XN|SP]; STUMAXL XS, [XN|SP]. Operands: rs, addr.

pub fn stumaxlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxlbEmitter<T0, T1>,

Emits the STUMAXLB instruction. Assembly forms: STUMAXLB WS, [XN|SP]. Operands: rs, addr.

pub fn stumaxlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StumaxlhEmitter<T0, T1>,

Emits the STUMAXLH instruction. Assembly forms: STUMAXLH WS, [XN|SP]. Operands: rs, addr.

pub fn stumin<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminEmitter<T0, T1>,

Emits the STUMIN instruction. Assembly forms: STUMIN WS, [XN|SP]; STUMIN XS, [XN|SP]. Operands: rs, addr.

pub fn stuminb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminbEmitter<T0, T1>,

Emits the STUMINB instruction. Assembly forms: STUMINB WS, [XN|SP]. Operands: rs, addr.

pub fn stuminh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminhEmitter<T0, T1>,

Emits the STUMINH instruction. Assembly forms: STUMINH WS, [XN|SP]. Operands: rs, addr.

pub fn stuminl<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminlEmitter<T0, T1>,

Emits the STUMINL instruction. Assembly forms: STUMINL WS, [XN|SP]; STUMINL XS, [XN|SP]. Operands: rs, addr.

pub fn stuminlb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminlbEmitter<T0, T1>,

Emits the STUMINLB instruction. Assembly forms: STUMINLB WS, [XN|SP]. Operands: rs, addr.

pub fn stuminlh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StuminlhEmitter<T0, T1>,

Emits the STUMINLH instruction. Assembly forms: STUMINLH WS, [XN|SP]. Operands: rs, addr.

pub fn stur<T0, T1>(&mut self, rs_or_rd: T0, addr: T1)

where Self: SturEmitter<T0, T1>,

Emits the STUR instruction. Assembly forms: STUR WS, [XN|SP, #OFFS]; STUR XS, [XN|SP, #OFFS]; STUR BD, [XN|SP, #OFFS]; STUR HD, [XN|SP, #OFFS] (and related forms). Operands: rs_or_rd, addr.

pub fn sturb<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SturbEmitter<T0, T1>,

Emits the STURB instruction. Assembly forms: STURB WS, [XN|SP, #OFFS]. Operands: rs, addr.

pub fn sturh<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: SturhEmitter<T0, T1>,

Emits the STURH instruction. Assembly forms: STURH WS, [XN|SP, #OFFS]. Operands: rs, addr.

pub fn stxp<T0, T1, T2, T3>(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3)

where Self: StxpEmitter<T0, T1, T2, T3>,

Emits the STXP instruction. Assembly forms: STXP WD, WS, WS2, [XN|SP]; STXP WD, XS, XS2, [XN|SP]. Operands: rd, rs, rs2, addr.

pub fn stlxp<T0, T1, T2, T3>(&mut self, rd: T0, rs: T1, rs2: T2, addr: T3)

where Self: StlxpEmitter<T0, T1, T2, T3>,

Emits the STLXP instruction. Assembly forms: STLXP WD, WS, WS2, [XN|SP]; STLXP WD, XS, XS2, [XN|SP]. Operands: rd, rs, rs2, addr.

pub fn stxr<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StxrEmitter<T0, T1, T2>,

Emits the STXR instruction. Assembly forms: STXR WD, WS, [XN|SP]; STXR WD, XS, [XN|SP]. Operands: rd, rs, addr.

pub fn stxrb<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StxrbEmitter<T0, T1, T2>,

Emits the STXRB instruction. Assembly forms: STXRB WD, WS, [XN|SP]. Operands: rd, rs, addr.

pub fn stxrh<T0, T1, T2>(&mut self, rd: T0, rs: T1, addr: T2)

where Self: StxrhEmitter<T0, T1, T2>,

Emits the STXRH instruction. Assembly forms: STXRH WD, XS, [XN|SP]. Operands: rd, rs, addr.

pub fn swp<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpEmitter<T0, T1, T2>,

Emits the SWP instruction. Assembly forms: SWP WS, WD, [XN|SP]; SWP XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpa<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpaEmitter<T0, T1, T2>,

Emits the SWPA instruction. Assembly forms: SWPA WS, WD, [XN|SP]; SWPA XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpab<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpabEmitter<T0, T1, T2>,

Emits the SWPAB instruction. Assembly forms: SWPAB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpah<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpahEmitter<T0, T1, T2>,

Emits the SWPAH instruction. Assembly forms: SWPAH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpal<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpalEmitter<T0, T1, T2>,

Emits the SWPAL instruction. Assembly forms: SWPAL WS, WD, [XN|SP]; SWPAL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpalb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpalbEmitter<T0, T1, T2>,

Emits the SWPALB instruction. Assembly forms: SWPALB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpalh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpalhEmitter<T0, T1, T2>,

Emits the SWPALH instruction. Assembly forms: SWPALH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwpbEmitter<T0, T1, T2>,

Emits the SWPB instruction. Assembly forms: SWPB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swph<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwphEmitter<T0, T1, T2>,

Emits the SWPH instruction. Assembly forms: SWPH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swpl<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwplEmitter<T0, T1, T2>,

Emits the SWPL instruction. Assembly forms: SWPL WS, WD, [XN|SP]; SWPL XS, XD, [XN|SP]. Operands: rs, rd, addr.

pub fn swplb<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwplbEmitter<T0, T1, T2>,

Emits the SWPLB instruction. Assembly forms: SWPLB WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn swplh<T0, T1, T2>(&mut self, rs: T0, rd: T1, addr: T2)

where Self: SwplhEmitter<T0, T1, T2>,

Emits the SWPLH instruction. Assembly forms: SWPLH WS, WD, [XN|SP]. Operands: rs, rd, addr.

pub fn bti<T0>(&mut self, targets: T0)

where Self: BtiEmitter<T0>,

Emits the BTI instruction. Assembly forms: BTI {#TARGETS}. Operands: targets.

pub fn chkfeat<T0>(&mut self, rd: T0)

where Self: ChkfeatEmitter<T0>,

Emits the CHKFEAT instruction. Assembly forms: CHKFEAT. Operands: rd.

pub fn clrbhb(&mut self)

where Self: ClrbhbEmitter,

Emits the CLRBHB instruction. Assembly forms: CLRBHB.

pub fn crc32b<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32bEmitter<T0, T1, T2>,

Emits the CRC32B instruction. Assembly forms: CRC32B WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32h<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32hEmitter<T0, T1, T2>,

Emits the CRC32H instruction. Assembly forms: CRC32H WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32w<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32wEmitter<T0, T1, T2>,

Emits the CRC32W instruction. Assembly forms: CRC32W WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32x<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32xEmitter<T0, T1, T2>,

Emits the CRC32X instruction. Assembly forms: CRC32X XD, XN, XM. Operands: rd, rn, rm.

pub fn crc32cb<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32cbEmitter<T0, T1, T2>,

Emits the CRC32CB instruction. Assembly forms: CRC32CB WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32ch<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32chEmitter<T0, T1, T2>,

Emits the CRC32CH instruction. Assembly forms: CRC32CH WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32cw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32cwEmitter<T0, T1, T2>,

Emits the CRC32CW instruction. Assembly forms: CRC32CW WD, WN, WM. Operands: rd, rn, rm.

pub fn crc32cx<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Crc32cxEmitter<T0, T1, T2>,

Emits the CRC32CX instruction. Assembly forms: CRC32CX XD, XN, XM. Operands: rd, rn, rm.

pub fn abs<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AbsEmitter<T0, T1>,

Emits the ABS instruction. Assembly forms: ABS WD, WN; ABS XD, XN; ABS DD, DN; ABS VD.T, VN.T (and related forms). Operands: rd, rn.

pub fn cnt<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: CntEmitter<T0, T1>,

Emits the CNT instruction. Assembly forms: CNT WD, WN; CNT XD, XN; CNT VD.8B, VN.8B; CNT VD.16B, VN.16B. Operands: rd, rn.

pub fn ctz<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: CtzEmitter<T0, T1>,

Emits the CTZ instruction. Assembly forms: CTZ WD, WN; CTZ XD, XN. Operands: rd, rn.

pub fn smax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: SmaxEmitter<T0, T1, T2>,

Emits the SMAX instruction. Assembly forms: SMAX WD, WN, WM; SMAX XD, XN, XM; SMAX WD, WN, #IMMS; SMAX XD, XN, #IMMS (and related forms). Operands: rd, rn, rm_or_imm.

pub fn smin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: SminEmitter<T0, T1, T2>,

Emits the SMIN instruction. Assembly forms: SMIN WD, WN, WM; SMIN XD, XN, XM; SMIN WD, WN, #IMMS; SMIN XD, XN, #IMMS (and related forms). Operands: rd, rn, rm_or_imm.

pub fn umax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: UmaxEmitter<T0, T1, T2>,

Emits the UMAX instruction. Assembly forms: UMAX WD, WN, WM; UMAX XD, XN, XM; UMAX WD, WN, #IMMZ; UMAX XD, XN, #IMMZ (and related forms). Operands: rd, rn, rm_or_imm.

pub fn umin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_imm: T2)

where Self: UminEmitter<T0, T1, T2>,

Emits the UMIN instruction. Assembly forms: UMIN WD, WN, WM; UMIN XD, XN, XM; UMIN WD, WN, #IMMZ; UMIN XD, XN, #IMMZ (and related forms). Operands: rd, rn, rm_or_imm.

pub fn dgh(&mut self)

where Self: DghEmitter,

Emits the DGH instruction. Assembly forms: DGH.

pub fn cfinv(&mut self)

where Self: CfinvEmitter,

Emits the CFINV instruction. Assembly forms: CFINV.

pub fn setf8<T0>(&mut self, rn: T0)

where Self: Setf8Emitter<T0>,

Emits the SETF8 instruction. Assembly forms: SETF8 WN. Operands: rn.

pub fn setf16<T0>(&mut self, rn: T0)

where Self: Setf16Emitter<T0>,

Emits the SETF16 instruction. Assembly forms: SETF16 WN. Operands: rn.

pub fn axflag(&mut self)

where Self: AxflagEmitter,

Emits the AXFLAG instruction. Assembly forms: AXFLAG.

pub fn xaflag(&mut self)

where Self: XaflagEmitter,

Emits the XAFLAG instruction. Assembly forms: XAFLAG.

pub fn bc<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_eq<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_ne<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_cs<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_hs<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_cc<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_lo<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_mi<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_pl<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_vs<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_vc<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_hi<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_ls<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_ge<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_lt<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_gt<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_le<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn bc_al<T0>(&mut self, target: T0)

where Self: BcEmitter<T0>,

Emits the BC instruction. Assembly forms: BC.<COND> #RELS*4. Operands: target.

pub fn autda<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AutdaEmitter<T0, T1>,

Emits the AUTDA instruction. Assembly forms: AUTDA XD, XN|SP. Operands: rd, rn.

pub fn autdb<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AutdbEmitter<T0, T1>,

Emits the AUTDB instruction. Assembly forms: AUTDB XD, XN|SP. Operands: rd, rn.

pub fn autdza<T0>(&mut self, rd: T0)

where Self: AutdzaEmitter<T0>,

Emits the AUTDZA instruction. Assembly forms: AUTDZA XD. Operands: rd.

pub fn autdzb<T0>(&mut self, rd: T0)

where Self: AutdzbEmitter<T0>,

Emits the AUTDZB instruction. Assembly forms: AUTDZB XD. Operands: rd.

pub fn autia<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AutiaEmitter<T0, T1>,

Emits the AUTIA instruction. Assembly forms: AUTIA XD, XN|SP. Operands: rd, rn.

pub fn autia1716(&mut self)

where Self: Autia1716Emitter,

Emits the AUTIA1716 instruction. Assembly forms: AUTIA1716.

pub fn autiasp(&mut self)

where Self: AutiaspEmitter,

Emits the AUTIASP instruction. Assembly forms: AUTIASP.

pub fn autiaz(&mut self)

where Self: AutiazEmitter,

Emits the AUTIAZ instruction. Assembly forms: AUTIAZ.

pub fn autib<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AutibEmitter<T0, T1>,

Emits the AUTIB instruction. Assembly forms: AUTIB XD, XN|SP. Operands: rd, rn.

pub fn autib1716(&mut self)

where Self: Autib1716Emitter,

Emits the AUTIB1716 instruction. Assembly forms: AUTIB1716.

pub fn autibsp(&mut self)

where Self: AutibspEmitter,

Emits the AUTIBSP instruction. Assembly forms: AUTIBSP.

pub fn autibz(&mut self)

where Self: AutibzEmitter,

Emits the AUTIBZ instruction. Assembly forms: AUTIBZ.

pub fn autiza<T0>(&mut self, rd: T0)

where Self: AutizaEmitter<T0>,

Emits the AUTIZA instruction. Assembly forms: AUTIZA XD. Operands: rd.

pub fn autizb<T0>(&mut self, rd: T0)

where Self: AutizbEmitter<T0>,

Emits the AUTIZB instruction. Assembly forms: AUTIZB XD. Operands: rd.

pub fn gmi<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: GmiEmitter<T0, T1, T2>,

Emits the GMI instruction. Assembly forms: GMI XD, XN|SP, XM. Operands: rd, rn, rm.

pub fn cmpp<T0, T1>(&mut self, rn: T0, rm: T1)

where Self: CmppEmitter<T0, T1>,

Emits the CMPP instruction. Assembly forms: CMPP XN|SP, XM|SP. Operands: rn, rm.

pub fn addg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3)

where Self: AddgEmitter<T0, T1, T2, T3>,

Emits the ADDG instruction. Assembly forms: ADDG XD|SP, XN|SP, #IMM1, #IMM2. Operands: rd, rn, imm1, imm2.

pub fn ldg<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdgEmitter<T0, T1>,

Emits the LDG instruction. Assembly forms: LDG XD, [XN|SP, #OFFS*16]. Operands: rd, addr.

pub fn ldgm<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdgmEmitter<T0, T1>,

Emits the LDGM instruction. Assembly forms: LDGM XD, [XN|SP]. Operands: rd, addr.

pub fn ldraa<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdraaEmitter<T0, T1>,

Emits the LDRAA instruction. Assembly forms: LDRAA XD, [XN|SP, #OFFS]{!}. Operands: rd, addr.

pub fn ldrab<T0, T1>(&mut self, rd: T0, addr: T1)

where Self: LdrabEmitter<T0, T1>,

Emits the LDRAB instruction. Assembly forms: LDRAB XD, [XN|SP, #OFFS]{!}. Operands: rd, addr.

pub fn pacda<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: PacdaEmitter<T0, T1>,

Emits the PACDA instruction. Assembly forms: PACDA XD, XN|SP. Operands: rd, rn.

pub fn pacdb<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: PacdbEmitter<T0, T1>,

Emits the PACDB instruction. Assembly forms: PACDB XD, XN|SP. Operands: rd, rn.

pub fn pacdza<T0>(&mut self, rd: T0)

where Self: PacdzaEmitter<T0>,

Emits the PACDZA instruction. Assembly forms: PACDZA XD. Operands: rd.

pub fn pacdzb<T0>(&mut self, rd: T0)

where Self: PacdzbEmitter<T0>,

Emits the PACDZB instruction. Assembly forms: PACDZB XD. Operands: rd.

pub fn pacga<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: PacgaEmitter<T0, T1, T2>,

Emits the PACGA instruction. Assembly forms: PACGA XD, XN, XM|SP. Operands: rd, rn, rm.

pub fn subp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SubpEmitter<T0, T1, T2>,

Emits the SUBP instruction. Assembly forms: SUBP XD, XN|SP, XM|SP. Operands: rd, rn, rm.

pub fn subps<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SubpsEmitter<T0, T1, T2>,

Emits the SUBPS instruction. Assembly forms: SUBPS XD, XN|SP, XM|SP. Operands: rd, rn, rm.

pub fn subg<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, imm1: T2, imm2: T3)

where Self: SubgEmitter<T0, T1, T2, T3>,

Emits the SUBG instruction. Assembly forms: SUBG XD|SP, XN|SP, #IMM1, #IMM2. Operands: rd, rn, imm1, imm2.

pub fn st2g<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: St2gEmitter<T0, T1>,

Emits the ST2G instruction. Assembly forms: ST2G XS|SP, [XN|SP, #OFFS*16]{@}{!}. Operands: rs, addr.

pub fn stg<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StgEmitter<T0, T1>,

Emits the STG instruction. Assembly forms: STG XS|SP, [XN|SP, #OFFS*16]{@}{!}. Operands: rs, addr.

pub fn stgp<T0, T1, T2>(&mut self, rs: T0, rs2: T1, addr: T2)

where Self: StgpEmitter<T0, T1, T2>,

Emits the STGP instruction. Assembly forms: STGP XS, XS2, [XN|SP, #OFFS*16]{@}{!}. Operands: rs, rs2, addr.

pub fn stgm<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StgmEmitter<T0, T1>,

Emits the STGM instruction. Assembly forms: STGM XS, [XN|SP]. Operands: rs, addr.

pub fn stzg<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StzgEmitter<T0, T1>,

Emits the STZG instruction. Assembly forms: STZG XS|SP, [XN|SP, #OFFS*16]{@}{!}. Operands: rs, addr.

pub fn stz2g<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: Stz2gEmitter<T0, T1>,

Emits the STZ2G instruction. Assembly forms: STZ2G XS|SP, [XN|SP, #OFFS*16]{@}{!}. Operands: rs, addr.

pub fn stzgm<T0, T1>(&mut self, rs: T0, addr: T1)

where Self: StzgmEmitter<T0, T1>,

Emits the STZGM instruction. Assembly forms: STZGM XS, [XN|SP]. Operands: rs, addr.

pub fn xpacd<T0>(&mut self, rd: T0)

where Self: XpacdEmitter<T0>,

Emits the XPACD instruction. Assembly forms: XPACD XD. Operands: rd.

pub fn xpaci<T0>(&mut self, rd: T0)

where Self: XpaciEmitter<T0>,

Emits the XPACI instruction. Assembly forms: XPACI XD. Operands: rd.

pub fn xpaclri(&mut self)

where Self: XpaclriEmitter,

Emits the XPACLRI instruction. Assembly forms: XPACLRI XD.

pub fn hint<T0>(&mut self, imm: T0)

where Self: HintEmitter<T0>,

Emits the HINT instruction. Assembly forms: HINT #IMM. Operands: imm.

pub fn nop(&mut self)

where Self: NopEmitter,

Emits the NOP instruction. Assembly forms: NOP.

pub fn sev(&mut self)

where Self: SevEmitter,

Emits the SEV instruction. Assembly forms: SEV.

pub fn sevl(&mut self)

where Self: SevlEmitter,

Emits the SEVL instruction. Assembly forms: SEVL.

pub fn wfe(&mut self)

where Self: WfeEmitter,

Emits the WFE instruction. Assembly forms: WFE.

pub fn wfi(&mut self)

where Self: WfiEmitter,

Emits the WFI instruction. Assembly forms: WFI.

pub fn yield(&mut self)

where Self: YieldEmitter,

Emits the YIELD instruction. Assembly forms: YIELD.

pub fn addhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: AddhnEmitter<T0, T1, T2>,

Emits the ADDHN instruction. Assembly forms: ADDHN VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn addhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Addhn2Emitter<T0, T1, T2>,

Emits the ADDHN2 instruction. Assembly forms: ADDHN2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn addp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AddpEmitter<T0, T1>,

Emits the ADDP instruction. Assembly forms: ADDP DD, VN.2D; ADDP VD.T, VN.T, VM.T; ADDP VD.T, VN.T, VM.T. Operands: rd, rn.

pub fn addp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Addp3Emitter<T0, T1, T2>,

Emits the ADDP_3 instruction. Assembly forms: ADDP DD, VN.2D; ADDP VD.T, VN.T, VM.T; ADDP VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn addv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AddvEmitter<T0, T1>,

Emits the ADDV instruction. Assembly forms: ADDV BD, VN.8B; ADDV BD, VN.16B; ADDV HD, VN.4H; ADDV HD, VN.8H (and related forms). Operands: rd, rn.

pub fn bic_2<T0, T1>(&mut self, rd: T0, rn_or_imm: T1)

where Self: Bic2Emitter<T0, T1>,

Emits the BIC_2 instruction. Assembly forms: BIC WD, WN, WM, {SOP #N}; BIC XD, XN, XM, {SOP #N}; BIC VD.8B, VN.8B, VM.8B; BIC VD.16B, VN.16B, VM.16B (and related forms). Operands: rd, rn_or_imm.

pub fn bif<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BifEmitter<T0, T1, T2>,

Emits the BIF instruction. Assembly forms: BIF DX.8B, VN.8B, VM.8B; BIF VX.16B, VN.16B, VM.16B. Operands: operand_1, rn, rm.

pub fn bit<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BitEmitter<T0, T1, T2>,

Emits the BIT instruction. Assembly forms: BIT DX.8B, VN.8B, VM.8B; BIT VX.16B, VN.16B, VM.16B. Operands: operand_1, rn, rm.

pub fn bsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BslEmitter<T0, T1, T2>,

Emits the BSL instruction. Assembly forms: BSL DX.8B, VN.8B, VM.8B; BSL VX.16B, VN.16B, VM.16B. Operands: operand_1, rn, rm.

pub fn cmeq<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: CmeqEmitter<T0, T1, T2>,

Emits the CMEQ instruction. Assembly forms: CMEQ DD, DN, DM; CMEQ DD, DN, #0; CMEQ VD.T, VN.T, VM.T; CMEQ VD.T, VN.T, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn cmge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: CmgeEmitter<T0, T1, T2>,

Emits the CMGE instruction. Assembly forms: CMGE DD, DN, DM; CMGE DD, DN, #0; CMGE VD.T, VN.T, VM.T; CMGE VD.T, VN.T, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn cmgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: CmgtEmitter<T0, T1, T2>,

Emits the CMGT instruction. Assembly forms: CMGT DD, DN, DM; CMGT DD, DN, #0; CMGT VD.T, VN.T, VM.T; CMGT VD.T, VN.T, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn cmhi<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: CmhiEmitter<T0, T1, T2>,

Emits the CMHI instruction. Assembly forms: CMHI DD, DN, DM; CMHI VD.T, VN.T, VM.T; CMHI VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn cmhs<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: CmhsEmitter<T0, T1, T2>,

Emits the CMHS instruction. Assembly forms: CMHS DD, DN, DM; CMHS VD.T, VN.T, VM.T; CMHS VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn cmle<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: CmleEmitter<T0, T1, T2>,

Emits the CMLE instruction. Assembly forms: CMLE DD, DN, #0; CMLE VD.T, VN.T, #0; CMLE VD.T, VN.T, #0. Operands: rd, rn, operand_3.

pub fn cmlt<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: CmltEmitter<T0, T1, T2>,

Emits the CMLT instruction. Assembly forms: CMLT DD, DN, #0; CMLT VD.T, VN.T, #0; CMLT VD.T, VN.T, #0. Operands: rd, rn, operand_3.

pub fn cmtst<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: CmtstEmitter<T0, T1, T2>,

Emits the CMTST instruction. Assembly forms: CMTST DD, DN, DM; CMTST VD.T, VN.T, VM.T; CMTST VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn dup<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: DupEmitter<T0, T1>,

Emits the DUP instruction. Assembly forms: DUP|MOV BD, VN.B[#IDX]; DUP|MOV HD, VN.H[#IDX]; DUP|MOV SD, VN.S[#IDX]; DUP|MOV DD, VN.D[#IDX] (and related forms). Operands: rd, rn.

pub fn ext<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, idx: T3)

where Self: ExtEmitter<T0, T1, T2, T3>,

Emits the EXT instruction. Assembly forms: EXT VD.8B, VN.8B, VM.8B, #IDX; EXT VD.16B, VN.16B, VM.16B, #IDX. Operands: rd, rn, rm, idx.

pub fn fabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FabdEmitter<T0, T1, T2>,

Emits the FABD instruction. Assembly forms: FABD SD, SN, SM; FABD DD, DN, DM; FABD VD.2S, VN.2S, VM.2S; FABD VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fabs<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FabsEmitter<T0, T1>,

Emits the FABS instruction. Assembly forms: FABS SD, SN; FABS DD, DN; FABS VD.2S, VN.2S; FABS VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn facge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FacgeEmitter<T0, T1, T2>,

Emits the FACGE instruction. Assembly forms: FACGE SD, SN, SM; FACGE DD, DN, DM; FACGE VD.2S, VN.2S, VM.2S; FACGE VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn facgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FacgtEmitter<T0, T1, T2>,

Emits the FACGT instruction. Assembly forms: FACGT SD, SN, SM; FACGT DD, DN, DM; FACGT VD.2S, VN.2S, VM.2S; FACGT VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FaddEmitter<T0, T1, T2>,

Emits the FADD instruction. Assembly forms: FADD SD, SN, SM; FADD DD, DN, DM; FADD VD.2S, VN.2S, VM.2S; FADD VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn faddp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FaddpEmitter<T0, T1>,

Emits the FADDP instruction. Assembly forms: FADDP SD, VN.2S; FADDP DD, VN.2D; FADDP VD.2S, VN.2S, VM.2S; FADDP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn.

pub fn faddp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Faddp3Emitter<T0, T1, T2>,

Emits the FADDP_3 instruction. Assembly forms: FADDP SD, VN.2S; FADDP DD, VN.2D; FADDP VD.2S, VN.2S, VM.2S; FADDP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fccmp<T0, T1, T2, T3>( &mut self, rn: T0, rm: T1, flags: T2, condition: T3, )

where Self: FccmpEmitter<T0, T1, T2, T3>,

Emits the FCCMP instruction. Assembly forms: FCCMP SN, SM, #NZCV, #COND; FCCMP DN, DM, #NZCV, #COND; FCCMP HN, HM, #NZCV, #COND. Operands: rn, rm, flags, condition.

pub fn fccmpe<T0, T1, T2, T3>( &mut self, rn: T0, rm: T1, flags: T2, condition: T3, )

where Self: FccmpeEmitter<T0, T1, T2, T3>,

Emits the FCCMPE instruction. Assembly forms: FCCMPE SN, SM, #NZCV, #COND; FCCMPE DN, DM, #NZCV, #COND; FCCMPE HN, HM, #NZCV, #COND. Operands: rn, rm, flags, condition.

pub fn fcmeq<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: FcmeqEmitter<T0, T1, T2>,

Emits the FCMEQ instruction. Assembly forms: FCMEQ SD, SN, SM; FCMEQ SD, SN, #0; FCMEQ DD, DN, DM; FCMEQ DD, DN, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn fcmge<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: FcmgeEmitter<T0, T1, T2>,

Emits the FCMGE instruction. Assembly forms: FCMGE SD, SN, SM; FCMGE SD, SN, #0; FCMGE DD, DN, DM; FCMGE DD, DN, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn fcmgt<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_operand_3: T2)

where Self: FcmgtEmitter<T0, T1, T2>,

Emits the FCMGT instruction. Assembly forms: FCMGT SD, SN, SM; FCMGT SD, SN, #0; FCMGT DD, DN, DM; FCMGT DD, DN, #0 (and related forms). Operands: rd, rn, rm_or_operand_3.

pub fn fcmle<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: FcmleEmitter<T0, T1, T2>,

Emits the FCMLE instruction. Assembly forms: FCMLE SD, SN, #0; FCMLE DD, DN, #0; FCMLE VD.2S, VN.2S, #0; FCMLE VD.4S, VN.4S, #0 (and related forms). Operands: rd, rn, operand_3.

pub fn fcmlt<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: FcmltEmitter<T0, T1, T2>,

Emits the FCMLT instruction. Assembly forms: FCMLT SD, SN, #0; FCMLT DD, DN, #0; FCMLT VD.2S, VN.2S, #0; FCMLT VD.4S, VN.4S, #0 (and related forms). Operands: rd, rn, operand_3.

pub fn fcmp<T0, T1>(&mut self, rn: T0, rm_or_operand_2: T1)

where Self: FcmpEmitter<T0, T1>,

Emits the FCMP instruction. Assembly forms: FCMP SN, SM; FCMP SN, #0; FCMP DN, DM; FCMP DN, #0 (and related forms). Operands: rn, rm_or_operand_2.

pub fn fcmpe<T0, T1>(&mut self, rn: T0, rm_or_operand_2: T1)

where Self: FcmpeEmitter<T0, T1>,

Emits the FCMPE instruction. Assembly forms: FCMPE SN, SM; FCMPE SN, #0; FCMPE DN, DM; FCMPE DN, #0 (and related forms). Operands: rn, rm_or_operand_2.

pub fn fcsel<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, condition: T3)

where Self: FcselEmitter<T0, T1, T2, T3>,

Emits the FCSEL instruction. Assembly forms: FCSEL SD, SN, SM, #COND; FCSEL DD, DN, DM, #COND; FCSEL HD, HN, HM, #COND. Operands: rd, rn, rm, condition.

pub fn fcvt<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtEmitter<T0, T1>,

Emits the FCVT instruction. Assembly forms: FCVT SD, HN; FCVT DD, HN; FCVT HD, SN; FCVT DD, SN (and related forms). Operands: rd, rn.

pub fn fcvtas<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtasEmitter<T0, T1>,

Emits the FCVTAS instruction. Assembly forms: FCVTAS WD, SN; FCVTAS XD, SN; FCVTAS WD, DN; FCVTAS XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtau<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtauEmitter<T0, T1>,

Emits the FCVTAU instruction. Assembly forms: FCVTAU WD, SN; FCVTAU XD, SN; FCVTAU WD, DN; FCVTAU XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtl<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtlEmitter<T0, T1>,

Emits the FCVTL instruction. Assembly forms: FCVTL VD.4S, VN.4H; FCVTL VD.2D, VN.2S. Operands: rd, rn.

pub fn fcvtl2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Fcvtl2Emitter<T0, T1>,

Emits the FCVTL2 instruction. Assembly forms: FCVTL2 VD.4S, VN.8H; FCVTL2 VD.2D, VN.4S. Operands: rd, rn.

pub fn fcvtms<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtmsEmitter<T0, T1>,

Emits the FCVTMS instruction. Assembly forms: FCVTMS WD, SN; FCVTMS XD, SN; FCVTMS WD, DN; FCVTMS XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtmu<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtmuEmitter<T0, T1>,

Emits the FCVTMU instruction. Assembly forms: FCVTMU WD, SN; FCVTMU XD, SN; FCVTMU WD, DN; FCVTMU XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtnEmitter<T0, T1>,

Emits the FCVTN instruction. Assembly forms: FCVTN VD.4S, VN.4H; FCVTN VD.2D, VN.2S; FCVTN VD.8B, VN.4H, VM.4H; FCVTN VD.16B, VN.8H, VM.8H (and related forms). Operands: rd, rn.

pub fn fcvtn2<T0, T1>(&mut self, rd_or_operand_1: T0, rn: T1)

where Self: Fcvtn2Emitter<T0, T1>,

Emits the FCVTN2 instruction. Assembly forms: FCVTN2 VD.4S, VN.8H; FCVTN2 VD.2D, VN.4S; FCVTN2 VX.16B, VN.4S, VM.4S. Operands: rd_or_operand_1, rn.

pub fn fcvtns<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtnsEmitter<T0, T1>,

Emits the FCVTNS instruction. Assembly forms: FCVTNS WD, SN; FCVTNS XD, SN; FCVTNS WD, DN; FCVTNS XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtnu<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtnuEmitter<T0, T1>,

Emits the FCVTNU instruction. Assembly forms: FCVTNU WD, SN; FCVTNU XD, SN; FCVTNU WD, DN; FCVTNU XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtps<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtpsEmitter<T0, T1>,

Emits the FCVTPS instruction. Assembly forms: FCVTPS WD, SN; FCVTPS XD, SN; FCVTPS WD, DN; FCVTPS XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtpu<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtpuEmitter<T0, T1>,

Emits the FCVTPU instruction. Assembly forms: FCVTPU WD, SN; FCVTPU XD, SN; FCVTPU WD, DN; FCVTPU XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtxn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtxnEmitter<T0, T1>,

Emits the FCVTXN instruction. Operands: rd, rn.

pub fn fcvtxn2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Fcvtxn2Emitter<T0, T1>,

Emits the FCVTXN2 instruction. Operands: rd, rn.

pub fn fcvtzs<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtzsEmitter<T0, T1>,

Emits the FCVTZS instruction. Assembly forms: FCVTZS WD, SN; FCVTZS XD, SN; FCVTZS WD, DN; FCVTZS XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtzs_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits: T2)

where Self: Fcvtzs3Emitter<T0, T1, T2>,

Emits the FCVTZS_3 instruction. Assembly forms: FCVTZS WD, SN; FCVTZS XD, SN; FCVTZS WD, DN; FCVTZS XD, DN (and related forms). Operands: rd, rn, fbits.

pub fn fcvtzu<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FcvtzuEmitter<T0, T1>,

Emits the FCVTZU instruction. Assembly forms: FCVTZU WD, SN; FCVTZU XD, SN; FCVTZU WD, DN; FCVTZU XD, DN (and related forms). Operands: rd, rn.

pub fn fcvtzu_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits: T2)

where Self: Fcvtzu3Emitter<T0, T1, T2>,

Emits the FCVTZU_3 instruction. Assembly forms: FCVTZU WD, SN; FCVTZU XD, SN; FCVTZU WD, DN; FCVTZU XD, DN (and related forms). Operands: rd, rn, fbits.

pub fn fdiv<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FdivEmitter<T0, T1, T2>,

Emits the FDIV instruction. Assembly forms: FDIV SD, SN, SM; FDIV DD, DN, DM; FDIV VD.2S, VN.2S, VM.2S; FDIV VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fmadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: FmaddEmitter<T0, T1, T2, T3>,

Emits the FMADD instruction. Assembly forms: FMADD SD, SN, SM, SA; FMADD DD, DN, DM, DA; FMADD HD, HN, HM, HA. Operands: rd, rn, rm, operand_4.

pub fn fmax<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmaxEmitter<T0, T1, T2>,

Emits the FMAX instruction. Assembly forms: FMAX SD, SN, SM; FMAX DD, DN, DM; FMAX VD.2S, VN.2S, VM.2S; FMAX VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fmaxnm<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmaxnmEmitter<T0, T1, T2>,

Emits the FMAXNM instruction. Assembly forms: FMAXNM SD, SN, SM; FMAXNM DD, DN, DM; FMAXNM VD.2S, VN.2S, VM.2S; FMAXNM VD.2D, VN.2D, VM.2D (and related forms). Operands: rd, rn, rm.

pub fn fmaxnmp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmaxnmpEmitter<T0, T1, T2>,

Emits the FMAXNMP instruction. Assembly forms: FMAXNMP SD, VN.2S; FMAXNMP DD, VN.2D; FMAXNMP VD.2S, VN.2S, VM.2S; FMAXNMP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fmaxnmp_2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Fmaxnmp2Emitter<T0, T1>,

Emits the FMAXNMP_2 instruction. Assembly forms: FMAXNMP SD, VN.2S; FMAXNMP DD, VN.2D; FMAXNMP VD.2S, VN.2S, VM.2S; FMAXNMP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn.

pub fn fmaxnmv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FmaxnmvEmitter<T0, T1>,

Emits the FMAXNMV instruction. Assembly forms: FMAXNMV SD, VN.4S; FMAXNMV HD, VN.4H; FMAXNMV HD, VN.8H. Operands: rd, rn.

pub fn fmaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmaxpEmitter<T0, T1, T2>,

Emits the FMAXP instruction. Assembly forms: FMAXP SD, VN.2S; FMAXP DD, VN.2D; FMAXP VD.2S, VN.2S, VM.2S; FMAXP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fmaxp_2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Fmaxp2Emitter<T0, T1>,

Emits the FMAXP_2 instruction. Assembly forms: FMAXP SD, VN.2S; FMAXP DD, VN.2D; FMAXP VD.2S, VN.2S, VM.2S; FMAXP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn.

pub fn fmaxv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FmaxvEmitter<T0, T1>,

Emits the FMAXV instruction. Assembly forms: FMAXV SD, VN.4S; FMAXV HD, VN.4H; FMAXV HD, VN.8H. Operands: rd, rn.

pub fn fmin<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FminEmitter<T0, T1, T2>,

Emits the FMIN instruction. Assembly forms: FMIN SD, SN, SM; FMIN DD, DN, DM; FMIN VD.2S, VN.2S, VM.2S; FMIN VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fminnm<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FminnmEmitter<T0, T1, T2>,

Emits the FMINNM instruction. Assembly forms: FMINNM SD, SN, SM; FMINNM DD, DN, DM; FMINNM VD.2S, VN.2S, VM.2S; FMINNM VD.2D, VN.2D, VM.2D (and related forms). Operands: rd, rn, rm.

pub fn fminnmv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FminnmvEmitter<T0, T1>,

Emits the FMINNMV instruction. Assembly forms: FMINNMV SD, VN.4S; FMINNMV HD, VN.4H; FMINNMV HD, VN.8H. Operands: rd, rn.

pub fn fminnmp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FminnmpEmitter<T0, T1, T2>,

Emits the FMINNMP instruction. Assembly forms: FMINNMP SD, VN.2S; FMINNMP DD, VN.2D; FMINNMP VD.2S, VN.2S, VM.2S; FMINNMP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fminnmp_2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Fminnmp2Emitter<T0, T1>,

Emits the FMINNMP_2 instruction. Assembly forms: FMINNMP SD, VN.2S; FMINNMP DD, VN.2D; FMINNMP VD.2S, VN.2S, VM.2S; FMINNMP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn.

pub fn fminp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FminpEmitter<T0, T1>,

Emits the FMINP instruction. Assembly forms: FMINP SD, VN.2S; FMINP DD, VN.2D; FMINP VD.2S, VN.2S, VM.2S; FMINP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn.

pub fn fminp_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Fminp3Emitter<T0, T1, T2>,

Emits the FMINP_3 instruction. Assembly forms: FMINP SD, VN.2S; FMINP DD, VN.2D; FMINP VD.2S, VN.2S, VM.2S; FMINP VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fminv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FminvEmitter<T0, T1>,

Emits the FMINV instruction. Assembly forms: FMINV SD, VN.4S; FMINV HD, VN.4H; FMINV HD, VN.8H. Operands: rd, rn.

pub fn fmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: FmlaEmitter<T0, T1, T2>,

Emits the FMLA instruction. Assembly forms: FMLA SX, SN, VM.S[#IDX]; FMLA DX, DN, VM.D[#IDX]; FMLA VX.2S, VN.2S, VM.2S; FMLA VX.4S, VN.4S, VM.4S (and related forms). Operands: operand_1, rn, rm.

pub fn fmls<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: FmlsEmitter<T0, T1, T2>,

Emits the FMLS instruction. Assembly forms: FMLS SX, SN, VM.S[#IDX]; FMLS DX, DN, VM.D[#IDX]; FMLS VX.2S, VN.2S, VM.2S; FMLS VX.4S, VN.4S, VM.4S (and related forms). Operands: operand_1, rn, rm.

pub fn fmov<T0, T1>(&mut self, rd: T0, rn_or_fimm: T1)

where Self: FmovEmitter<T0, T1>,

Emits the FMOV instruction. Assembly forms: FMOV WD, SN; FMOV XD, DN; FMOV XD, VN.D[#1]; FMOV SD, WN (and related forms). Operands: rd, rn_or_fimm.

pub fn fmsub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: FmsubEmitter<T0, T1, T2, T3>,

Emits the FMSUB instruction. Assembly forms: FMSUB SD, SN, SM, SA; FMSUB DD, DN, DM, DA; FMSUB HD, HN, HM, HA. Operands: rd, rn, rm, operand_4.

pub fn fmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmulEmitter<T0, T1, T2>,

Emits the FMUL instruction. Assembly forms: FMUL SD, SN, SM; FMUL DD, DN, DM; FMUL SD, SN, VM.S[#IDX]; FMUL DD, DN, VM.D[#IDX] (and related forms). Operands: rd, rn, rm.

pub fn fmulx<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FmulxEmitter<T0, T1, T2>,

Emits the FMULX instruction. Assembly forms: FMULX SD, SN, SM; FMULX DD, DN, DM; FMULX SD, SN, VM.S[#IDX]; FMULX DD, DN, VM.D[#IDX] (and related forms). Operands: rd, rn, rm.

pub fn fneg<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FnegEmitter<T0, T1>,

Emits the FNEG instruction. Assembly forms: FNEG SD, SN; FNEG DD, DN; FNEG VD.2S, VN.2S; FNEG VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn fnmadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: FnmaddEmitter<T0, T1, T2, T3>,

Emits the FNMADD instruction. Assembly forms: FNMADD SD, SN, SM, SA; FNMADD DD, DN, DM, DA; FNMADD HD, HN, HM, HA. Operands: rd, rn, rm, operand_4.

pub fn fnmsub<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: FnmsubEmitter<T0, T1, T2, T3>,

Emits the FNMSUB instruction. Assembly forms: FNMSUB SD, SN, SM, SA; FNMSUB DD, DN, DM, DA; FNMSUB HD, HN, HM, HA. Operands: rd, rn, rm, operand_4.

pub fn fnmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FnmulEmitter<T0, T1, T2>,

Emits the FNMUL instruction. Assembly forms: FNMUL SD, SN, SM; FNMUL DD, DN, DM; FNMUL HD, HN, HM. Operands: rd, rn, rm.

pub fn frecpe<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrecpeEmitter<T0, T1>,

Emits the FRECPE instruction. Assembly forms: FRECPE SD, SN; FRECPE DD, DN; FRECPE VD.2S, VN.2S; FRECPE VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frecps<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FrecpsEmitter<T0, T1, T2>,

Emits the FRECPS instruction. Assembly forms: FRECPS SD, SN, SM; FRECPS DD, DN, DM; FRECPS VD.2S, VN.2S, VM.2S; FRECPS VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn frecpx<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrecpxEmitter<T0, T1>,

Emits the FRECPX instruction. Assembly forms: FRECPX SD, SN, SM; FRECPX DD, DN, DM; FRECPX HD, HN, HM. Operands: rd, rn.

pub fn frint32x<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Frint32xEmitter<T0, T1>,

Emits the FRINT32X instruction. Assembly forms: FRINT32X SD, SN; FRINT32X DD, DN; FRINT32X VD.2S, VN.2S; FRINT32X VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frint32z<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Frint32zEmitter<T0, T1>,

Emits the FRINT32Z instruction. Assembly forms: FRINT32Z SD, SN; FRINT32Z DD, DN; FRINT32Z VD.2S, VN.2S; FRINT32Z VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frint64x<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Frint64xEmitter<T0, T1>,

Emits the FRINT64X instruction. Assembly forms: FRINT64X SD, SN; FRINT64X DD, DN; FRINT64X VD.2S, VN.2S; FRINT64X VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frint64z<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Frint64zEmitter<T0, T1>,

Emits the FRINT64Z instruction. Assembly forms: FRINT64Z SD, SN; FRINT64Z DD, DN; FRINT64Z VD.2S, VN.2S; FRINT64Z VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frinta<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintaEmitter<T0, T1>,

Emits the FRINTA instruction. Assembly forms: FRINTA SD, SN; FRINTA DD, DN; FRINTA VD.2S, VN.2S; FRINTA VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frinti<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintiEmitter<T0, T1>,

Emits the FRINTI instruction. Assembly forms: FRINTI SD, SN; FRINTI DD, DN; FRINTI VD.2S, VN.2S; FRINTI VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frintm<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintmEmitter<T0, T1>,

Emits the FRINTM instruction. Assembly forms: FRINTM SD, SN; FRINTM DD, DN; FRINTM VD.2S, VN.2S; FRINTM VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frintn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintnEmitter<T0, T1>,

Emits the FRINTN instruction. Assembly forms: FRINTN SD, SN; FRINTN DD, DN; FRINTN VD.2S, VN.2S; FRINTN VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frintp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintpEmitter<T0, T1>,

Emits the FRINTP instruction. Assembly forms: FRINTP SD, SN; FRINTP DD, DN; FRINTP VD.2S, VN.2S; FRINTP VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frintx<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintxEmitter<T0, T1>,

Emits the FRINTX instruction. Assembly forms: FRINTX SD, SN; FRINTX DD, DN; FRINTX VD.2S, VN.2S; FRINTX VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frintz<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrintzEmitter<T0, T1>,

Emits the FRINTZ instruction. Assembly forms: FRINTZ SD, SN; FRINTZ DD, DN; FRINTZ VD.2S, VN.2S; FRINTZ VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frsqrte<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FrsqrteEmitter<T0, T1>,

Emits the FRSQRTE instruction. Assembly forms: FRSQRTE SD, SN; FRSQRTE DD, DN; FRSQRTE VD.2S, VN.2S; FRSQRTE VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn frsqrts<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FrsqrtsEmitter<T0, T1, T2>,

Emits the FRSQRTS instruction. Assembly forms: FRSQRTS SD, SN, SM; FRSQRTS DD, DN, DM; FRSQRTS VD.2S, VN.2S, VM.2S; FRSQRTS VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn fsqrt<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FsqrtEmitter<T0, T1>,

Emits the FSQRT instruction. Assembly forms: FSQRT SD, SN; FSQRT DD, DN; FSQRT VD.2S, VN.2S; FSQRT VD.4S, VN.4S (and related forms). Operands: rd, rn.

pub fn fsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: FsubEmitter<T0, T1, T2>,

Emits the FSUB instruction. Assembly forms: FSUB SD, SN, SM; FSUB DD, DN, DM; FSUB VD.2S, VN.2S, VM.2S; FSUB VD.4S, VN.4S, VM.4S (and related forms). Operands: rd, rn, rm.

pub fn ins<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: InsEmitter<T0, T1>,

Emits the INS instruction. Assembly forms: INS|MOV VD.B[#IDX], WN; INS|MOV VD.H[#IDX], WN; INS|MOV VD.S[#IDX], WN; INS|MOV VD.D[#IDX], XN (and related forms). Operands: rd, rn.

pub fn ld1<T0, T1>(&mut self, idx_or_operand_1: T0, addr: T1)

where Self: Ld1Emitter<T0, T1>,

Emits the LD1 instruction. Assembly forms: LD1 VX.B[#IDX], [XN|SP]; LD1 VX.H[#IDX], [XN|SP]; LD1 VX.S[#IDX], [XN|SP]; LD1 VX.D[#IDX], [XN|SP] (and related forms). Operands: idx_or_operand_1, addr.

pub fn ld1_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)

where Self: Ld13Emitter<T0, T1, T2>,

Emits the LD1_3 instruction. Assembly forms: LD1 VX.B[#IDX], [XN|SP]; LD1 VX.H[#IDX], [XN|SP]; LD1 VX.S[#IDX], [XN|SP]; LD1 VX.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, addr.

pub fn ld1_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)

where Self: Ld14Emitter<T0, T1, T2, T3>,

Emits the LD1_4 instruction. Assembly forms: LD1 VX.B[#IDX], [XN|SP]; LD1 VX.H[#IDX], [XN|SP]; LD1 VX.S[#IDX], [XN|SP]; LD1 VX.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, addr.

pub fn ld1_5<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: Ld15Emitter<T0, T1, T2, T3, T4>,

Emits the LD1_5 instruction. Assembly forms: LD1 VX.B[#IDX], [XN|SP]; LD1 VX.H[#IDX], [XN|SP]; LD1 VX.S[#IDX], [XN|SP]; LD1 VX.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, rm2, addr.

pub fn ld1r<T0, T1>(&mut self, operand_1: T0, addr: T1)

where Self: Ld1rEmitter<T0, T1>,

Emits the LD1R instruction. Assembly forms: LD1R 1X{VD.T}, [XN|SP]; LD1R 1X{VD.T}, [XN|SP]; LD1R 1X{VD.T}, [XN|SP, XM]@; LD1R 1X{VD.T}, [XN|SP, XM]@ (and related forms). Operands: operand_1, addr.

pub fn ld2<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)

where Self: Ld2Emitter<T0, T1, T2>,

Emits the LD2 instruction. Assembly forms: LD2 2X{VX.B}[#IDX], [XN|SP]; LD2 2X{VX.H}[#IDX], [XN|SP]; LD2 2X{VX.S}[#IDX], [XN|SP]; LD2 2X{VX.D}[#IDX], [XN|SP] (and related forms). Operands: rd, rn, addr.

pub fn ld2r<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)

where Self: Ld2rEmitter<T0, T1, T2>,

Emits the LD2R instruction. Assembly forms: LD2R 2X{VD.T}, [XN|SP]; LD2R 2X{VD.T}, [XN|SP]; LD2R 2X{VD.T}, [XN|SP, XM]@; LD2R 2X{VD.T}, [XN|SP, XM]@ (and related forms). Operands: rd, rn, addr.

pub fn ld3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)

where Self: Ld3Emitter<T0, T1, T2, T3>,

Emits the LD3 instruction. Assembly forms: LD3 3X{VX.B}[#IDX], [XN|SP]; LD3 3X{VX.H}[#IDX], [XN|SP]; LD3 3X{VX.S}[#IDX], [XN|SP]; LD3 3X{VX.D}[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, addr.

pub fn ld3r<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)

where Self: Ld3rEmitter<T0, T1, T2, T3>,

Emits the LD3R instruction. Assembly forms: LD3R 3X{VD.T}, [XN|SP]; LD3R 3X{VD.T}, [XN|SP]; LD3R 3X{VD.T}, [XN|SP, XM]@; LD3R 3X{VD.T}, [XN|SP, XM]@ (and related forms). Operands: rd, rn, rm1, addr.

pub fn ld4<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: Ld4Emitter<T0, T1, T2, T3, T4>,

Emits the LD4 instruction. Assembly forms: LD4 4X{VX.B}[#IDX], [XN|SP]; LD4 4X{VX.H}[#IDX], [XN|SP]; LD4 4X{VX.S}[#IDX], [XN|SP]; LD4 4X{VX.D}[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, rm2, addr.

pub fn ld4r<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: Ld4rEmitter<T0, T1, T2, T3, T4>,

Emits the LD4R instruction. Assembly forms: LD4R 4X{VD.T}, [XN|SP]; LD4R 4X{VD.T}, [XN|SP]; LD4R 4X{VD.T}, [XN|SP, XM]@; LD4R 4X{VD.T}, [XN|SP, XM]@ (and related forms). Operands: rd, rn, rm1, rm2, addr.

pub fn mla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: MlaEmitter<T0, T1, T2>,

Emits the MLA instruction. Assembly forms: MLA VX.T, VN.T, VM.T; MLA VX.T, VN.T, VM.T; MLA VX.4H, VN.4H, VM.H[#IDX]; MLA VX.8H, VN.8H, VM.H[#IDX] (and related forms). Operands: operand_1, rn, rm.

pub fn mls<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: MlsEmitter<T0, T1, T2>,

Emits the MLS instruction. Assembly forms: MLS VX.T, VN.T, VM.T; MLS VX.T, VN.T, VM.T; MLS VX.4H, VN.4H, VM.H[#IDX]; MLS VX.8H, VN.8H, VM.H[#IDX] (and related forms). Operands: operand_1, rn, rm.

pub fn movi<T0, T1>(&mut self, rd: T0, imm: T1)

where Self: MoviEmitter<T0, T1>,

Emits the MOVI instruction. Assembly forms: MOVI DD, #IMM, {LSL #N}; MOVI VD.T, #IMM, {LSL #N}; MOVI VD.T, #IMM, {LSL #N}. Operands: rd, imm.

pub fn movi_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)

where Self: Movi3Emitter<T0, T1, T2>,

Emits the MOVI_3 instruction. Assembly forms: MOVI DD, #IMM, {LSL #N}; MOVI VD.T, #IMM, {LSL #N}; MOVI VD.T, #IMM, {LSL #N}. Operands: rd, imm, shift.

pub fn mvni<T0, T1>(&mut self, rd: T0, imm: T1)

where Self: MvniEmitter<T0, T1>,

Emits the MVNI instruction. Assembly forms: MVNI DD, #IMM, {LSL #N}; MVNI VD.T, #IMM, {LSL #N}; MVNI VD.T, #IMM, {LSL #N}. Operands: rd, imm.

pub fn mvni_3<T0, T1, T2>(&mut self, rd: T0, imm: T1, shift: T2)

where Self: Mvni3Emitter<T0, T1, T2>,

Emits the MVNI_3 instruction. Assembly forms: MVNI DD, #IMM, {LSL #N}; MVNI VD.T, #IMM, {LSL #N}; MVNI VD.T, #IMM, {LSL #N}. Operands: rd, imm, shift.

pub fn not_<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: NotEmitter<T0, T1>,

Emits the NOT_ instruction. Assembly forms: NOT|MVN VD.8B, VN.8B; NOT|MVN VD.16B, VN.16B. Operands: rd, rn.

pub fn orr_2<T0, T1>(&mut self, rd: T0, rn_or_imm: T1)

where Self: Orr2Emitter<T0, T1>,

Emits the ORR_2 instruction. Assembly forms: ORR WD, WN, WM, {SOP #N}; ORR XD, XN, XM, {SOP #N}; ORR WD|WSP, WN, #LOG_IMM; ORR XD|SP, XN, #LOG_IMM (and related forms). Operands: rd, rn_or_imm.

pub fn pmul<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: PmulEmitter<T0, T1, T2>,

Emits the PMUL instruction. Assembly forms: PMUL VD.8B, VN.8B, VM.8B; PMUL VD.16B, VN.16B, VM.16B. Operands: rd, rn, rm.

pub fn pmull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: PmullEmitter<T0, T1, T2>,

Emits the PMULL instruction. Assembly forms: PMULL VD.8H, VN.8B, VM.8B; PMULL VD.1Q, VN.1D, VM.1D. Operands: rd, rn, rm.

pub fn pmull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Pmull2Emitter<T0, T1, T2>,

Emits the PMULL2 instruction. Assembly forms: PMULL2 VD.8H, VN.16B, VM.16B; PMULL2 VD.1Q, VN.2D, VM.2D. Operands: rd, rn, rm.

pub fn raddhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: RaddhnEmitter<T0, T1, T2>,

Emits the RADDHN instruction. Assembly forms: RADDHN VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn raddhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Raddhn2Emitter<T0, T1, T2>,

Emits the RADDHN2 instruction. Assembly forms: RADDHN2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn rshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: RshrnEmitter<T0, T1, T2>,

Emits the RSHRN instruction. Assembly forms: RSHRN VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn rshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Rshrn2Emitter<T0, T1, T2>,

Emits the RSHRN2 instruction. Assembly forms: RSHRN2 VX.TA, VN.TB, #N. Operands: operand_1, rn, shift.

pub fn rsubhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: RsubhnEmitter<T0, T1, T2>,

Emits the RSUBHN instruction. Assembly forms: RSUBHN VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn rsubhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Rsubhn2Emitter<T0, T1, T2>,

Emits the RSUBHN2 instruction. Assembly forms: RSUBHN2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn saba<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SabaEmitter<T0, T1, T2>,

Emits the SABA instruction. Assembly forms: SABA VX.T, VN.T, VM.T; SABA VX.T, VN.T, VM.T. Operands: operand_1, rn, rm.

pub fn sabal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SabalEmitter<T0, T1, T2>,

Emits the SABAL instruction. Assembly forms: SABAL VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn sabal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sabal2Emitter<T0, T1, T2>,

Emits the SABAL2 instruction. Assembly forms: SABAL2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn sabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SabdEmitter<T0, T1, T2>,

Emits the SABD instruction. Assembly forms: SABD VD.T, VN.T, VM.T; SABD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn sabdl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SabdlEmitter<T0, T1, T2>,

Emits the SABDL instruction. Assembly forms: SABDL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn sabdl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Sabdl2Emitter<T0, T1, T2>,

Emits the SABDL2 instruction. Assembly forms: SABDL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn sadalp<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: SadalpEmitter<T0, T1>,

Emits the SADALP instruction. Assembly forms: SADALP VX.TA, VN.TB; SADALP VX.TA, VN.TB. Operands: operand_1, rn.

pub fn saddl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SaddlEmitter<T0, T1, T2>,

Emits the SADDL instruction. Assembly forms: SADDL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn saddl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Saddl2Emitter<T0, T1, T2>,

Emits the SADDL2 instruction. Assembly forms: SADDL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn saddlp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SaddlpEmitter<T0, T1>,

Emits the SADDLP instruction. Assembly forms: SADDLP VD.TA, VN.TB; SADDLP VD.TA, VN.TB. Operands: rd, rn.

pub fn saddlv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SaddlvEmitter<T0, T1>,

Emits the SADDLV instruction. Assembly forms: SADDLV HD, VN.8B; SADDLV HD, VN.16B; SADDLV SD, VN.4H; SADDLV SD, VN.8H (and related forms). Operands: rd, rn.

pub fn saddw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SaddwEmitter<T0, T1, T2>,

Emits the SADDW instruction. Assembly forms: SADDW VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn saddw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Saddw2Emitter<T0, T1, T2>,

Emits the SADDW2 instruction. Assembly forms: SADDW2 VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn scvtf<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: ScvtfEmitter<T0, T1>,

Emits the SCVTF instruction. Assembly forms: SCVTF SD, WN; SCVTF SD, WN, #FBITS; SCVTF SD, XN; SCVTF SD, XN, #FBITS (and related forms). Operands: rd, rn.

pub fn scvtf_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits_or_bits: T2)

where Self: Scvtf3Emitter<T0, T1, T2>,

Emits the SCVTF_3 instruction. Assembly forms: SCVTF SD, WN; SCVTF SD, WN, #FBITS; SCVTF SD, XN; SCVTF SD, XN, #FBITS (and related forms). Operands: rd, rn, fbits_or_bits.

pub fn shadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: ShaddEmitter<T0, T1, T2>,

Emits the SHADD instruction. Assembly forms: SHADD VD.T, VN.T, VM.T; SHADD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn shl<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: ShlEmitter<T0, T1, T2>,

Emits the SHL instruction. Assembly forms: SHL DD, DN, #N; SHL VD.T, VN.T, #N; SHL VD.T, VN.T, #N. Operands: rd, rn, shift.

pub fn shll<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: ShllEmitter<T0, T1, T2>,

Emits the SHLL instruction. Assembly forms: SHLL VD.8H, VN.8B, #8; SHLL VD.4S, VN.4H, #16; SHLL VD.2D, VN.2S, #32. Operands: rd, rn, operand_3.

pub fn shll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, operand_3: T2)

where Self: Shll2Emitter<T0, T1, T2>,

Emits the SHLL2 instruction. Assembly forms: SHLL2 VD.8H, VN.16B, #8; SHLL2 VD.4S, VN.8H, #16; SHLL2 VD.2D, VN.4S, #32. Operands: rd, rn, operand_3.

pub fn shrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: ShrnEmitter<T0, T1, T2>,

Emits the SHRN instruction. Assembly forms: SHRN VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn shrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Shrn2Emitter<T0, T1, T2>,

Emits the SHRN2 instruction. Assembly forms: SHRN2 VX.TA, VN.TB, #N. Operands: operand_1, rn, shift.

pub fn shsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: ShsubEmitter<T0, T1, T2>,

Emits the SHSUB instruction. Assembly forms: SHSUB VD.T, VN.T, VM.T; SHSUB VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn sli<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: SliEmitter<T0, T1, T2>,

Emits the SLI instruction. Assembly forms: SLI DX, DN, #N; SLI VX.T, VN.T, #N; SLI VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn smaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SmaxpEmitter<T0, T1, T2>,

Emits the SMAXP instruction. Assembly forms: SMAXP VD.T, VN.T, VM.T; SMAXP VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn smaxv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SmaxvEmitter<T0, T1>,

Emits the SMAXV instruction. Assembly forms: SMAXV BD, VN.8B; SMAXV BD, VN.16B; SMAXV HD, VN.4H; SMAXV HD, VN.8H (and related forms). Operands: rd, rn.

pub fn sminp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SminpEmitter<T0, T1, T2>,

Emits the SMINP instruction. Assembly forms: SMINP VD.T, VN.T, VM.T; SMINP VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn sminv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SminvEmitter<T0, T1>,

Emits the SMINV instruction. Assembly forms: SMINV BD, VN.8B; SMINV BD, VN.16B; SMINV HD, VN.4H; SMINV HD, VN.8H (and related forms). Operands: rd, rn.

pub fn smlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SmlalEmitter<T0, T1, T2>,

Emits the SMLAL instruction. Assembly forms: SMLAL VX.TA, VN.TB, VM.TB; SMLAL VX.4S, VN.4H, VM.H[#IDX]; SMLAL VX.2D, VN.2S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn smlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Smlal2Emitter<T0, T1, T2>,

Emits the SMLAL2 instruction. Assembly forms: SMLAL2 VX.TA, VN.TB, VM.TB; SMLAL2 VX.4S, VN.8H, VM.H[#IDX]; SMLAL2 VX.2D, VN.4S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn smlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SmlslEmitter<T0, T1, T2>,

Emits the SMLSL instruction. Assembly forms: SMLSL VX.TA, VN.TB, VM.TB; SMLSL VX.4S, VN.4H, VM.H[#IDX]; SMLSL VX.2D, VN.2S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn smlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Smlsl2Emitter<T0, T1, T2>,

Emits the SMLSL2 instruction. Assembly forms: SMLSL2 VX.TA, VN.TB, VM.TB; SMLSL2 VX.4S, VN.8H, VM.H[#IDX]; SMLSL2 VX.2D, VN.4S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn smov<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SmovEmitter<T0, T1>,

Emits the SMOV instruction. Assembly forms: SMOV WD, VN.B[#IDX]; SMOV WD, VN.H[#IDX]; SMOV XD, VN.B[#IDX]; SMOV XD, VN.H[#IDX] (and related forms). Operands: rd, rn.

pub fn smull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Smull2Emitter<T0, T1, T2>,

Emits the SMULL2 instruction. Assembly forms: SMULL2 VD.TA, VN.TB, VM.TB; SMULL2 VD.4S, VN.8H, VM.H[#IDX]; SMULL2 VD.2D, VN.4S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn sqabs<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SqabsEmitter<T0, T1>,

Emits the SQABS instruction. Assembly forms: SQABS BD, BN; SQABS HD, HN; SQABS SD, SN; SQABS DD, DN (and related forms). Operands: rd, rn.

pub fn sqadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqaddEmitter<T0, T1, T2>,

Emits the SQADD instruction. Assembly forms: SQADD BD, BN, BM; SQADD HD, HN, HM; SQADD SD, SN, SM; SQADD DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn sqdmlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SqdmlalEmitter<T0, T1, T2>,

Emits the SQDMLAL instruction. Assembly forms: SQDMLAL SX, HN, HM; SQDMLAL DX, SN, SM; SQDMLAL SX, HN, VM.H[#IDX]; SQDMLAL DX, SN, VM.S[#IDX] (and related forms). Operands: operand_1, rn, rm.

pub fn sqdmlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sqdmlal2Emitter<T0, T1, T2>,

Emits the SQDMLAL2 instruction. Assembly forms: SQDMLAL2 VX.TA, VN.TB, VM.TB; SQDMLAL2 VX.4S, VN.8H, VM.H[#IDX]; SQDMLAL2 VX.2D, VN.4S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn sqdmlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SqdmlslEmitter<T0, T1, T2>,

Emits the SQDMLSL instruction. Assembly forms: SQDMLSL SX, HN, HM; SQDMLSL DX, SN, SM; SQDMLSL SX, HN, VM.H[#IDX]; SQDMLSL DX, SN, VM.S[#IDX] (and related forms). Operands: operand_1, rn, rm.

pub fn sqdmlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sqdmlsl2Emitter<T0, T1, T2>,

Emits the SQDMLSL2 instruction. Assembly forms: SQDMLSL2 VX.TA, VN.TB, VM.TB; SQDMLSL2 VX.4S, VN.8H, VM.H[#IDX]; SQDMLSL2 VX.2D, VN.4S, VM.S[#IDX]. Operands: operand_1, rn, rm.

pub fn sqdmulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqdmulhEmitter<T0, T1, T2>,

Emits the SQDMULH instruction. Assembly forms: SQDMULH HD, HN, HM; SQDMULH SD, SN, SM; SQDMULH HD, HN, VM.H[#IDX]; SQDMULH SD, SN, VM.S[#IDX] (and related forms). Operands: rd, rn, rm.

pub fn sqdmull<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqdmullEmitter<T0, T1, T2>,

Emits the SQDMULL instruction. Assembly forms: SQDMULL SD, HN, HM; SQDMULL DD, SN, SM; SQDMULL SD, HN, VM.H[#IDX]; SQDMULL DD, SN, VM.S[#IDX] (and related forms). Operands: rd, rn, rm.

pub fn sqdmull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Sqdmull2Emitter<T0, T1, T2>,

Emits the SQDMULL2 instruction. Assembly forms: SQDMULL2 VD.TA, VN.TB, VM.TB; SQDMULL2 VD.4S, VN.8H, VM.H[#IDX]; SQDMULL2 VD.2D, VN.4S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn sqneg<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SqnegEmitter<T0, T1>,

Emits the SQNEG instruction. Assembly forms: SQNEG BD, BN; SQNEG HD, HN; SQNEG SD, SN; SQNEG DD, DN (and related forms). Operands: rd, rn.

pub fn sqrdmulh<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqrdmulhEmitter<T0, T1, T2>,

Emits the SQRDMULH instruction. Assembly forms: SQRDMULH HD, HN, HM; SQRDMULH SD, SN, SM; SQRDMULH HD, HN, VM.H[#IDX]; SQRDMULH SD, SN, VM.S[#IDX] (and related forms). Operands: rd, rn, rm.

pub fn sqrshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqrshlEmitter<T0, T1, T2>,

Emits the SQRSHL instruction. Assembly forms: SQRSHL BD, BN, BM; SQRSHL HD, HN, HM; SQRSHL SD, SN, SM; SQRSHL DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn sqrshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SqrshrnEmitter<T0, T1, T2>,

Emits the SQRSHRN instruction. Assembly forms: SQRSHRN BD, HN, #N; SQRSHRN HD, SN, #N; SQRSHRN SD, DN, #N; SQRSHRN VD.8B, VN.8H, #N (and related forms). Operands: rd, rn, shift.

pub fn sqrshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Sqrshrn2Emitter<T0, T1, T2>,

Emits the SQRSHRN2 instruction. Assembly forms: SQRSHRN2 VX.16B, VN.8H, #N; SQRSHRN2 VX.8H, VN.4S, #N; SQRSHRN2 VX.4S, VN.2D, #N. Operands: operand_1, rn, shift.

pub fn sqrshrun<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SqrshrunEmitter<T0, T1, T2>,

Emits the SQRSHRUN instruction. Assembly forms: SQRSHRUN BD, HN, #N; SQRSHRUN HD, SN, #N; SQRSHRUN SD, DN, #N; SQRSHRUN VD.8B, VN.8H, #N (and related forms). Operands: rd, rn, shift.

pub fn sqrshrun2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Sqrshrun2Emitter<T0, T1, T2>,

Emits the SQRSHRUN2 instruction. Assembly forms: SQRSHRUN2 VX.16B, VN.8H, #N; SQRSHRUN2 VX.8H, VN.4S, #N; SQRSHRUN2 VX.4S, VN.2D, #N. Operands: operand_1, rn, shift.

pub fn sqshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: SqshlEmitter<T0, T1, T2>,

Emits the SQSHL instruction. Assembly forms: SQSHL BD, BN, BM; SQSHL HD, HN, HM; SQSHL SD, SN, SM; SQSHL DD, DN, DM (and related forms). Operands: rd, rn, rm_or_shift.

pub fn sqshlu<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SqshluEmitter<T0, T1, T2>,

Emits the SQSHLU instruction. Assembly forms: SQSHLU BD, BN, #N; SQSHLU HD, HN, #N; SQSHLU SD, SN, #N; SQSHLU DD, DN, #N (and related forms). Operands: rd, rn, shift.

pub fn sqshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SqshrnEmitter<T0, T1, T2>,

Emits the SQSHRN instruction. Assembly forms: SQSHRN BD, HN, #N; SQSHRN HD, SN, #N; SQSHRN SD, DN, #N; SQSHRN VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn sqshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Sqshrn2Emitter<T0, T1, T2>,

Emits the SQSHRN2 instruction. Assembly forms: SQSHRN2 VX.TA, VN.TB, #N. Operands: operand_1, rn, shift.

pub fn sqshrun<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SqshrunEmitter<T0, T1, T2>,

Emits the SQSHRUN instruction. Assembly forms: SQSHRUN BD, HN, #N; SQSHRUN HD, SN, #N; SQSHRUN SD, DN, #N; SQSHRUN VD.8B, VN.8H, #N (and related forms). Operands: rd, rn, shift.

pub fn sqshrun2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Sqshrun2Emitter<T0, T1, T2>,

Emits the SQSHRUN2 instruction. Assembly forms: SQSHRUN2 VX.16B, VN.8H, #N; SQSHRUN2 VX.8H, VN.4S, #N; SQSHRUN2 VX.4S, VN.2D, #N. Operands: operand_1, rn, shift.

pub fn sqsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SqsubEmitter<T0, T1, T2>,

Emits the SQSUB instruction. Assembly forms: SQSUB BD, BN, BM; SQSUB HD, HN, HM; SQSUB SD, SN, SM; SQSUB DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn sqxtn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SqxtnEmitter<T0, T1>,

Emits the SQXTN instruction. Assembly forms: SQXTN BD, HN; SQXTN HD, SN; SQXTN SD, DN; SQXTN VD.TA, VN.TB. Operands: rd, rn.

pub fn sqxtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sqxtn2Emitter<T0, T1>,

Emits the SQXTN2 instruction. Assembly forms: SQXTN2 VX.TA, VN.TB. Operands: operand_1, rn.

pub fn sqxtun<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SqxtunEmitter<T0, T1>,

Emits the SQXTUN instruction. Assembly forms: SQXTUN BD, HN; SQXTUN HD, SN; SQXTUN SD, DN; SQXTUN VD.TA, VN.TB. Operands: rd, rn.

pub fn sqxtun2<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sqxtun2Emitter<T0, T1>,

Emits the SQXTUN2 instruction. Assembly forms: SQXTUN2 VX.TA, VN.TB. Operands: operand_1, rn.

pub fn srhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SrhaddEmitter<T0, T1, T2>,

Emits the SRHADD instruction. Assembly forms: SRHADD VD.T, VN.T, VM.T; SRHADD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn sri<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: SriEmitter<T0, T1, T2>,

Emits the SRI instruction. Assembly forms: SRI DX, DN, #N; SRI VX.T, VN.T, #N; SRI VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn srshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SrshlEmitter<T0, T1, T2>,

Emits the SRSHL instruction. Assembly forms: SRSHL DD, DN, DM; SRSHL VD.T, VN.T, VM.T; SRSHL VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn srshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SrshrEmitter<T0, T1, T2>,

Emits the SRSHR instruction. Assembly forms: SRSHR DD, DN, #N; SRSHR VD.T, VN.T, #N; SRSHR VD.T, VN.T, #N. Operands: rd, rn, shift.

pub fn srsra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: SrsraEmitter<T0, T1, T2>,

Emits the SRSRA instruction. Assembly forms: SRSRA DX, DN, #N; SRSRA VX.T, VN.T, #N; SRSRA VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn sshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SshlEmitter<T0, T1, T2>,

Emits the SSHL instruction. Assembly forms: SSHL DD, DN, DM; SSHL VD.T, VN.T, VM.T; SSHL VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn sshll<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SshllEmitter<T0, T1, T2>,

Emits the SSHLL instruction. Assembly forms: SSHLL VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn sshll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: Sshll2Emitter<T0, T1, T2>,

Emits the SSHLL2 instruction. Assembly forms: SSHLL2 VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn sshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: SshrEmitter<T0, T1, T2>,

Emits the SSHR instruction. Assembly forms: SSHR DD, DN, #N; SSHR VD.T, VN.T, #N; SSHR VD.T, VN.T, #N. Operands: rd, rn, shift.

pub fn ssra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: SsraEmitter<T0, T1, T2>,

Emits the SSRA instruction. Assembly forms: SSRA DX, DN, #N; SSRA VX.T, VN.T, #N; SSRA VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn ssubl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SsublEmitter<T0, T1, T2>,

Emits the SSUBL instruction. Assembly forms: SSUBL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn ssubl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Ssubl2Emitter<T0, T1, T2>,

Emits the SSUBL2 instruction. Assembly forms: SSUBL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn ssubw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SsubwEmitter<T0, T1, T2>,

Emits the SSUBW instruction. Assembly forms: SSUBW VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn ssubw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Ssubw2Emitter<T0, T1, T2>,

Emits the SSUBW2 instruction. Assembly forms: SSUBW2 VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn st1<T0, T1>(&mut self, rs_or_operand_1: T0, addr: T1)

where Self: St1Emitter<T0, T1>,

Emits the ST1 instruction. Assembly forms: ST1 VS.B[#IDX], [XN|SP]; ST1 VS.H[#IDX], [XN|SP]; ST1 VS.S[#IDX], [XN|SP]; ST1 VS.D[#IDX], [XN|SP] (and related forms). Operands: rs_or_operand_1, addr.

pub fn st1_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)

where Self: St13Emitter<T0, T1, T2>,

Emits the ST1_3 instruction. Assembly forms: ST1 VS.B[#IDX], [XN|SP]; ST1 VS.H[#IDX], [XN|SP]; ST1 VS.S[#IDX], [XN|SP]; ST1 VS.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, addr.

pub fn st1_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)

where Self: St14Emitter<T0, T1, T2, T3>,

Emits the ST1_4 instruction. Assembly forms: ST1 VS.B[#IDX], [XN|SP]; ST1 VS.H[#IDX], [XN|SP]; ST1 VS.S[#IDX], [XN|SP]; ST1 VS.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, addr.

pub fn st1_5<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: St15Emitter<T0, T1, T2, T3, T4>,

Emits the ST1_5 instruction. Assembly forms: ST1 VS.B[#IDX], [XN|SP]; ST1 VS.H[#IDX], [XN|SP]; ST1 VS.S[#IDX], [XN|SP]; ST1 VS.D[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, rm2, addr.

pub fn st2<T0, T1, T2>(&mut self, rd: T0, rn: T1, addr: T2)

where Self: St2Emitter<T0, T1, T2>,

Emits the ST2 instruction. Assembly forms: ST2 2X{VS.B}+[#IDX], [XN|SP]; ST2 2X{VS.H}+[#IDX], [XN|SP]; ST2 2X{VS.S}+[#IDX], [XN|SP]; ST2 2X{VS.D}+[#IDX], [XN|SP] (and related forms). Operands: rd, rn, addr.

pub fn st3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, addr: T3)

where Self: St3Emitter<T0, T1, T2, T3>,

Emits the ST3 instruction. Assembly forms: ST3 3X{VS.B}+[#IDX], [XN|SP]; ST3 3X{VS.H}+[#IDX], [XN|SP]; ST3 3X{VS.S}+[#IDX], [XN|SP]; ST3 3X{VS.D}+[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, addr.

pub fn st4<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, addr: T4, )

where Self: St4Emitter<T0, T1, T2, T3, T4>,

Emits the ST4 instruction. Assembly forms: ST4 4X{VS.B}+[#IDX], [XN|SP]; ST4 4X{VS.H}+[#IDX], [XN|SP]; ST4 4X{VS.S}+[#IDX], [XN|SP]; ST4 4X{VS.D}+[#IDX], [XN|SP] (and related forms). Operands: rd, rn, rm1, rm2, addr.

pub fn subhn<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: SubhnEmitter<T0, T1, T2>,

Emits the SUBHN instruction. Assembly forms: SUBHN VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn subhn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Subhn2Emitter<T0, T1, T2>,

Emits the SUBHN2 instruction. Assembly forms: SUBHN2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn suqadd<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: SuqaddEmitter<T0, T1>,

Emits the SUQADD instruction. Assembly forms: SUQADD BX, BN; SUQADD HX, HN; SUQADD SX, SN; SUQADD DX, DN (and related forms). Operands: operand_1, rn.

pub fn sxtl<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: SxtlEmitter<T0, T1>,

Emits the SXTL instruction. Assembly forms: SXTL VD.TA, VN.TB. Operands: rd, rn.

pub fn sxtl2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Sxtl2Emitter<T0, T1>,

Emits the SXTL2 instruction. Assembly forms: SXTL2 VD.TA, VN.TB. Operands: rd, rn.

pub fn tbl<T0, T1, T2>(&mut self, rd: T0, rn_or_operand_2: T1, rm: T2)

where Self: TblEmitter<T0, T1, T2>,

Emits the TBL instruction. Assembly forms: TBL VD.8B, VN.16B, VM.8B; TBL VD.16B, VN.16B, VM.16B; TBL VD.8B, 2X{VN.16B}+, VM.8B; TBL VD.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn_or_operand_2, rm.

pub fn tbl_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3)

where Self: Tbl4Emitter<T0, T1, T2, T3>,

Emits the TBL_4 instruction. Assembly forms: TBL VD.8B, VN.16B, VM.8B; TBL VD.16B, VN.16B, VM.16B; TBL VD.8B, 2X{VN.16B}+, VM.8B; TBL VD.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2.

pub fn tbl_5<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, )

where Self: Tbl5Emitter<T0, T1, T2, T3, T4>,

Emits the TBL_5 instruction. Assembly forms: TBL VD.8B, VN.16B, VM.8B; TBL VD.16B, VN.16B, VM.16B; TBL VD.8B, 2X{VN.16B}+, VM.8B; TBL VD.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2, rm3.

pub fn tbl_6<T0, T1, T2, T3, T4, T5>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, rm4: T5, )

where Self: Tbl6Emitter<T0, T1, T2, T3, T4, T5>,

Emits the TBL_6 instruction. Assembly forms: TBL VD.8B, VN.16B, VM.8B; TBL VD.16B, VN.16B, VM.16B; TBL VD.8B, 2X{VN.16B}+, VM.8B; TBL VD.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2, rm3, rm4.

pub fn tbx<T0, T1, T2>(&mut self, operand_1: T0, rn_or_operand_2: T1, rm: T2)

where Self: TbxEmitter<T0, T1, T2>,

Emits the TBX instruction. Assembly forms: TBX VX.8B, VN.16B, VM.8B; TBX VX.16B, VN.16B, VM.16B; TBX VX.8B, 2X{VN.16B}+, VM.8B; TBX VX.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: operand_1, rn_or_operand_2, rm.

pub fn tbx_4<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm1: T2, rm2: T3)

where Self: Tbx4Emitter<T0, T1, T2, T3>,

Emits the TBX_4 instruction. Assembly forms: TBX VX.8B, VN.16B, VM.8B; TBX VX.16B, VN.16B, VM.16B; TBX VX.8B, 2X{VN.16B}+, VM.8B; TBX VX.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2.

pub fn tbx_5<T0, T1, T2, T3, T4>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, )

where Self: Tbx5Emitter<T0, T1, T2, T3, T4>,

Emits the TBX_5 instruction. Assembly forms: TBX VX.8B, VN.16B, VM.8B; TBX VX.16B, VN.16B, VM.16B; TBX VX.8B, 2X{VN.16B}+, VM.8B; TBX VX.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2, rm3.

pub fn tbx_6<T0, T1, T2, T3, T4, T5>( &mut self, rd: T0, rn: T1, rm1: T2, rm2: T3, rm3: T4, rm4: T5, )

where Self: Tbx6Emitter<T0, T1, T2, T3, T4, T5>,

Emits the TBX_6 instruction. Assembly forms: TBX VX.8B, VN.16B, VM.8B; TBX VX.16B, VN.16B, VM.16B; TBX VX.8B, 2X{VN.16B}+, VM.8B; TBX VX.16B, 2X{VN.16B}+, VM.16B (and related forms). Operands: rd, rn, rm1, rm2, rm3, rm4.

pub fn trn1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Trn1Emitter<T0, T1, T2>,

Emits the TRN1 instruction. Assembly forms: TRN1 VD.T, VN.T, VM.T; TRN1 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn trn2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Trn2Emitter<T0, T1, T2>,

Emits the TRN2 instruction. Assembly forms: TRN2 VD.T, VN.T, VM.T; TRN2 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn uaba<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UabaEmitter<T0, T1, T2>,

Emits the UABA instruction. Assembly forms: UABA VX.T, VN.T, VM.T; UABA VX.T, VN.T, VM.T. Operands: operand_1, rn, rm.

pub fn uabal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UabalEmitter<T0, T1, T2>,

Emits the UABAL instruction. Assembly forms: UABAL VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn uabal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Uabal2Emitter<T0, T1, T2>,

Emits the UABAL2 instruction. Assembly forms: UABAL2 VX.TA, VN.TB, VM.TB. Operands: operand_1, rn, rm.

pub fn uabd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UabdEmitter<T0, T1, T2>,

Emits the UABD instruction. Assembly forms: UABD VD.T, VN.T, VM.T; UABD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn uabdl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UabdlEmitter<T0, T1, T2>,

Emits the UABDL instruction. Assembly forms: UABDL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn uabdl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Uabdl2Emitter<T0, T1, T2>,

Emits the UABDL2 instruction. Assembly forms: UABDL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn uadalp<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: UadalpEmitter<T0, T1>,

Emits the UADALP instruction. Assembly forms: UADALP VX.TA, VN.TB; UADALP VX.TA, VN.TB. Operands: operand_1, rn.

pub fn uaddl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UaddlEmitter<T0, T1, T2>,

Emits the UADDL instruction. Assembly forms: UADDL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn uaddl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Uaddl2Emitter<T0, T1, T2>,

Emits the UADDL2 instruction. Assembly forms: UADDL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn uaddlp<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UaddlpEmitter<T0, T1>,

Emits the UADDLP instruction. Assembly forms: UADDLP VD.TA, VN.TB; UADDLP VD.TA, VN.TB. Operands: rd, rn.

pub fn uaddlv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UaddlvEmitter<T0, T1>,

Emits the UADDLV instruction. Assembly forms: UADDLV HD, VN.8B; UADDLV HD, VN.16B; UADDLV SD, VN.4H; UADDLV SD, VN.8H (and related forms). Operands: rd, rn.

pub fn uaddw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UaddwEmitter<T0, T1, T2>,

Emits the UADDW instruction. Assembly forms: UADDW VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn uaddw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Uaddw2Emitter<T0, T1, T2>,

Emits the UADDW2 instruction. Assembly forms: UADDW2 VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn ucvtf<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UcvtfEmitter<T0, T1>,

Emits the UCVTF instruction. Assembly forms: UCVTF SD, WN; UCVTF SD, WN, #FBITS; UCVTF SD, XN; UCVTF SD, XN, #FBITS (and related forms). Operands: rd, rn.

pub fn ucvtf_3<T0, T1, T2>(&mut self, rd: T0, rn: T1, fbits_or_bits: T2)

where Self: Ucvtf3Emitter<T0, T1, T2>,

Emits the UCVTF_3 instruction. Assembly forms: UCVTF SD, WN; UCVTF SD, WN, #FBITS; UCVTF SD, XN; UCVTF SD, XN, #FBITS (and related forms). Operands: rd, rn, fbits_or_bits.

pub fn uhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UhaddEmitter<T0, T1, T2>,

Emits the UHADD instruction. Assembly forms: UHADD VD.T, VN.T, VM.T; UHADD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn uhsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UhsubEmitter<T0, T1, T2>,

Emits the UHSUB instruction. Assembly forms: UHSUB VD.T, VN.T, VM.T; UHSUB VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn umaxp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmaxpEmitter<T0, T1, T2>,

Emits the UMAXP instruction. Assembly forms: UMAXP VD.T, VN.T, VM.T; UMAXP VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn umaxv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UmaxvEmitter<T0, T1>,

Emits the UMAXV instruction. Assembly forms: UMAXV BD, VN.8B; UMAXV BD, VN.16B; UMAXV HD, VN.4H; UMAXV HD, VN.8H (and related forms). Operands: rd, rn.

pub fn uminp<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UminpEmitter<T0, T1, T2>,

Emits the UMINP instruction. Assembly forms: UMINP VD.T, VN.T, VM.T; UMINP VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn uminv<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UminvEmitter<T0, T1>,

Emits the UMINV instruction. Assembly forms: UMINV BD, VN.8B; UMINV BD, VN.16B; UMINV HD, VN.4H; UMINV HD, VN.8H (and related forms). Operands: rd, rn.

pub fn umlal<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmlalEmitter<T0, T1, T2>,

Emits the UMLAL instruction. Assembly forms: UMLAL VD.TA, VN.TB, VM.TB; UMLAL VD.4S, VN.4H, VM.H[#IDX]; UMLAL VD.2D, VN.2S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn umlal2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Umlal2Emitter<T0, T1, T2>,

Emits the UMLAL2 instruction. Assembly forms: UMLAL2 VD.TA, VN.TB, VM.TB; UMLAL2 VD.4S, VN.8H, VM.H[#IDX]; UMLAL2 VD.2D, VN.4S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn umlsl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UmlslEmitter<T0, T1, T2>,

Emits the UMLSL instruction. Assembly forms: UMLSL VD.TA, VN.TB, VM.TB; UMLSL VD.4S, VN.4H, VM.H[#IDX]; UMLSL VD.2D, VN.2S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn umlsl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Umlsl2Emitter<T0, T1, T2>,

Emits the UMLSL2 instruction. Assembly forms: UMLSL2 VD.TA, VN.TB, VM.TB; UMLSL2 VD.4S, VN.8H, VM.H[#IDX]; UMLSL2 VD.2D, VN.4S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn umov<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UmovEmitter<T0, T1>,

Emits the UMOV instruction. Assembly forms: UMOV WD, VN.B[#IDX]; UMOV WD, VN.H[#IDX]; UMOV|MOV WD, VN.S[#IDX]; UMOV|MOV XD, VN.D[#IDX]. Operands: rd, rn.

pub fn umull2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Umull2Emitter<T0, T1, T2>,

Emits the UMULL2 instruction. Assembly forms: UMULL2 VD.TA, VN.TB, VM.TB; UMULL2 VD.4S, VN.8H, VM.H[#IDX]; UMULL2 VD.2D, VN.4S, VM.S[#IDX]. Operands: rd, rn, rm.

pub fn uqadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UqaddEmitter<T0, T1, T2>,

Emits the UQADD instruction. Assembly forms: UQADD BD, BN, BM; UQADD HD, HN, HM; UQADD SD, SN, SM; UQADD DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn uqrshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UqrshlEmitter<T0, T1, T2>,

Emits the UQRSHL instruction. Assembly forms: UQRSHL BD, BN, BM; UQRSHL HD, HN, HM; UQRSHL SD, SN, SM; UQRSHL DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn uqrshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: UqrshrnEmitter<T0, T1, T2>,

Emits the UQRSHRN instruction. Assembly forms: UQRSHRN BD, HN, #N; UQRSHRN HD, SN, #N; UQRSHRN SD, DN, #N; UQRSHRN VD.8B, VN.8H, #N (and related forms). Operands: rd, rn, shift.

pub fn uqrshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Uqrshrn2Emitter<T0, T1, T2>,

Emits the UQRSHRN2 instruction. Assembly forms: UQRSHRN2 VX.16B, VN.8H, #N; UQRSHRN2 VX.8H, VN.4S, #N; UQRSHRN2 VX.4S, VN.2D, #N. Operands: operand_1, rn, shift.

pub fn uqshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm_or_shift: T2)

where Self: UqshlEmitter<T0, T1, T2>,

Emits the UQSHL instruction. Assembly forms: UQSHL BD, BN, BM; UQSHL HD, HN, HM; UQSHL SD, SN, SM; UQSHL DD, DN, DM (and related forms). Operands: rd, rn, rm_or_shift.

pub fn uqshrn<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: UqshrnEmitter<T0, T1, T2>,

Emits the UQSHRN instruction. Assembly forms: UQSHRN BD, HN, #N; UQSHRN HD, SN, #N; UQSHRN SD, DN, #N; UQSHRN VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn uqshrn2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: Uqshrn2Emitter<T0, T1, T2>,

Emits the UQSHRN2 instruction. Assembly forms: UQSHRN2 VX.TA, VN.TB, #N. Operands: operand_1, rn, shift.

pub fn uqsub<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UqsubEmitter<T0, T1, T2>,

Emits the UQSUB instruction. Assembly forms: UQSUB BD, BN, BM; UQSUB HD, HN, HM; UQSUB SD, SN, SM; UQSUB DD, DN, DM (and related forms). Operands: rd, rn, rm.

pub fn uqxtn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UqxtnEmitter<T0, T1>,

Emits the UQXTN instruction. Assembly forms: UQXTN BD, HN; UQXTN HD, SN; UQXTN SD, DN; UQXTN VD.TA, VN.TB. Operands: rd, rn.

pub fn uqxtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Uqxtn2Emitter<T0, T1>,

Emits the UQXTN2 instruction. Assembly forms: UQXTN2 VX.TA, VN.TB. Operands: operand_1, rn.

pub fn urecpe<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UrecpeEmitter<T0, T1>,

Emits the URECPE instruction. Assembly forms: URECPE VD.2S, VN.2S; URECPE VD.4S, VN.4S. Operands: rd, rn.

pub fn urhadd<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UrhaddEmitter<T0, T1, T2>,

Emits the URHADD instruction. Assembly forms: URHADD VD.T, VN.T, VM.T; URHADD VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn urshl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UrshlEmitter<T0, T1, T2>,

Emits the URSHL instruction. Assembly forms: URSHL DD, DN, DM; URSHL VD.T, VN.T, VM.T; URSHL VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn urshr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: UrshrEmitter<T0, T1, T2>,

Emits the URSHR instruction. Assembly forms: URSHR DD, DN, #N; URSHR VD.T, VN.T, #N; URSHR VD.T, VN.T, #N. Operands: rd, rn, shift.

pub fn ursqrte<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UrsqrteEmitter<T0, T1>,

Emits the URSQRTE instruction. Assembly forms: URSQRTE VD.2S, VN.2S; URSQRTE VD.4S, VN.4S. Operands: rd, rn.

pub fn ursra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: UrsraEmitter<T0, T1, T2>,

Emits the URSRA instruction. Assembly forms: URSRA DX, DN, #N; URSRA VX.T, VN.T, #N; URSRA VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn ushl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UshlEmitter<T0, T1, T2>,

Emits the USHL instruction. Assembly forms: USHL DD, DN, DM; USHL VD.T, VN.T, VM.T; USHL VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn ushll<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: UshllEmitter<T0, T1, T2>,

Emits the USHLL instruction. Assembly forms: USHLL VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn ushll2<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: Ushll2Emitter<T0, T1, T2>,

Emits the USHLL2 instruction. Assembly forms: USHLL2 VD.TA, VN.TB, #N. Operands: rd, rn, shift.

pub fn ushr<T0, T1, T2>(&mut self, rd: T0, rn: T1, shift: T2)

where Self: UshrEmitter<T0, T1, T2>,

Emits the USHR instruction. Assembly forms: USHR DD, DN, #N; USHR VD.T, VN.T, #N; USHR VD.T, VN.T, #N. Operands: rd, rn, shift.

pub fn usqadd<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: UsqaddEmitter<T0, T1>,

Emits the USQADD instruction. Assembly forms: USQADD BX, BN; USQADD HX, HN; USQADD SX, SN; USQADD DX, DN (and related forms). Operands: operand_1, rn.

pub fn usra<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, shift: T2)

where Self: UsraEmitter<T0, T1, T2>,

Emits the USRA instruction. Assembly forms: USRA DX, DN, #N; USRA VX.T, VN.T, #N; USRA VX.T, VN.T, #N. Operands: operand_1, rn, shift.

pub fn usubl<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UsublEmitter<T0, T1, T2>,

Emits the USUBL instruction. Assembly forms: USUBL VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn usubl2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Usubl2Emitter<T0, T1, T2>,

Emits the USUBL2 instruction. Assembly forms: USUBL2 VD.TA, VN.TB, VM.TB. Operands: rd, rn, rm.

pub fn usubw<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: UsubwEmitter<T0, T1, T2>,

Emits the USUBW instruction. Assembly forms: USUBW VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn usubw2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Usubw2Emitter<T0, T1, T2>,

Emits the USUBW2 instruction. Assembly forms: USUBW2 VD.TA, VN.TA, VM.TB. Operands: rd, rn, rm.

pub fn uxtl<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: UxtlEmitter<T0, T1>,

Emits the UXTL instruction. Assembly forms: UXTL VD.TA, VN.TB. Operands: rd, rn.

pub fn uxtl2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Uxtl2Emitter<T0, T1>,

Emits the UXTL2 instruction. Assembly forms: UXTL2 VD.TA, VN.TB. Operands: rd, rn.

pub fn uzp1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Uzp1Emitter<T0, T1, T2>,

Emits the UZP1 instruction. Assembly forms: UZP1 VD.T, VN.T, VM.T; UZP1 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn uzp2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Uzp2Emitter<T0, T1, T2>,

Emits the UZP2 instruction. Assembly forms: UZP2 VD.T, VN.T, VM.T; UZP2 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn xtn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: XtnEmitter<T0, T1>,

Emits the XTN instruction. Assembly forms: XTN VD.TA, VN.TB. Operands: rd, rn.

pub fn xtn2<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Xtn2Emitter<T0, T1>,

Emits the XTN2 instruction. Assembly forms: XTN2 VX.TA, VN.TB. Operands: operand_1, rn.

pub fn zip1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Zip1Emitter<T0, T1, T2>,

Emits the ZIP1 instruction. Assembly forms: ZIP1 VD.T, VN.T, VM.T; ZIP1 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn zip2<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Zip2Emitter<T0, T1, T2>,

Emits the ZIP2 instruction. Assembly forms: ZIP2 VD.T, VN.T, VM.T; ZIP2 VD.T, VN.T, VM.T. Operands: rd, rn, rm.

pub fn aesd<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AesdEmitter<T0, T1>,

Emits the AESD instruction. Assembly forms: AESD VD.16B, VN.16B. Operands: rd, rn.

pub fn aese<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AeseEmitter<T0, T1>,

Emits the AESE instruction. Assembly forms: AESE VD.16B, VN.16B. Operands: rd, rn.

pub fn aesimc<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AesimcEmitter<T0, T1>,

Emits the AESIMC instruction. Assembly forms: AESIMC VD.16B, VN.16B. Operands: rd, rn.

pub fn aesmc<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: AesmcEmitter<T0, T1>,

Emits the AESMC instruction. Assembly forms: AESMC VD.16B, VN.16B. Operands: rd, rn.

pub fn sha1c<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha1cEmitter<T0, T1, T2>,

Emits the SHA1C instruction. Assembly forms: SHA1C QX, SN, VM.4S. Operands: operand_1, rn, rm.

pub fn sha1h<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Sha1hEmitter<T0, T1>,

Emits the SHA1H instruction. Assembly forms: SHA1H SD, SN. Operands: rd, rn.

pub fn sha1m<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha1mEmitter<T0, T1, T2>,

Emits the SHA1M instruction. Assembly forms: SHA1M QX, SN, VM.4S. Operands: operand_1, rn, rm.

pub fn sha1p<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha1pEmitter<T0, T1, T2>,

Emits the SHA1P instruction. Assembly forms: SHA1P QX, SN, VM.4S. Operands: operand_1, rn, rm.

pub fn sha1su0<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha1su0Emitter<T0, T1, T2>,

Emits the SHA1SU0 instruction. Assembly forms: SHA1SU0 VX.4S, VN.4S, VM.4S. Operands: operand_1, rn, rm.

pub fn sha1su1<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sha1su1Emitter<T0, T1>,

Emits the SHA1SU1 instruction. Assembly forms: SHA1SU1 VX.4S, VN.4S. Operands: operand_1, rn.

pub fn sha256h<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha256hEmitter<T0, T1, T2>,

Emits the SHA256H instruction. Assembly forms: SHA256H QX, QN, VM.4S. Operands: operand_1, rn, rm.

pub fn sha256h2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha256h2Emitter<T0, T1, T2>,

Emits the SHA256H2 instruction. Assembly forms: SHA256H2 QX, QN, VM.4S. Operands: operand_1, rn, rm.

pub fn sha256su0<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sha256su0Emitter<T0, T1>,

Emits the SHA256SU0 instruction. Assembly forms: SHA256SU0 VX.4S, VN.4S. Operands: operand_1, rn.

pub fn sha256su1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha256su1Emitter<T0, T1, T2>,

Emits the SHA256SU1 instruction. Assembly forms: SHA256SU1 VX.4S, VN.4S, VM.4S. Operands: operand_1, rn, rm.

pub fn sqrdmlah<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2)

where Self: SqrdmlahEmitter<T0, T1, T2>,

Emits the SQRDMLAH instruction. Assembly forms: SQRDMLAH HX, HN, HM; SQRDMLAH SX, SN, SM; SQRDMLAH HX, HN, VN.H[#IDX]; SQRDMLAH SX, SN, VN.S[#IDX] (and related forms). Operands: operand_1, rn, rm_or_rn.

pub fn sqrdmlsh<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm_or_rn: T2)

where Self: SqrdmlshEmitter<T0, T1, T2>,

Emits the SQRDMLSH instruction. Assembly forms: SQRDMLSH HX, HN, HM; SQRDMLSH SX, SN, SM; SQRDMLSH HX, HN, VN.H[#IDX]; SQRDMLSH SX, SN, VN.S[#IDX] (and related forms). Operands: operand_1, rn, rm_or_rn.

pub fn fcadd<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3)

where Self: FcaddEmitter<T0, T1, T2, T3>,

Emits the FCADD instruction. Assembly forms: FCADD VD.T, VN.T, VM.T, #ROTATE; FCADD VD.T, VN.T, VM.T, #ROTATE. Operands: rd, rn, rm, rotate.

pub fn fcmla<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, rotate: T3)

where Self: FcmlaEmitter<T0, T1, T2, T3>,

Emits the FCMLA instruction. Assembly forms: FCMLA VD.T, VN.T, VM.T, #ROTATE; FCMLA VD.T, VN.T, VM.T, #ROTATE; FCMLA VD.4H, VN.4H, VM.H[#IDX], #ROTATE; FCMLA VD.8H, VN.8H, VM.H[#IDX], #ROTATE (and related forms). Operands: rd, rn, rm, rotate.

pub fn fjcvtzs<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: FjcvtzsEmitter<T0, T1>,

Emits the FJCVTZS instruction. Assembly forms: FJCVTZS WD, DN. Operands: rd, rn.

pub fn fmlal<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: FmlalEmitter<T0, T1, T2>,

Emits the FMLAL instruction. Assembly forms: FMLAL VX.2S, VN.2H, VM.2H; FMLAL VX.4S, VN.4H, VM.4H; FMLAL VX.2S, VN.2H, VM.H[#IDX]; FMLAL VX.4S, VN.4H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn fmlal2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Fmlal2Emitter<T0, T1, T2>,

Emits the FMLAL2 instruction. Assembly forms: FMLAL2 VX.2S, VN.2H, VM.2H; FMLAL2 VX.4S, VN.4H, VM.4H; FMLAL2 VX.2S, VN.2H, VM.H[#IDX]; FMLAL2 VX.4S, VN.4H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn fmlsl<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: FmlslEmitter<T0, T1, T2>,

Emits the FMLSL instruction. Assembly forms: FMLSL VX.2S, VN.2H, VM.2H; FMLSL VX.4S, VN.4H, VM.4H; FMLSL VX.2S, VN.2H, VM.H[#IDX]; FMLSL VX.4S, VN.4H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn fmlsl2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Fmlsl2Emitter<T0, T1, T2>,

Emits the FMLSL2 instruction. Assembly forms: FMLSL2 VX.2S, VN.2H, VM.2H; FMLSL2 VX.4S, VN.4H, VM.4H; FMLSL2 VX.2S, VN.2H, VM.H[#IDX]; FMLSL2 VX.4S, VN.4H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn bcax<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: BcaxEmitter<T0, T1, T2, T3>,

Emits the BCAX instruction. Assembly forms: BCAX VD.16B, VN.16B, VM.16B, VA.16B. Operands: rd, rn, rm, operand_4.

pub fn eor3<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: Eor3Emitter<T0, T1, T2, T3>,

Emits the EOR3 instruction. Assembly forms: EOR3 VD.16B, VN.16B, VM.16B, VA.16B. Operands: rd, rn, rm, operand_4.

pub fn rax1<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Rax1Emitter<T0, T1, T2>,

Emits the RAX1 instruction. Assembly forms: RAX1 VD.2D, VN.2D, VM.2D. Operands: rd, rn, rm.

pub fn xar<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, imm: T3)

where Self: XarEmitter<T0, T1, T2, T3>,

Emits the XAR instruction. Assembly forms: XAR VD.2D, VN.2D, VM.2D, #IMM. Operands: rd, rn, rm, imm.

pub fn sha512h<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha512hEmitter<T0, T1, T2>,

Emits the SHA512H instruction. Assembly forms: SHA512H QX, QN, VM.2D. Operands: operand_1, rn, rm.

pub fn sha512h2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha512h2Emitter<T0, T1, T2>,

Emits the SHA512H2 instruction. Assembly forms: SHA512H2 QX, QN, VM.2D. Operands: operand_1, rn, rm.

pub fn sha512su0<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sha512su0Emitter<T0, T1>,

Emits the SHA512SU0 instruction. Assembly forms: SHA512SU0 VX.2D, VN.2D. Operands: operand_1, rn.

pub fn sha512su1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sha512su1Emitter<T0, T1, T2>,

Emits the SHA512SU1 instruction. Assembly forms: SHA512SU1 VX.2D, VN.2D, VM.2D. Operands: operand_1, rn, rm.

pub fn sm3partw1<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3partw1Emitter<T0, T1, T2>,

Emits the SM3PARTW1 instruction. Assembly forms: SM3PARTW1 VX.4S, VN.4S, VM.4S. Operands: operand_1, rn, rm.

pub fn sm3partw2<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3partw2Emitter<T0, T1, T2>,

Emits the SM3PARTW2 instruction. Assembly forms: SM3PARTW2 VX.4S, VN.4S, VM.4S. Operands: operand_1, rn, rm.

pub fn sm3ss1<T0, T1, T2, T3>(&mut self, rd: T0, rn: T1, rm: T2, operand_4: T3)

where Self: Sm3ss1Emitter<T0, T1, T2, T3>,

Emits the SM3SS1 instruction. Assembly forms: SM3SS1 VD.4S, VN.4S, VM.4S, VA.4S. Operands: rd, rn, rm, operand_4.

pub fn sm3tt1a<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3tt1aEmitter<T0, T1, T2>,

Emits the SM3TT1A instruction. Assembly forms: SM3TT1A VX.4S, VN.4S, VM.4[#IDX]. Operands: operand_1, rn, rm.

pub fn sm3tt1b<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3tt1bEmitter<T0, T1, T2>,

Emits the SM3TT1B instruction. Assembly forms: SM3TT1B VX.4S, VN.4S, VM.4[#IDX]. Operands: operand_1, rn, rm.

pub fn sm3tt2a<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3tt2aEmitter<T0, T1, T2>,

Emits the SM3TT2A instruction. Assembly forms: SM3TT2A VX.4S, VN.4S, VM.4[#IDX]. Operands: operand_1, rn, rm.

pub fn sm3tt2b<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: Sm3tt2bEmitter<T0, T1, T2>,

Emits the SM3TT2B instruction. Assembly forms: SM3TT2B VX.4S, VN.4S, VM.4[#IDX]. Operands: operand_1, rn, rm.

pub fn sm4e<T0, T1>(&mut self, operand_1: T0, rn: T1)

where Self: Sm4eEmitter<T0, T1>,

Emits the SM4E instruction. Assembly forms: SM4E VX.4S, VN.4S. Operands: operand_1, rn.

pub fn sm4ekey<T0, T1, T2>(&mut self, rd: T0, rn: T1, rm: T2)

where Self: Sm4ekeyEmitter<T0, T1, T2>,

Emits the SM4EKEY instruction. Assembly forms: SM4EKEY VD.4S, VN.4S, VM.4S. Operands: rd, rn, rm.

pub fn sdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SdotEmitter<T0, T1, T2>,

Emits the SDOT instruction. Assembly forms: SDOT VX.2S, VN.8B, VM.8B; SDOT VX.4S, VN.16B, VM.16B; SDOT VX.2S, VN.8B, VM.4B[#IDX]; SDOT VX.4S, VN.16B, VM.4B[#IDX]. Operands: operand_1, rn, rm.

pub fn udot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UdotEmitter<T0, T1, T2>,

Emits the UDOT instruction. Assembly forms: UDOT VX.2S, VN.8B, VM.8B; UDOT VX.4S, VN.16B, VM.16B; UDOT VX.2S, VN.8B, VM.4B[#IDX]; UDOT VX.4S, VN.16B, VM.4B[#IDX]. Operands: operand_1, rn, rm.

pub fn bfcvt<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: BfcvtEmitter<T0, T1>,

Emits the BFCVT instruction. Assembly forms: BFCVT HD, SN. Operands: rd, rn.

pub fn bfcvtn<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: BfcvtnEmitter<T0, T1>,

Emits the BFCVTN instruction. Assembly forms: BFCVTN VD.4H, VN.4S. Operands: rd, rn.

pub fn bfcvtn2<T0, T1>(&mut self, rd: T0, rn: T1)

where Self: Bfcvtn2Emitter<T0, T1>,

Emits the BFCVTN2 instruction. Assembly forms: BFCVTN2 VD.8H, VN.4S. Operands: rd, rn.

pub fn bfmlalb<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BfmlalbEmitter<T0, T1, T2>,

Emits the BFMLALB instruction. Assembly forms: BFMLALB VX.4S, VN.8H, VM.8H; BFMLALB VX.4S, VN.8H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn bfmlalt<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BfmlaltEmitter<T0, T1, T2>,

Emits the BFMLALT instruction. Assembly forms: BFMLALT VX.4S, VN.8H, VM.8H; BFMLALT VX.4S, VN.8H, VM.H[#IDX]. Operands: operand_1, rn, rm.

pub fn bfmmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BfmmlaEmitter<T0, T1, T2>,

Emits the BFMMLA instruction. Assembly forms: BFMMLA VX.4S, VN.8H, VM.8H. Operands: operand_1, rn, rm.

pub fn bfdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: BfdotEmitter<T0, T1, T2>,

Emits the BFDOT instruction. Assembly forms: BFDOT VX.2S, VN.4H, VM.4H; BFDOT VX.4S, VN.8H, VM.8H; BFDOT VX.2S, VN.4H, VM.2H[#IDX]; BFDOT VX.4S, VN.8H, VM.2H[#IDX]. Operands: operand_1, rn, rm.

pub fn smmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SmmlaEmitter<T0, T1, T2>,

Emits the SMMLA instruction. Assembly forms: SMMLA VX.4S, VN.16B, VM.16B. Operands: operand_1, rn, rm.

pub fn sudot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: SudotEmitter<T0, T1, T2>,

Emits the SUDOT instruction. Assembly forms: SUDOT VX.2S, VN.8B, VM.4B[#IDX]; SUDOT VX.4S, VN.16B, VM.4B[#IDX]. Operands: operand_1, rn, rm.

pub fn ummla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UmmlaEmitter<T0, T1, T2>,

Emits the UMMLA instruction. Assembly forms: UMMLA VX.4S, VN.16B, VM.16B. Operands: operand_1, rn, rm.

pub fn usdot<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UsdotEmitter<T0, T1, T2>,

Emits the USDOT instruction. Assembly forms: USDOT VX.2S, VN.8B, VM.TB; USDOT VX.4S, VN.16B, VM.TB; USDOT VX.2S, VN.8B, VM.4B[#IDX]; USDOT VX.4S, VN.16B, VM.4B[#IDX]. Operands: operand_1, rn, rm.

pub fn usmmla<T0, T1, T2>(&mut self, operand_1: T0, rn: T1, rm: T2)

where Self: UsmmlaEmitter<T0, T1, T2>,

Emits the USMMLA instruction. Assembly forms: USMMLA VX.4S, VN.16B, VM.16B. Operands: operand_1, rn, rm.

Trait Implementations

impl AbsEmitter<Gp, Gp> for Assembler<'_>

fn abs(&mut self, rd: Gp, rn: Gp)

impl AbsEmitter<Vec, Vec> for Assembler<'_>

fn abs(&mut self, rd: Vec, rn: Vec)

impl AdcEmitter<Gp, Gp, Gp> for Assembler<'_>

fn adc(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl AdcsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn adcs(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Add4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn add_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm)

impl Add4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn add_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm)

impl AddEmitter<Gp, Gp, Gp> for Assembler<'_>

fn add(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl AddEmitter<Gp, Gp, Imm> for Assembler<'_>

fn add(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl AddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn add(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl AddgEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn addg(&mut self, rd: Gp, rn: Gp, imm1: Imm, imm2: Imm)

impl Addhn2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn addhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl AddhnEmitter<Vec, Vec, Vec> for Assembler<'_>

fn addhn(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Addp3Emitter<Vec, Vec, Vec> for Assembler<'_>

fn addp_3(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl AddpEmitter<Vec, Vec> for Assembler<'_>

fn addp(&mut self, rd: Vec, rn: Vec)

impl Adds4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn adds_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm)

impl Adds4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn adds_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm)

impl AddsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn adds(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl AddsEmitter<Gp, Gp, Imm> for Assembler<'_>

fn adds(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl AddvEmitter<Vec, Vec> for Assembler<'_>

fn addv(&mut self, rd: Vec, rn: Vec)

impl AdrEmitter<Gp, Imm> for Assembler<'_>

fn adr(&mut self, rd: Gp, target: Imm)

impl AdrEmitter<Gp, Label> for Assembler<'_>

fn adr(&mut self, rd: Gp, target: Label)

impl AdrEmitter<Gp, Sym> for Assembler<'_>

fn adr(&mut self, rd: Gp, target: Sym)

impl AdrpEmitter<Gp, Imm> for Assembler<'_>

fn adrp(&mut self, rd: Gp, target: Imm)

impl AdrpEmitter<Gp, Label> for Assembler<'_>

fn adrp(&mut self, rd: Gp, target: Label)

impl AdrpEmitter<Gp, Sym> for Assembler<'_>

fn adrp(&mut self, rd: Gp, target: Sym)

impl AesdEmitter<Vec, Vec> for Assembler<'_>

fn aesd(&mut self, rd: Vec, rn: Vec)

impl AeseEmitter<Vec, Vec> for Assembler<'_>

fn aese(&mut self, rd: Vec, rn: Vec)

impl AesimcEmitter<Vec, Vec> for Assembler<'_>

fn aesimc(&mut self, rd: Vec, rn: Vec)

impl AesmcEmitter<Vec, Vec> for Assembler<'_>

fn aesmc(&mut self, rd: Vec, rn: Vec)

impl And4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn and__4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl AndEmitter<Gp, Gp, Gp> for Assembler<'_>

fn and_(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl AndEmitter<Gp, Gp, Imm> for Assembler<'_>

fn and_(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl AndEmitter<Vec, Vec, Vec> for Assembler<'_>

fn and_(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl Ands4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn ands_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl AndsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn ands(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl AndsEmitter<Gp, Gp, Imm> for Assembler<'_>

fn ands(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl AsrEmitter<Gp, Gp, Gp> for Assembler<'_>

fn asr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp)

impl AsrEmitter<Gp, Gp, Imm> for Assembler<'_>

fn asr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm)

impl AsrvEmitter<Gp, Gp, Gp> for Assembler<'_>

fn asrv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl AtEmitter<Imm, Gp> for Assembler<'_>

fn at(&mut self, at_op: Imm, rt: Gp)

impl AutdaEmitter<Gp, Gp> for Assembler<'_>

fn autda(&mut self, rd: Gp, rn: Gp)

impl AutdbEmitter<Gp, Gp> for Assembler<'_>

fn autdb(&mut self, rd: Gp, rn: Gp)

impl AutdzaEmitter<Gp> for Assembler<'_>

fn autdza(&mut self, rd: Gp)

impl AutdzbEmitter<Gp> for Assembler<'_>

fn autdzb(&mut self, rd: Gp)

impl Autia1716Emitter for Assembler<'_>

fn autia1716(&mut self)

impl AutiaEmitter<Gp, Gp> for Assembler<'_>

fn autia(&mut self, rd: Gp, rn: Gp)

impl AutiaspEmitter for Assembler<'_>

fn autiasp(&mut self)

impl AutiazEmitter for Assembler<'_>

fn autiaz(&mut self)

impl Autib1716Emitter for Assembler<'_>

fn autib1716(&mut self)

impl AutibEmitter<Gp, Gp> for Assembler<'_>

fn autib(&mut self, rd: Gp, rn: Gp)

impl AutibspEmitter for Assembler<'_>

fn autibsp(&mut self)

impl AutibzEmitter for Assembler<'_>

fn autibz(&mut self)

impl AutizaEmitter<Gp> for Assembler<'_>

fn autiza(&mut self, rd: Gp)

impl AutizbEmitter<Gp> for Assembler<'_>

fn autizb(&mut self, rd: Gp)

impl AxflagEmitter for Assembler<'_>

fn axflag(&mut self)

impl BEmitter<Imm> for Assembler<'_>

fn b(&mut self, target: Imm)

fn b_eq(&mut self, target: Imm)

fn b_ne(&mut self, target: Imm)

fn b_cs(&mut self, target: Imm)

fn b_hs(&mut self, target: Imm)

fn b_cc(&mut self, target: Imm)

fn b_lo(&mut self, target: Imm)

fn b_mi(&mut self, target: Imm)

fn b_pl(&mut self, target: Imm)

fn b_vs(&mut self, target: Imm)

fn b_vc(&mut self, target: Imm)

fn b_hi(&mut self, target: Imm)

fn b_ls(&mut self, target: Imm)

fn b_ge(&mut self, target: Imm)

fn b_lt(&mut self, target: Imm)

fn b_gt(&mut self, target: Imm)

fn b_le(&mut self, target: Imm)

fn b_al(&mut self, target: Imm)

impl BEmitter<Label> for Assembler<'_>

fn b(&mut self, target: Label)

fn b_eq(&mut self, target: Label)

fn b_ne(&mut self, target: Label)

fn b_cs(&mut self, target: Label)

fn b_hs(&mut self, target: Label)

fn b_cc(&mut self, target: Label)

fn b_lo(&mut self, target: Label)

fn b_mi(&mut self, target: Label)

fn b_pl(&mut self, target: Label)

fn b_vs(&mut self, target: Label)

fn b_vc(&mut self, target: Label)

fn b_hi(&mut self, target: Label)

fn b_ls(&mut self, target: Label)

fn b_ge(&mut self, target: Label)

fn b_lt(&mut self, target: Label)

fn b_gt(&mut self, target: Label)

fn b_le(&mut self, target: Label)

fn b_al(&mut self, target: Label)

impl BcEmitter<Imm> for Assembler<'_>

fn bc(&mut self, target: Imm)

fn bc_eq(&mut self, target: Imm)

fn bc_ne(&mut self, target: Imm)

fn bc_cs(&mut self, target: Imm)

fn bc_hs(&mut self, target: Imm)

fn bc_cc(&mut self, target: Imm)

fn bc_lo(&mut self, target: Imm)

fn bc_mi(&mut self, target: Imm)

fn bc_pl(&mut self, target: Imm)

fn bc_vs(&mut self, target: Imm)

fn bc_vc(&mut self, target: Imm)

fn bc_hi(&mut self, target: Imm)

fn bc_ls(&mut self, target: Imm)

fn bc_ge(&mut self, target: Imm)

fn bc_lt(&mut self, target: Imm)

fn bc_gt(&mut self, target: Imm)

fn bc_le(&mut self, target: Imm)

fn bc_al(&mut self, target: Imm)

impl BcEmitter<Label> for Assembler<'_>

fn bc(&mut self, target: Label)

fn bc_eq(&mut self, target: Label)

fn bc_ne(&mut self, target: Label)

fn bc_cs(&mut self, target: Label)

fn bc_hs(&mut self, target: Label)

fn bc_cc(&mut self, target: Label)

fn bc_lo(&mut self, target: Label)

fn bc_mi(&mut self, target: Label)

fn bc_pl(&mut self, target: Label)

fn bc_vs(&mut self, target: Label)

fn bc_vc(&mut self, target: Label)

fn bc_hi(&mut self, target: Label)

fn bc_ls(&mut self, target: Label)

fn bc_ge(&mut self, target: Label)

fn bc_lt(&mut self, target: Label)

fn bc_gt(&mut self, target: Label)

fn bc_le(&mut self, target: Label)

fn bc_al(&mut self, target: Label)

impl BcEmitter<Sym> for Assembler<'_>

fn bc(&mut self, target: Sym)

fn bc_eq(&mut self, target: Sym)

fn bc_ne(&mut self, target: Sym)

fn bc_cs(&mut self, target: Sym)

fn bc_hs(&mut self, target: Sym)

fn bc_cc(&mut self, target: Sym)

fn bc_lo(&mut self, target: Sym)

fn bc_mi(&mut self, target: Sym)

fn bc_pl(&mut self, target: Sym)

fn bc_vs(&mut self, target: Sym)

fn bc_vc(&mut self, target: Sym)

fn bc_hi(&mut self, target: Sym)

fn bc_ls(&mut self, target: Sym)

fn bc_ge(&mut self, target: Sym)

fn bc_lt(&mut self, target: Sym)

fn bc_gt(&mut self, target: Sym)

fn bc_le(&mut self, target: Sym)

fn bc_al(&mut self, target: Sym)

impl BcaxEmitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn bcax(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl BfcEmitter<Gp, Imm, Imm> for Assembler<'_>

fn bfc(&mut self, rd: Gp, lsb: Imm, width: Imm)

impl BfcvtEmitter<Vec, Vec> for Assembler<'_>

fn bfcvt(&mut self, rd: Vec, rn: Vec)

impl Bfcvtn2Emitter<Vec, Vec> for Assembler<'_>

fn bfcvtn2(&mut self, rd: Vec, rn: Vec)

impl BfcvtnEmitter<Vec, Vec> for Assembler<'_>

fn bfcvtn(&mut self, rd: Vec, rn: Vec)

impl BfdotEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bfdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BfiEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn bfi(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl BfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn bfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm)

impl BfmlalbEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bfmlalb(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BfmlaltEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bfmlalt(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BfmmlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bfmmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BfxilEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn bfxil(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl Bic2Emitter<Vec, Imm> for Assembler<'_>

fn bic_2(&mut self, rd: Vec, rn_or_imm: Imm)

impl Bic4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn bic_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl BicEmitter<Gp, Gp, Gp> for Assembler<'_>

fn bic(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_shift: Gp)

impl BicEmitter<Gp, Gp, Imm> for Assembler<'_>

fn bic(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_shift: Imm)

impl BicEmitter<Vec, Imm, Imm> for Assembler<'_>

fn bic(&mut self, rd: Vec, rn_or_imm: Imm, rm_or_shift: Imm)

impl BicEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bic(&mut self, rd: Vec, rn_or_imm: Vec, rm_or_shift: Vec)

impl Bics4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn bics_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl BicsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn bics(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl BicsEmitter<Gp, Gp, Imm> for Assembler<'_>

fn bics(&mut self, rd: Gp, rn: Gp, rm: Imm)

impl BifEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bif(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BitEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bit(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BlEmitter<Imm> for Assembler<'_>

fn bl(&mut self, target: Imm)

impl BlEmitter<Label> for Assembler<'_>

fn bl(&mut self, target: Label)

impl BlEmitter<Sym> for Assembler<'_>

fn bl(&mut self, target: Sym)

impl BlrEmitter<Gp> for Assembler<'_>

fn blr(&mut self, rn: Gp)

impl BrEmitter<Gp> for Assembler<'_>

fn br(&mut self, rn: Gp)

impl BrkEmitter<Imm> for Assembler<'_>

fn brk(&mut self, imm: Imm)

impl BslEmitter<Vec, Vec, Vec> for Assembler<'_>

fn bsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl BtiEmitter<Imm> for Assembler<'_>

fn bti(&mut self, targets: Imm)

impl CasEmitter<Gp, Gp, Mem> for Assembler<'_>

fn cas(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casa(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CasbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CashEmitter<Gp, Gp, Mem> for Assembler<'_>

fn cash(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CaslEmitter<Gp, Gp, Mem> for Assembler<'_>

fn casl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CaslbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn caslb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CaslhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn caslh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl CaspEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_>

fn casp(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem)

impl CaspaEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_>

fn caspa(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem)

impl CaspalEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_>

fn caspal(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem)

impl CasplEmitter<Gp, Gp, Gp, Gp, Mem> for Assembler<'_>

fn caspl(&mut self, rd: Gp, rn: Gp, rm1: Gp, rm2: Gp, addr: Mem)

impl CbnzEmitter<Gp, Imm> for Assembler<'_>

fn cbnz(&mut self, rn: Gp, target: Imm)

impl CbnzEmitter<Gp, Label> for Assembler<'_>

fn cbnz(&mut self, rn: Gp, target: Label)

impl CbnzEmitter<Gp, Sym> for Assembler<'_>

fn cbnz(&mut self, rn: Gp, target: Sym)

impl CbzEmitter<Gp, Imm> for Assembler<'_>

fn cbz(&mut self, rn: Gp, target: Imm)

impl CbzEmitter<Gp, Label> for Assembler<'_>

fn cbz(&mut self, rn: Gp, target: Label)

impl CbzEmitter<Gp, Sym> for Assembler<'_>

fn cbz(&mut self, rn: Gp, target: Sym)

impl CcmnEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn ccmn(&mut self, rn: Gp, rm_or_imm: Gp, flags: Imm, condition: Imm)

impl CcmnEmitter<Gp, Imm, Imm, Imm> for Assembler<'_>

fn ccmn(&mut self, rn: Gp, rm_or_imm: Imm, flags: Imm, condition: Imm)

impl CcmpEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn ccmp(&mut self, rn: Gp, rm_or_imm: Gp, flags: Imm, condition: Imm)

impl CcmpEmitter<Gp, Imm, Imm, Imm> for Assembler<'_>

fn ccmp(&mut self, rn: Gp, rm_or_imm: Imm, flags: Imm, condition: Imm)

impl CfinvEmitter for Assembler<'_>

fn cfinv(&mut self)

impl ChkfeatEmitter<Gp> for Assembler<'_>

fn chkfeat(&mut self, rd: Gp)

impl CincEmitter<Gp, Gp, Imm> for Assembler<'_>

fn cinc(&mut self, rd: Gp, rn: Gp, condition: Imm)

impl CinvEmitter<Gp, Gp, Imm> for Assembler<'_>

fn cinv(&mut self, rd: Gp, rn: Gp, condition: Imm)

impl ClrbhbEmitter for Assembler<'_>

fn clrbhb(&mut self)

impl ClrexEmitter<Imm> for Assembler<'_>

fn clrex(&mut self, imm: Imm)

impl ClsEmitter<Gp, Gp> for Assembler<'_>

fn cls(&mut self, rd: Gp, rn: Gp)

impl ClsEmitter<Vec, Vec> for Assembler<'_>

fn cls(&mut self, rd: Vec, rn: Vec)

impl ClzEmitter<Gp, Gp> for Assembler<'_>

fn clz(&mut self, rd: Gp, rn: Gp)

impl ClzEmitter<Vec, Vec> for Assembler<'_>

fn clz(&mut self, rd: Vec, rn: Vec)

impl CmeqEmitter<Vec, Vec, Imm> for Assembler<'_>

fn cmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl CmeqEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl CmgeEmitter<Vec, Vec, Imm> for Assembler<'_>

fn cmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl CmgeEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl CmgtEmitter<Vec, Vec, Imm> for Assembler<'_>

fn cmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl CmgtEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl CmhiEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmhi(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl CmhsEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmhs(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl CmleEmitter<Vec, Vec, Imm> for Assembler<'_>

fn cmle(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl CmltEmitter<Vec, Vec, Imm> for Assembler<'_>

fn cmlt(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl Cmn3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn cmn_3(&mut self, rn: Gp, imm_or_rm: Gp, shift: Imm)

impl Cmn3Emitter<Gp, Imm, Imm> for Assembler<'_>

fn cmn_3(&mut self, rn: Gp, imm_or_rm: Imm, shift: Imm)

impl CmnEmitter<Gp, Gp> for Assembler<'_>

fn cmn(&mut self, rn: Gp, imm_or_rm: Gp)

impl CmnEmitter<Gp, Imm> for Assembler<'_>

fn cmn(&mut self, rn: Gp, imm_or_rm: Imm)

impl Cmp3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn cmp_3(&mut self, rn: Gp, rm_or_imm: Gp, shift: Imm)

impl Cmp3Emitter<Gp, Imm, Imm> for Assembler<'_>

fn cmp_3(&mut self, rn: Gp, rm_or_imm: Imm, shift: Imm)

impl CmpEmitter<Gp, Gp> for Assembler<'_>

fn cmp(&mut self, rn: Gp, rm_or_imm: Gp)

impl CmpEmitter<Gp, Imm> for Assembler<'_>

fn cmp(&mut self, rn: Gp, rm_or_imm: Imm)

impl CmppEmitter<Gp, Gp> for Assembler<'_>

fn cmpp(&mut self, rn: Gp, rm: Gp)

impl CmtstEmitter<Vec, Vec, Vec> for Assembler<'_>

fn cmtst(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl CnegEmitter<Gp, Gp, Imm> for Assembler<'_>

fn cneg(&mut self, rd: Gp, rn: Gp, condition: Imm)

impl CntEmitter<Gp, Gp> for Assembler<'_>

fn cnt(&mut self, rd: Gp, rn: Gp)

impl CntEmitter<Vec, Vec> for Assembler<'_>

fn cnt(&mut self, rd: Vec, rn: Vec)

impl Crc32bEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32b(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32cbEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32cb(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32chEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32ch(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32cwEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32cw(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32cxEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32cx(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32hEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32h(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32wEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32w(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Crc32xEmitter<Gp, Gp, Gp> for Assembler<'_>

fn crc32x(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl CsdbEmitter for Assembler<'_>

fn csdb(&mut self)

impl CselEmitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn csel(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm)

impl CsetEmitter<Gp, Imm> for Assembler<'_>

fn cset(&mut self, rd: Gp, condition: Imm)

impl CsetmEmitter<Gp, Imm> for Assembler<'_>

fn csetm(&mut self, rd: Gp, condition: Imm)

impl CsincEmitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn csinc(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm)

impl CsinvEmitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn csinv(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm)

impl CsnegEmitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn csneg(&mut self, rd: Gp, rn: Gp, rm: Gp, condition: Imm)

impl CtzEmitter<Gp, Gp> for Assembler<'_>

fn ctz(&mut self, rd: Gp, rn: Gp)

impl DcEmitter<Imm, Gp> for Assembler<'_>

fn dc(&mut self, dc_op: Imm, rt: Gp)

impl Dcps1Emitter<Imm> for Assembler<'_>

fn dcps1(&mut self, imm: Imm)

impl Dcps2Emitter<Imm> for Assembler<'_>

fn dcps2(&mut self, imm: Imm)

impl Dcps3Emitter<Imm> for Assembler<'_>

fn dcps3(&mut self, imm: Imm)

impl DghEmitter for Assembler<'_>

fn dgh(&mut self)

impl DmbEmitter<Imm> for Assembler<'_>

fn dmb(&mut self, barrier_op: Imm)

impl DrpsEmitter for Assembler<'_>

fn drps(&mut self)

impl DsbEmitter<Imm> for Assembler<'_>

fn dsb(&mut self, barrier_op: Imm)

impl DupEmitter<Vec, Gp> for Assembler<'_>

fn dup(&mut self, rd: Vec, rn: Gp)

impl DupEmitter<Vec, Vec> for Assembler<'_>

fn dup(&mut self, rd: Vec, rn: Vec)

impl Eon4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn eon_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl EonEmitter<Gp, Gp, Gp> for Assembler<'_>

fn eon(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Eor3Emitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn eor3(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl Eor4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn eor_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl EorEmitter<Gp, Gp, Gp> for Assembler<'_>

fn eor(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl EorEmitter<Gp, Gp, Imm> for Assembler<'_>

fn eor(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl EorEmitter<Vec, Vec, Vec> for Assembler<'_>

fn eor(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl EretEmitter for Assembler<'_>

fn eret(&mut self)

impl EsbEmitter for Assembler<'_>

fn esb(&mut self)

impl ExtEmitter<Vec, Vec, Vec, Imm> for Assembler<'_>

fn ext(&mut self, rd: Vec, rn: Vec, rm: Vec, idx: Imm)

impl ExtrEmitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn extr(&mut self, rd: Gp, rn: Gp, rm: Gp, imm: Imm)

impl FabdEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fabd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FabsEmitter<Vec, Vec> for Assembler<'_>

fn fabs(&mut self, rd: Vec, rn: Vec)

impl FacgeEmitter<Vec, Vec, Vec> for Assembler<'_>

fn facge(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FacgtEmitter<Vec, Vec, Vec> for Assembler<'_>

fn facgt(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Faddp3Emitter<Vec, Vec, Vec> for Assembler<'_>

fn faddp_3(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FaddpEmitter<Vec, Vec> for Assembler<'_>

fn faddp(&mut self, rd: Vec, rn: Vec)

impl FcaddEmitter<Vec, Vec, Vec, Imm> for Assembler<'_>

fn fcadd(&mut self, rd: Vec, rn: Vec, rm: Vec, rotate: Imm)

impl FccmpEmitter<Vec, Vec, Imm, Imm> for Assembler<'_>

fn fccmp(&mut self, rn: Vec, rm: Vec, flags: Imm, condition: Imm)

impl FccmpeEmitter<Vec, Vec, Imm, Imm> for Assembler<'_>

fn fccmpe(&mut self, rn: Vec, rm: Vec, flags: Imm, condition: Imm)

impl FcmeqEmitter<Vec, Vec, Imm> for Assembler<'_>

fn fcmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl FcmeqEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fcmeq(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl FcmgeEmitter<Vec, Vec, Imm> for Assembler<'_>

fn fcmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl FcmgeEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fcmge(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl FcmgtEmitter<Vec, Vec, Imm> for Assembler<'_>

fn fcmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Imm)

impl FcmgtEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fcmgt(&mut self, rd: Vec, rn: Vec, rm_or_operand_3: Vec)

impl FcmlaEmitter<Vec, Vec, Vec, Imm> for Assembler<'_>

fn fcmla(&mut self, rd: Vec, rn: Vec, rm: Vec, rotate: Imm)

impl FcmleEmitter<Vec, Vec, Imm> for Assembler<'_>

fn fcmle(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl FcmltEmitter<Vec, Vec, Imm> for Assembler<'_>

fn fcmlt(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl FcmpEmitter<Vec, Imm> for Assembler<'_>

fn fcmp(&mut self, rn: Vec, rm_or_operand_2: Imm)

impl FcmpEmitter<Vec, Vec> for Assembler<'_>

fn fcmp(&mut self, rn: Vec, rm_or_operand_2: Vec)

impl FcmpeEmitter<Vec, Imm> for Assembler<'_>

fn fcmpe(&mut self, rn: Vec, rm_or_operand_2: Imm)

impl FcmpeEmitter<Vec, Vec> for Assembler<'_>

fn fcmpe(&mut self, rn: Vec, rm_or_operand_2: Vec)

impl FcselEmitter<Vec, Vec, Vec, Imm> for Assembler<'_>

fn fcsel(&mut self, rd: Vec, rn: Vec, rm: Vec, condition: Imm)

impl FcvtEmitter<Vec, Vec> for Assembler<'_>

fn fcvt(&mut self, rd: Vec, rn: Vec)

impl FcvtasEmitter<Gp, Vec> for Assembler<'_>

fn fcvtas(&mut self, rd: Gp, rn: Vec)

impl FcvtasEmitter<Vec, Vec> for Assembler<'_>

fn fcvtas(&mut self, rd: Vec, rn: Vec)

impl FcvtauEmitter<Gp, Vec> for Assembler<'_>

fn fcvtau(&mut self, rd: Gp, rn: Vec)

impl FcvtauEmitter<Vec, Vec> for Assembler<'_>

fn fcvtau(&mut self, rd: Vec, rn: Vec)

impl Fcvtl2Emitter<Vec, Vec> for Assembler<'_>

fn fcvtl2(&mut self, rd: Vec, rn: Vec)

impl FcvtlEmitter<Vec, Vec> for Assembler<'_>

fn fcvtl(&mut self, rd: Vec, rn: Vec)

impl FcvtmsEmitter<Gp, Vec> for Assembler<'_>

fn fcvtms(&mut self, rd: Gp, rn: Vec)

impl FcvtmsEmitter<Vec, Vec> for Assembler<'_>

fn fcvtms(&mut self, rd: Vec, rn: Vec)

impl FcvtmuEmitter<Gp, Vec> for Assembler<'_>

fn fcvtmu(&mut self, rd: Gp, rn: Vec)

impl FcvtmuEmitter<Vec, Vec> for Assembler<'_>

fn fcvtmu(&mut self, rd: Vec, rn: Vec)

impl Fcvtn2Emitter<Vec, Vec> for Assembler<'_>

fn fcvtn2(&mut self, rd_or_operand_1: Vec, rn: Vec)

impl FcvtnEmitter<Vec, Vec> for Assembler<'_>

fn fcvtn(&mut self, rd: Vec, rn: Vec)

impl FcvtnsEmitter<Gp, Vec> for Assembler<'_>

fn fcvtns(&mut self, rd: Gp, rn: Vec)

impl FcvtnsEmitter<Vec, Vec> for Assembler<'_>

fn fcvtns(&mut self, rd: Vec, rn: Vec)

impl FcvtnuEmitter<Gp, Vec> for Assembler<'_>

fn fcvtnu(&mut self, rd: Gp, rn: Vec)

impl FcvtnuEmitter<Vec, Vec> for Assembler<'_>

fn fcvtnu(&mut self, rd: Vec, rn: Vec)

impl FcvtpsEmitter<Gp, Vec> for Assembler<'_>

fn fcvtps(&mut self, rd: Gp, rn: Vec)

impl FcvtpsEmitter<Vec, Vec> for Assembler<'_>

fn fcvtps(&mut self, rd: Vec, rn: Vec)

impl FcvtpuEmitter<Gp, Vec> for Assembler<'_>

fn fcvtpu(&mut self, rd: Gp, rn: Vec)

impl FcvtpuEmitter<Vec, Vec> for Assembler<'_>

fn fcvtpu(&mut self, rd: Vec, rn: Vec)

impl Fcvtxn2Emitter<Vec, Vec> for Assembler<'_>

fn fcvtxn2(&mut self, rd: Vec, rn: Vec)

impl FcvtxnEmitter<Vec, Vec> for Assembler<'_>

fn fcvtxn(&mut self, rd: Vec, rn: Vec)

impl Fcvtzs3Emitter<Gp, Vec, Imm> for Assembler<'_>

fn fcvtzs_3(&mut self, rd: Gp, rn: Vec, fbits: Imm)

impl Fcvtzs3Emitter<Vec, Vec, Imm> for Assembler<'_>

fn fcvtzs_3(&mut self, rd: Vec, rn: Vec, fbits: Imm)

impl FcvtzsEmitter<Gp, Vec> for Assembler<'_>

fn fcvtzs(&mut self, rd: Gp, rn: Vec)

impl FcvtzsEmitter<Vec, Vec> for Assembler<'_>

fn fcvtzs(&mut self, rd: Vec, rn: Vec)

impl Fcvtzu3Emitter<Gp, Vec, Imm> for Assembler<'_>

fn fcvtzu_3(&mut self, rd: Gp, rn: Vec, fbits: Imm)

impl Fcvtzu3Emitter<Vec, Vec, Imm> for Assembler<'_>

fn fcvtzu_3(&mut self, rd: Vec, rn: Vec, fbits: Imm)

impl FcvtzuEmitter<Gp, Vec> for Assembler<'_>

fn fcvtzu(&mut self, rd: Gp, rn: Vec)

impl FcvtzuEmitter<Vec, Vec> for Assembler<'_>

fn fcvtzu(&mut self, rd: Vec, rn: Vec)

impl FdivEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fdiv(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FjcvtzsEmitter<Gp, Vec> for Assembler<'_>

fn fjcvtzs(&mut self, rd: Gp, rn: Vec)

impl FmaddEmitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn fmadd(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl FmaxEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmax(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FmaxnmEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmaxnm(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Fmaxnmp2Emitter<Vec, Vec> for Assembler<'_>

fn fmaxnmp_2(&mut self, rd: Vec, rn: Vec)

impl FmaxnmpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmaxnmp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FmaxnmvEmitter<Vec, Vec> for Assembler<'_>

fn fmaxnmv(&mut self, rd: Vec, rn: Vec)

impl Fmaxp2Emitter<Vec, Vec> for Assembler<'_>

fn fmaxp_2(&mut self, rd: Vec, rn: Vec)

impl FmaxpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmaxp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FmaxvEmitter<Vec, Vec> for Assembler<'_>

fn fmaxv(&mut self, rd: Vec, rn: Vec)

impl FminEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmin(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FminnmEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fminnm(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Fminnmp2Emitter<Vec, Vec> for Assembler<'_>

fn fminnmp_2(&mut self, rd: Vec, rn: Vec)

impl FminnmpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fminnmp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FminnmvEmitter<Vec, Vec> for Assembler<'_>

fn fminnmv(&mut self, rd: Vec, rn: Vec)

impl Fminp3Emitter<Vec, Vec, Vec> for Assembler<'_>

fn fminp_3(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FminpEmitter<Vec, Vec> for Assembler<'_>

fn fminp(&mut self, rd: Vec, rn: Vec)

impl FminvEmitter<Vec, Vec> for Assembler<'_>

fn fminv(&mut self, rd: Vec, rn: Vec)

impl FmlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Fmlal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn fmlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl FmlalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl FmlsEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmls(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Fmlsl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn fmlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl FmlslEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl FmovEmitter<Gp, Vec> for Assembler<'_>

fn fmov(&mut self, rd: Gp, rn_or_fimm: Vec)

impl FmovEmitter<Vec, Gp> for Assembler<'_>

fn fmov(&mut self, rd: Vec, rn_or_fimm: Gp)

impl FmovEmitter<Vec, Imm> for Assembler<'_>

fn fmov(&mut self, rd: Vec, rn_or_fimm: Imm)

impl FmovEmitter<Vec, Vec> for Assembler<'_>

fn fmov(&mut self, rd: Vec, rn_or_fimm: Vec)

impl FmsubEmitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn fmsub(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl FmulEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmul(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FmulxEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fmulx(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FnegEmitter<Vec, Vec> for Assembler<'_>

fn fneg(&mut self, rd: Vec, rn: Vec)

impl FnmaddEmitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn fnmadd(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl FnmsubEmitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn fnmsub(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl FnmulEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fnmul(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FrecpeEmitter<Vec, Vec> for Assembler<'_>

fn frecpe(&mut self, rd: Vec, rn: Vec)

impl FrecpsEmitter<Vec, Vec, Vec> for Assembler<'_>

fn frecps(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FrecpxEmitter<Vec, Vec> for Assembler<'_>

fn frecpx(&mut self, rd: Vec, rn: Vec)

impl Frint32xEmitter<Vec, Vec> for Assembler<'_>

fn frint32x(&mut self, rd: Vec, rn: Vec)

impl Frint32zEmitter<Vec, Vec> for Assembler<'_>

fn frint32z(&mut self, rd: Vec, rn: Vec)

impl Frint64xEmitter<Vec, Vec> for Assembler<'_>

fn frint64x(&mut self, rd: Vec, rn: Vec)

impl Frint64zEmitter<Vec, Vec> for Assembler<'_>

fn frint64z(&mut self, rd: Vec, rn: Vec)

impl FrintaEmitter<Vec, Vec> for Assembler<'_>

fn frinta(&mut self, rd: Vec, rn: Vec)

impl FrintiEmitter<Vec, Vec> for Assembler<'_>

fn frinti(&mut self, rd: Vec, rn: Vec)

impl FrintmEmitter<Vec, Vec> for Assembler<'_>

fn frintm(&mut self, rd: Vec, rn: Vec)

impl FrintnEmitter<Vec, Vec> for Assembler<'_>

fn frintn(&mut self, rd: Vec, rn: Vec)

impl FrintpEmitter<Vec, Vec> for Assembler<'_>

fn frintp(&mut self, rd: Vec, rn: Vec)

impl FrintxEmitter<Vec, Vec> for Assembler<'_>

fn frintx(&mut self, rd: Vec, rn: Vec)

impl FrintzEmitter<Vec, Vec> for Assembler<'_>

fn frintz(&mut self, rd: Vec, rn: Vec)

impl FrsqrteEmitter<Vec, Vec> for Assembler<'_>

fn frsqrte(&mut self, rd: Vec, rn: Vec)

impl FrsqrtsEmitter<Vec, Vec, Vec> for Assembler<'_>

fn frsqrts(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl FsqrtEmitter<Vec, Vec> for Assembler<'_>

fn fsqrt(&mut self, rd: Vec, rn: Vec)

impl FsubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn fsub(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl GmiEmitter<Gp, Gp, Gp> for Assembler<'_>

fn gmi(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl HintEmitter<Imm> for Assembler<'_>

fn hint(&mut self, imm: Imm)

impl HltEmitter<Imm> for Assembler<'_>

fn hlt(&mut self, imm: Imm)

impl HvcEmitter<Imm> for Assembler<'_>

fn hvc(&mut self, imm: Imm)

impl IcEmitter<Imm, Gp> for Assembler<'_>

fn ic(&mut self, ic_op: Imm, rt: Gp)

impl InsEmitter<Vec, Gp> for Assembler<'_>

fn ins(&mut self, rd: Vec, rn: Gp)

impl InsEmitter<Vec, Vec> for Assembler<'_>

fn ins(&mut self, rd: Vec, rn: Vec)

impl InstSink for Assembler<'_>

fn arch(&self) -> Arch

Target architecture accepted by this sink.

fn emit_inst(&mut self, inst: &Inst) -> Result<(), AsmError>

Emits one recorded instruction.

fn bind_label(&mut self, label: Label) -> Result<(), AsmError>

Binds a label at the current position.

impl IsbEmitter<Imm> for Assembler<'_>

fn isb(&mut self, isb_op: Imm)

impl Ld1Emitter<Vec, Mem> for Assembler<'_>

fn ld1(&mut self, idx_or_operand_1: Vec, addr: Mem)

impl Ld1rEmitter<Vec, Mem> for Assembler<'_>

fn ld1r(&mut self, operand_1: Vec, addr: Mem)

impl Ld2Emitter<Vec, Vec, Mem> for Assembler<'_>

fn ld2(&mut self, rd: Vec, rn: Vec, addr: Mem)

impl Ld2rEmitter<Vec, Vec, Mem> for Assembler<'_>

fn ld2r(&mut self, rd: Vec, rn: Vec, addr: Mem)

impl Ld3Emitter<Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld3(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem)

impl Ld3rEmitter<Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld3r(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem)

impl Ld4Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem)

impl Ld4rEmitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld4r(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem)

impl Ld13Emitter<Vec, Vec, Mem> for Assembler<'_>

fn ld1_3(&mut self, rd: Vec, rn: Vec, addr: Mem)

impl Ld14Emitter<Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld1_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem)

impl Ld15Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_>

fn ld1_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem)

impl LdaddEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldadd(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldadda(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdaddlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaddlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdarEmitter<Gp, Mem> for Assembler<'_>

fn ldar(&mut self, rd: Gp, addr: Mem)

impl LdarbEmitter<Gp, Mem> for Assembler<'_>

fn ldarb(&mut self, rd: Gp, addr: Mem)

impl LdarhEmitter<Gp, Mem> for Assembler<'_>

fn ldarh(&mut self, rd: Gp, addr: Mem)

impl LdaxpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldaxp(&mut self, rd: Gp, rd2: Gp, addr: Mem)

impl LdaxrEmitter<Gp, Mem> for Assembler<'_>

fn ldaxr(&mut self, rd: Gp, addr: Mem)

impl LdaxrbEmitter<Gp, Mem> for Assembler<'_>

fn ldaxrb(&mut self, rd: Gp, addr: Mem)

impl LdaxrhEmitter<Gp, Mem> for Assembler<'_>

fn ldaxrh(&mut self, rd: Gp, addr: Mem)

impl LdclrEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclr(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclraEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclra(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclralEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclral(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclralbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclralb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclralhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclralh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdclrlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldclrlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeor(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeoraEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeora(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeoralEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeoral(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeoralbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeoralb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeoralhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeoralh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdeorlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldeorlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdgEmitter<Gp, Mem> for Assembler<'_>

fn ldg(&mut self, rd: Gp, addr: Mem)

impl LdgmEmitter<Gp, Mem> for Assembler<'_>

fn ldgm(&mut self, rd: Gp, addr: Mem)

impl LdlarEmitter<Gp, Mem> for Assembler<'_>

fn ldlar(&mut self, rd: Gp, addr: Mem)

impl LdlarbEmitter<Gp, Mem> for Assembler<'_>

fn ldlarb(&mut self, rd: Gp, addr: Mem)

impl LdlarhEmitter<Gp, Mem> for Assembler<'_>

fn ldlarh(&mut self, rd: Gp, addr: Mem)

impl LdnpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldnp(&mut self, rd: Gp, rd2: Gp, addr: Mem)

impl LdnpEmitter<Vec, Vec, Mem> for Assembler<'_>

fn ldnp(&mut self, rd: Vec, rd2: Vec, addr: Mem)

impl LdpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldp(&mut self, rd: Gp, rd2: Gp, addr: Mem)

impl LdpEmitter<Vec, Vec, Mem> for Assembler<'_>

fn ldp(&mut self, rd: Vec, rd2: Vec, addr: Mem)

impl LdpswEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldpsw(&mut self, rd: Gp, rd2: Gp, addr: Mem)

impl LdrEmitter<Gp, Mem> for Assembler<'_>

fn ldr(&mut self, rd: Gp, addr: Mem)

impl LdrEmitter<Vec, Mem> for Assembler<'_>

fn ldr(&mut self, rd: Vec, addr: Mem)

impl LdraaEmitter<Gp, Mem> for Assembler<'_>

fn ldraa(&mut self, rd: Gp, addr: Mem)

impl LdrabEmitter<Gp, Mem> for Assembler<'_>

fn ldrab(&mut self, rd: Gp, addr: Mem)

impl LdrbEmitter<Gp, Mem> for Assembler<'_>

fn ldrb(&mut self, rd: Gp, addr: Mem)

impl LdrhEmitter<Gp, Mem> for Assembler<'_>

fn ldrh(&mut self, rd: Gp, addr: Mem)

impl LdrsbEmitter<Gp, Mem> for Assembler<'_>

fn ldrsb(&mut self, rd: Gp, addr: Mem)

impl LdrshEmitter<Gp, Mem> for Assembler<'_>

fn ldrsh(&mut self, rd: Gp, addr: Mem)

impl LdrswEmitter<Gp, Mem> for Assembler<'_>

fn ldrsw(&mut self, rd: Gp, addr: Mem)

impl LdsetEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldset(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldseta(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsethEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldseth(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsetlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsetlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmax(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxa(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsmaxlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmaxlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmin(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsmina(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdsminlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldsminlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdtrEmitter<Gp, Mem> for Assembler<'_>

fn ldtr(&mut self, rd: Gp, addr: Mem)

impl LdtrbEmitter<Gp, Mem> for Assembler<'_>

fn ldtrb(&mut self, rd: Gp, addr: Mem)

impl LdtrhEmitter<Gp, Mem> for Assembler<'_>

fn ldtrh(&mut self, rd: Gp, addr: Mem)

impl LdtrsbEmitter<Gp, Mem> for Assembler<'_>

fn ldtrsb(&mut self, rd: Gp, addr: Mem)

impl LdtrshEmitter<Gp, Mem> for Assembler<'_>

fn ldtrsh(&mut self, rd: Gp, addr: Mem)

impl LdtrswEmitter<Gp, Mem> for Assembler<'_>

fn ldtrsw(&mut self, rd: Gp, addr: Mem)

impl LdumaxEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumax(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxa(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdumaxlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumaxlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumin(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldumina(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminlEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminlbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminlb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LduminlhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn lduminlh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl LdurEmitter<Gp, Mem> for Assembler<'_>

fn ldur(&mut self, rd: Gp, addr: Mem)

impl LdurEmitter<Vec, Mem> for Assembler<'_>

fn ldur(&mut self, rd: Vec, addr: Mem)

impl LdurbEmitter<Gp, Mem> for Assembler<'_>

fn ldurb(&mut self, rd: Gp, addr: Mem)

impl LdurhEmitter<Gp, Mem> for Assembler<'_>

fn ldurh(&mut self, rd: Gp, addr: Mem)

impl LdursbEmitter<Gp, Mem> for Assembler<'_>

fn ldursb(&mut self, rd: Gp, addr: Mem)

impl LdurshEmitter<Gp, Mem> for Assembler<'_>

fn ldursh(&mut self, rd: Gp, addr: Mem)

impl LdurswEmitter<Gp, Mem> for Assembler<'_>

fn ldursw(&mut self, rd: Gp, addr: Mem)

impl LdxpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn ldxp(&mut self, rd: Gp, rd2: Gp, addr: Mem)

impl LdxrEmitter<Gp, Mem> for Assembler<'_>

fn ldxr(&mut self, rd: Gp, addr: Mem)

impl LdxrbEmitter<Gp, Mem> for Assembler<'_>

fn ldxrb(&mut self, rd: Gp, addr: Mem)

impl LdxrhEmitter<Gp, Mem> for Assembler<'_>

fn ldxrh(&mut self, rd: Gp, addr: Mem)

impl LoadConstantEmitter<Gp, Constant> for Assembler<'_>

fn load_constant(&mut self, dst: Gp, src: Constant)

impl LoadConstantEmitter<Gp, Label> for Assembler<'_>

fn load_constant(&mut self, dst: Gp, src: Label)

impl LoadConstantEmitter<Gp, Sym> for Assembler<'_>

fn load_constant(&mut self, dst: Gp, src: Sym)

impl LslEmitter<Gp, Gp, Gp> for Assembler<'_>

fn lsl(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp)

impl LslEmitter<Gp, Gp, Imm> for Assembler<'_>

fn lsl(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm)

impl LslvEmitter<Gp, Gp, Gp> for Assembler<'_>

fn lslv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl LsrEmitter<Gp, Gp, Gp> for Assembler<'_>

fn lsr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp)

impl LsrEmitter<Gp, Gp, Imm> for Assembler<'_>

fn lsr(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm)

impl LsrvEmitter<Gp, Gp, Gp> for Assembler<'_>

fn lsrv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl MaddEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn madd(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl MlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn mla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl MlsEmitter<Vec, Vec, Vec> for Assembler<'_>

fn mls(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl MnegEmitter<Gp, Gp, Gp> for Assembler<'_>

fn mneg(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl MovEmitter<Gp, Gp> for Assembler<'_>

fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Gp)

impl MovEmitter<Gp, Imm> for Assembler<'_>

fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Imm)

impl MovEmitter<Gp, Vec> for Assembler<'_>

fn mov(&mut self, rd: Gp, rm_or_rn_or_imm_or_log_imm: Vec)

impl MovEmitter<Vec, Gp> for Assembler<'_>

fn mov(&mut self, rd: Vec, rm_or_rn_or_imm_or_log_imm: Gp)

impl MovEmitter<Vec, Vec> for Assembler<'_>

fn mov(&mut self, rd: Vec, rm_or_rn_or_imm_or_log_imm: Vec)

impl Movi3Emitter<Vec, Imm, Imm> for Assembler<'_>

fn movi_3(&mut self, rd: Vec, imm: Imm, shift: Imm)

impl MoviEmitter<Vec, Imm> for Assembler<'_>

fn movi(&mut self, rd: Vec, imm: Imm)

impl Movk3Emitter<Gp, Imm, Imm> for Assembler<'_>

fn movk_3(&mut self, rd: Gp, imm: Imm, shift: Imm)

impl MovkEmitter<Gp, Imm> for Assembler<'_>

fn movk(&mut self, rd: Gp, imm: Imm)

impl Movn3Emitter<Gp, Imm, Imm> for Assembler<'_>

fn movn_3(&mut self, rd: Gp, imm: Imm, shift: Imm)

impl MovnEmitter<Gp, Imm> for Assembler<'_>

fn movn(&mut self, rd: Gp, imm: Imm)

impl Movz3Emitter<Gp, Imm, Imm> for Assembler<'_>

fn movz_3(&mut self, rd: Gp, imm: Imm, shift: Imm)

impl MovzEmitter<Gp, Imm> for Assembler<'_>

fn movz(&mut self, rd: Gp, imm: Imm)

impl MrsEmitter<Gp, Imm> for Assembler<'_>

fn mrs(&mut self, rd: Gp, sysreg: Imm)

impl MsrEmitter<Imm, Gp> for Assembler<'_>

fn msr(&mut self, sysreg_or_pstatefield: Imm, rs_or_imm: Gp)

impl MsrEmitter<Imm, Imm> for Assembler<'_>

fn msr(&mut self, sysreg_or_pstatefield: Imm, rs_or_imm: Imm)

impl MsubEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn msub(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl MulEmitter<Gp, Gp, Gp> for Assembler<'_>

fn mul(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl MulEmitter<Vec, Vec, Vec> for Assembler<'_>

fn mul(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Mvn3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn mvn_3(&mut self, rd: Gp, rn: Gp, shift: Imm)

impl MvnEmitter<Gp, Gp> for Assembler<'_>

fn mvn(&mut self, rd: Gp, rn: Gp)

impl MvnEmitter<Vec, Vec> for Assembler<'_>

fn mvn(&mut self, rd: Vec, rn: Vec)

impl Mvn_3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn mvn__3(&mut self, rd: Gp, rn: Gp, shift: Imm)

impl Mvn_Emitter<Gp, Gp> for Assembler<'_>

fn mvn_(&mut self, rd: Gp, rn: Gp)

impl Mvn_Emitter<Vec, Vec> for Assembler<'_>

fn mvn_(&mut self, rd: Vec, rn: Vec)

impl Mvni3Emitter<Vec, Imm, Imm> for Assembler<'_>

fn mvni_3(&mut self, rd: Vec, imm: Imm, shift: Imm)

impl MvniEmitter<Vec, Imm> for Assembler<'_>

fn mvni(&mut self, rd: Vec, imm: Imm)

impl Neg3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn neg_3(&mut self, rd: Gp, rm: Gp, shift: Imm)

impl NegEmitter<Gp, Gp> for Assembler<'_>

fn neg(&mut self, rd: Gp, rm_or_rn: Gp)

impl NegEmitter<Vec, Vec> for Assembler<'_>

fn neg(&mut self, rd: Vec, rm_or_rn: Vec)

impl Negs3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn negs_3(&mut self, rd: Gp, rm: Gp, shift: Imm)

impl NegsEmitter<Gp, Gp> for Assembler<'_>

fn negs(&mut self, rd: Gp, rm: Gp)

impl NgcEmitter<Gp, Gp> for Assembler<'_>

fn ngc(&mut self, rd: Gp, rm: Gp)

impl NgcsEmitter<Gp, Gp> for Assembler<'_>

fn ngcs(&mut self, rd: Gp, rm: Gp)

impl NopEmitter for Assembler<'_>

fn nop(&mut self)

impl NotEmitter<Vec, Vec> for Assembler<'_>

fn not_(&mut self, rd: Vec, rn: Vec)

impl Orn4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn orn_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl OrnEmitter<Gp, Gp, Gp> for Assembler<'_>

fn orn(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl OrnEmitter<Vec, Vec, Vec> for Assembler<'_>

fn orn(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Orr2Emitter<Vec, Imm> for Assembler<'_>

fn orr_2(&mut self, rd: Vec, rn_or_imm: Imm)

impl Orr4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn orr_4(&mut self, rd: Gp, rn: Gp, rm: Gp, shift: Imm)

impl OrrEmitter<Gp, Gp, Gp> for Assembler<'_>

fn orr(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_log_imm_or_shift: Gp)

impl OrrEmitter<Gp, Gp, Imm> for Assembler<'_>

fn orr(&mut self, rd: Gp, rn_or_imm: Gp, rm_or_log_imm_or_shift: Imm)

impl OrrEmitter<Vec, Imm, Imm> for Assembler<'_>

fn orr(&mut self, rd: Vec, rn_or_imm: Imm, rm_or_log_imm_or_shift: Imm)

impl OrrEmitter<Vec, Vec, Vec> for Assembler<'_>

fn orr(&mut self, rd: Vec, rn_or_imm: Vec, rm_or_log_imm_or_shift: Vec)

impl PacdaEmitter<Gp, Gp> for Assembler<'_>

fn pacda(&mut self, rd: Gp, rn: Gp)

impl PacdbEmitter<Gp, Gp> for Assembler<'_>

fn pacdb(&mut self, rd: Gp, rn: Gp)

impl PacdzaEmitter<Gp> for Assembler<'_>

fn pacdza(&mut self, rd: Gp)

impl PacdzbEmitter<Gp> for Assembler<'_>

fn pacdzb(&mut self, rd: Gp)

impl PacgaEmitter<Gp, Gp, Gp> for Assembler<'_>

fn pacga(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl PmulEmitter<Vec, Vec, Vec> for Assembler<'_>

fn pmul(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Pmull2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn pmull2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl PmullEmitter<Vec, Vec, Vec> for Assembler<'_>

fn pmull(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl PrfmEmitter<Imm, Mem> for Assembler<'_>

fn prfm(&mut self, prf_op: Imm, addr: Mem)

impl PssbbEmitter for Assembler<'_>

fn pssbb(&mut self)

impl Raddhn2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn raddhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl RaddhnEmitter<Vec, Vec, Vec> for Assembler<'_>

fn raddhn(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Rax1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn rax1(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl RbitEmitter<Gp, Gp> for Assembler<'_>

fn rbit(&mut self, rd: Gp, rn: Gp)

impl RbitEmitter<Vec, Vec> for Assembler<'_>

fn rbit(&mut self, rd: Vec, rn: Vec)

impl RetEmitter<Gp> for Assembler<'_>

fn ret(&mut self, rn: Gp)

impl Rev16Emitter<Gp, Gp> for Assembler<'_>

fn rev16(&mut self, rd: Gp, rn: Gp)

impl Rev16Emitter<Vec, Vec> for Assembler<'_>

fn rev16(&mut self, rd: Vec, rn: Vec)

impl Rev32Emitter<Gp, Gp> for Assembler<'_>

fn rev32(&mut self, rd: Gp, rn: Gp)

impl Rev32Emitter<Vec, Vec> for Assembler<'_>

fn rev32(&mut self, rd: Vec, rn: Vec)

impl Rev64Emitter<Gp, Gp> for Assembler<'_>

fn rev64(&mut self, rd: Gp, rn: Gp)

impl Rev64Emitter<Vec, Vec> for Assembler<'_>

fn rev64(&mut self, rd: Vec, rn: Vec)

impl RevEmitter<Gp, Gp> for Assembler<'_>

fn rev(&mut self, rd: Gp, rn: Gp)

impl RorEmitter<Gp, Gp, Gp> for Assembler<'_>

fn ror(&mut self, rd: Gp, rn: Gp, rm_or_shift: Gp)

impl RorEmitter<Gp, Gp, Imm> for Assembler<'_>

fn ror(&mut self, rd: Gp, rn: Gp, rm_or_shift: Imm)

impl RorvEmitter<Gp, Gp, Gp> for Assembler<'_>

fn rorv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Rshrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn rshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl RshrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn rshrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl Rsubhn2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn rsubhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl RsubhnEmitter<Vec, Vec, Vec> for Assembler<'_>

fn rsubhn(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SabaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn saba(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sabal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sabal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SabalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sabal(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SabdEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sabd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sabdl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sabdl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SabdlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sabdl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SadalpEmitter<Vec, Vec> for Assembler<'_>

fn sadalp(&mut self, operand_1: Vec, rn: Vec)

impl Saddl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn saddl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SaddlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn saddl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SaddlpEmitter<Vec, Vec> for Assembler<'_>

fn saddlp(&mut self, rd: Vec, rn: Vec)

impl SaddlvEmitter<Vec, Vec> for Assembler<'_>

fn saddlv(&mut self, rd: Vec, rn: Vec)

impl Saddw2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn saddw2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SaddwEmitter<Vec, Vec, Vec> for Assembler<'_>

fn saddw(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SbcEmitter<Gp, Gp, Gp> for Assembler<'_>

fn sbc(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SbcsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn sbcs(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SbfizEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn sbfiz(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl SbfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn sbfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm)

impl SbfxEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn sbfx(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl Scvtf3Emitter<Vec, Gp, Imm> for Assembler<'_>

fn scvtf_3(&mut self, rd: Vec, rn: Gp, fbits_or_bits: Imm)

impl Scvtf3Emitter<Vec, Vec, Imm> for Assembler<'_>

fn scvtf_3(&mut self, rd: Vec, rn: Vec, fbits_or_bits: Imm)

impl ScvtfEmitter<Vec, Gp> for Assembler<'_>

fn scvtf(&mut self, rd: Vec, rn: Gp)

impl ScvtfEmitter<Vec, Vec> for Assembler<'_>

fn scvtf(&mut self, rd: Vec, rn: Vec)

impl SdivEmitter<Gp, Gp, Gp> for Assembler<'_>

fn sdiv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SdotEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Setf8Emitter<Gp> for Assembler<'_>

fn setf8(&mut self, rn: Gp)

impl Setf16Emitter<Gp> for Assembler<'_>

fn setf16(&mut self, rn: Gp)

impl SevEmitter for Assembler<'_>

fn sev(&mut self)

impl SevlEmitter for Assembler<'_>

fn sevl(&mut self)

impl Sha1cEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sha1c(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha1hEmitter<Vec, Vec> for Assembler<'_>

fn sha1h(&mut self, rd: Vec, rn: Vec)

impl Sha1mEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sha1m(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha1pEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sha1p(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha1su0Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sha1su0(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha1su1Emitter<Vec, Vec> for Assembler<'_>

fn sha1su1(&mut self, operand_1: Vec, rn: Vec)

impl Sha256h2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sha256h2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha256hEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sha256h(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha256su0Emitter<Vec, Vec> for Assembler<'_>

fn sha256su0(&mut self, operand_1: Vec, rn: Vec)

impl Sha256su1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sha256su1(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha512h2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sha512h2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha512hEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sha512h(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sha512su0Emitter<Vec, Vec> for Assembler<'_>

fn sha512su0(&mut self, operand_1: Vec, rn: Vec)

impl Sha512su1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sha512su1(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl ShaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn shadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl ShlEmitter<Vec, Vec, Imm> for Assembler<'_>

fn shl(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl Shll2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn shll2(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl ShllEmitter<Vec, Vec, Imm> for Assembler<'_>

fn shll(&mut self, rd: Vec, rn: Vec, operand_3: Imm)

impl Shrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn shrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl ShrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn shrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl ShsubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn shsub(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SliEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sli(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl Sm3partw1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3partw1(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm3partw2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3partw2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm3ss1Emitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn sm3ss1(&mut self, rd: Vec, rn: Vec, rm: Vec, operand_4: Vec)

impl Sm3tt1aEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3tt1a(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm3tt1bEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3tt1b(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm3tt2aEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3tt2a(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm3tt2bEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sm3tt2b(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sm4eEmitter<Vec, Vec> for Assembler<'_>

fn sm4e(&mut self, operand_1: Vec, rn: Vec)

impl Sm4ekeyEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sm4ekey(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SmaddlEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn smaddl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl SmaxEmitter<Gp, Gp, Gp> for Assembler<'_>

fn smax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl SmaxEmitter<Gp, Gp, Imm> for Assembler<'_>

fn smax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl SmaxEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smax(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl SmaxpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smaxp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SmaxvEmitter<Vec, Vec> for Assembler<'_>

fn smaxv(&mut self, rd: Vec, rn: Vec)

impl SmcEmitter<Imm> for Assembler<'_>

fn smc(&mut self, imm: Imm)

impl SminEmitter<Gp, Gp, Gp> for Assembler<'_>

fn smin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl SminEmitter<Gp, Gp, Imm> for Assembler<'_>

fn smin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl SminEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smin(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl SminpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sminp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SminvEmitter<Vec, Vec> for Assembler<'_>

fn sminv(&mut self, rd: Vec, rn: Vec)

impl Smlal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn smlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SmlalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Smlsl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn smlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SmlslEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SmmlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SmneglEmitter<Gp, Gp, Gp> for Assembler<'_>

fn smnegl(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SmovEmitter<Gp, Vec> for Assembler<'_>

fn smov(&mut self, rd: Gp, rn: Vec)

impl SmsublEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn smsubl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl SmulhEmitter<Gp, Gp, Gp> for Assembler<'_>

fn smulh(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Smull2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn smull2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SmullEmitter<Gp, Gp, Gp> for Assembler<'_>

fn smull(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SmullEmitter<Vec, Vec, Vec> for Assembler<'_>

fn smull(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SqabsEmitter<Vec, Vec> for Assembler<'_>

fn sqabs(&mut self, rd: Vec, rn: Vec)

impl SqaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sqdmlal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmlal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SqdmlalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmlal(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Sqdmlsl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmlsl2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SqdmlslEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmlsl(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SqdmulhEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmulh(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sqdmull2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmull2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SqdmullEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqdmull(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SqnegEmitter<Vec, Vec> for Assembler<'_>

fn sqneg(&mut self, rd: Vec, rn: Vec)

impl SqrdmlahEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqrdmlah(&mut self, operand_1: Vec, rn: Vec, rm_or_rn: Vec)

impl SqrdmlshEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqrdmlsh(&mut self, operand_1: Vec, rn: Vec, rm_or_rn: Vec)

impl SqrdmulhEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqrdmulh(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SqrshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqrshl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sqrshrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn sqrshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SqrshrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqrshrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl Sqrshrun2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn sqrshrun2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SqrshrunEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqrshrun(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SqshlEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Imm)

impl SqshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Vec)

impl SqshluEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshlu(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl Sqshrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SqshrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl Sqshrun2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshrun2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SqshrunEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sqshrun(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SqsubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sqsub(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sqxtn2Emitter<Vec, Vec> for Assembler<'_>

fn sqxtn2(&mut self, operand_1: Vec, rn: Vec)

impl SqxtnEmitter<Vec, Vec> for Assembler<'_>

fn sqxtn(&mut self, rd: Vec, rn: Vec)

impl Sqxtun2Emitter<Vec, Vec> for Assembler<'_>

fn sqxtun2(&mut self, operand_1: Vec, rn: Vec)

impl SqxtunEmitter<Vec, Vec> for Assembler<'_>

fn sqxtun(&mut self, rd: Vec, rn: Vec)

impl SrhaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn srhadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SriEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sri(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SrshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn srshl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SrshrEmitter<Vec, Vec, Imm> for Assembler<'_>

fn srshr(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SrsraEmitter<Vec, Vec, Imm> for Assembler<'_>

fn srsra(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl SsbbEmitter for Assembler<'_>

fn ssbb(&mut self)

impl SshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sshl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Sshll2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn sshll2(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SshllEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sshll(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SshrEmitter<Vec, Vec, Imm> for Assembler<'_>

fn sshr(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl SsraEmitter<Vec, Vec, Imm> for Assembler<'_>

fn ssra(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl Ssubl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn ssubl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SsublEmitter<Vec, Vec, Vec> for Assembler<'_>

fn ssubl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Ssubw2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn ssubw2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SsubwEmitter<Vec, Vec, Vec> for Assembler<'_>

fn ssubw(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl St1Emitter<Vec, Mem> for Assembler<'_>

fn st1(&mut self, rs_or_operand_1: Vec, addr: Mem)

impl St2Emitter<Vec, Vec, Mem> for Assembler<'_>

fn st2(&mut self, rd: Vec, rn: Vec, addr: Mem)

impl St2gEmitter<Gp, Mem> for Assembler<'_>

fn st2g(&mut self, rs: Gp, addr: Mem)

impl St3Emitter<Vec, Vec, Vec, Mem> for Assembler<'_>

fn st3(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem)

impl St4Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_>

fn st4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem)

impl St13Emitter<Vec, Vec, Mem> for Assembler<'_>

fn st1_3(&mut self, rd: Vec, rn: Vec, addr: Mem)

impl St14Emitter<Vec, Vec, Vec, Mem> for Assembler<'_>

fn st1_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, addr: Mem)

impl St15Emitter<Vec, Vec, Vec, Vec, Mem> for Assembler<'_>

fn st1_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, addr: Mem)

impl StaddEmitter<Gp, Mem> for Assembler<'_>

fn stadd(&mut self, rs: Gp, addr: Mem)

impl StaddbEmitter<Gp, Mem> for Assembler<'_>

fn staddb(&mut self, rs: Gp, addr: Mem)

impl StaddhEmitter<Gp, Mem> for Assembler<'_>

fn staddh(&mut self, rs: Gp, addr: Mem)

impl StaddlEmitter<Gp, Mem> for Assembler<'_>

fn staddl(&mut self, rs: Gp, addr: Mem)

impl StaddlbEmitter<Gp, Mem> for Assembler<'_>

fn staddlb(&mut self, rs: Gp, addr: Mem)

impl StaddlhEmitter<Gp, Mem> for Assembler<'_>

fn staddlh(&mut self, rs: Gp, addr: Mem)

impl StclrEmitter<Gp, Mem> for Assembler<'_>

fn stclr(&mut self, rs: Gp, addr: Mem)

impl StclrbEmitter<Gp, Mem> for Assembler<'_>

fn stclrb(&mut self, rs: Gp, addr: Mem)

impl StclrhEmitter<Gp, Mem> for Assembler<'_>

fn stclrh(&mut self, rs: Gp, addr: Mem)

impl StclrlEmitter<Gp, Mem> for Assembler<'_>

fn stclrl(&mut self, rs: Gp, addr: Mem)

impl StclrlbEmitter<Gp, Mem> for Assembler<'_>

fn stclrlb(&mut self, rs: Gp, addr: Mem)

impl StclrlhEmitter<Gp, Mem> for Assembler<'_>

fn stclrlh(&mut self, rs: Gp, addr: Mem)

impl SteorEmitter<Gp, Mem> for Assembler<'_>

fn steor(&mut self, rs: Gp, addr: Mem)

impl SteorbEmitter<Gp, Mem> for Assembler<'_>

fn steorb(&mut self, rs: Gp, addr: Mem)

impl SteorhEmitter<Gp, Mem> for Assembler<'_>

fn steorh(&mut self, rs: Gp, addr: Mem)

impl SteorlEmitter<Gp, Mem> for Assembler<'_>

fn steorl(&mut self, rs: Gp, addr: Mem)

impl SteorlbEmitter<Gp, Mem> for Assembler<'_>

fn steorlb(&mut self, rs: Gp, addr: Mem)

impl SteorlhEmitter<Gp, Mem> for Assembler<'_>

fn steorlh(&mut self, rs: Gp, addr: Mem)

impl StgEmitter<Gp, Mem> for Assembler<'_>

fn stg(&mut self, rs: Gp, addr: Mem)

impl StgmEmitter<Gp, Mem> for Assembler<'_>

fn stgm(&mut self, rs: Gp, addr: Mem)

impl StgpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stgp(&mut self, rs: Gp, rs2: Gp, addr: Mem)

impl StllrEmitter<Gp, Mem> for Assembler<'_>

fn stllr(&mut self, rs: Gp, addr: Mem)

impl StllrbEmitter<Gp, Mem> for Assembler<'_>

fn stllrb(&mut self, rs: Gp, addr: Mem)

impl StllrhEmitter<Gp, Mem> for Assembler<'_>

fn stllrh(&mut self, rs: Gp, addr: Mem)

impl StlrEmitter<Gp, Mem> for Assembler<'_>

fn stlr(&mut self, rs: Gp, addr: Mem)

impl StlrbEmitter<Gp, Mem> for Assembler<'_>

fn stlrb(&mut self, rs: Gp, addr: Mem)

impl StlrhEmitter<Gp, Mem> for Assembler<'_>

fn stlrh(&mut self, rs: Gp, addr: Mem)

impl StlxpEmitter<Gp, Gp, Gp, Mem> for Assembler<'_>

fn stlxp(&mut self, rd: Gp, rs: Gp, rs2: Gp, addr: Mem)

impl StlxrEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stlxr(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl StlxrbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stlxrb(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl StlxrhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stlxrh(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl StnpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stnp(&mut self, rs_or_rd: Gp, rs2_or_rd2: Gp, addr: Mem)

impl StnpEmitter<Vec, Vec, Mem> for Assembler<'_>

fn stnp(&mut self, rs_or_rd: Vec, rs2_or_rd2: Vec, addr: Mem)

impl StpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stp(&mut self, rs_or_rd: Gp, rs2_or_rd2: Gp, addr: Mem)

impl StpEmitter<Vec, Vec, Mem> for Assembler<'_>

fn stp(&mut self, rs_or_rd: Vec, rs2_or_rd2: Vec, addr: Mem)

impl StrEmitter<Gp, Mem> for Assembler<'_>

fn str(&mut self, rs_or_rd: Gp, addr: Mem)

impl StrEmitter<Vec, Mem> for Assembler<'_>

fn str(&mut self, rs_or_rd: Vec, addr: Mem)

impl StrbEmitter<Gp, Mem> for Assembler<'_>

fn strb(&mut self, rs: Gp, addr: Mem)

impl StrhEmitter<Gp, Mem> for Assembler<'_>

fn strh(&mut self, rs: Gp, addr: Mem)

impl StsetEmitter<Gp, Mem> for Assembler<'_>

fn stset(&mut self, rs: Gp, addr: Mem)

impl StsetbEmitter<Gp, Mem> for Assembler<'_>

fn stsetb(&mut self, rs: Gp, addr: Mem)

impl StsethEmitter<Gp, Mem> for Assembler<'_>

fn stseth(&mut self, rs: Gp, addr: Mem)

impl StsetlEmitter<Gp, Mem> for Assembler<'_>

fn stsetl(&mut self, rs: Gp, addr: Mem)

impl StsetlbEmitter<Gp, Mem> for Assembler<'_>

fn stsetlb(&mut self, rs: Gp, addr: Mem)

impl StsetlhEmitter<Gp, Mem> for Assembler<'_>

fn stsetlh(&mut self, rs: Gp, addr: Mem)

impl StsmaxEmitter<Gp, Mem> for Assembler<'_>

fn stsmax(&mut self, rs: Gp, addr: Mem)

impl StsmaxbEmitter<Gp, Mem> for Assembler<'_>

fn stsmaxb(&mut self, rs: Gp, addr: Mem)

impl StsmaxhEmitter<Gp, Mem> for Assembler<'_>

fn stsmaxh(&mut self, rs: Gp, addr: Mem)

impl StsmaxlEmitter<Gp, Mem> for Assembler<'_>

fn stsmaxl(&mut self, rs: Gp, addr: Mem)

impl StsmaxlbEmitter<Gp, Mem> for Assembler<'_>

fn stsmaxlb(&mut self, rs: Gp, addr: Mem)

impl StsmaxlhEmitter<Gp, Mem> for Assembler<'_>

fn stsmaxlh(&mut self, rs: Gp, addr: Mem)

impl StsminEmitter<Gp, Mem> for Assembler<'_>

fn stsmin(&mut self, rs: Gp, addr: Mem)

impl StsminbEmitter<Gp, Mem> for Assembler<'_>

fn stsminb(&mut self, rs: Gp, addr: Mem)

impl StsminhEmitter<Gp, Mem> for Assembler<'_>

fn stsminh(&mut self, rs: Gp, addr: Mem)

impl StsminlEmitter<Gp, Mem> for Assembler<'_>

fn stsminl(&mut self, rs: Gp, addr: Mem)

impl StsminlbEmitter<Gp, Mem> for Assembler<'_>

fn stsminlb(&mut self, rs: Gp, addr: Mem)

impl StsminlhEmitter<Gp, Mem> for Assembler<'_>

fn stsminlh(&mut self, rs: Gp, addr: Mem)

impl SttrEmitter<Gp, Mem> for Assembler<'_>

fn sttr(&mut self, rs: Gp, addr: Mem)

impl SttrbEmitter<Gp, Mem> for Assembler<'_>

fn sttrb(&mut self, rs: Gp, addr: Mem)

impl SttrhEmitter<Gp, Mem> for Assembler<'_>

fn sttrh(&mut self, rs: Gp, addr: Mem)

impl StumaxEmitter<Gp, Mem> for Assembler<'_>

fn stumax(&mut self, rs: Gp, addr: Mem)

impl StumaxbEmitter<Gp, Mem> for Assembler<'_>

fn stumaxb(&mut self, rs: Gp, addr: Mem)

impl StumaxhEmitter<Gp, Mem> for Assembler<'_>

fn stumaxh(&mut self, rs: Gp, addr: Mem)

impl StumaxlEmitter<Gp, Mem> for Assembler<'_>

fn stumaxl(&mut self, rs: Gp, addr: Mem)

impl StumaxlbEmitter<Gp, Mem> for Assembler<'_>

fn stumaxlb(&mut self, rs: Gp, addr: Mem)

impl StumaxlhEmitter<Gp, Mem> for Assembler<'_>

fn stumaxlh(&mut self, rs: Gp, addr: Mem)

impl StuminEmitter<Gp, Mem> for Assembler<'_>

fn stumin(&mut self, rs: Gp, addr: Mem)

impl StuminbEmitter<Gp, Mem> for Assembler<'_>

fn stuminb(&mut self, rs: Gp, addr: Mem)

impl StuminhEmitter<Gp, Mem> for Assembler<'_>

fn stuminh(&mut self, rs: Gp, addr: Mem)

impl StuminlEmitter<Gp, Mem> for Assembler<'_>

fn stuminl(&mut self, rs: Gp, addr: Mem)

impl StuminlbEmitter<Gp, Mem> for Assembler<'_>

fn stuminlb(&mut self, rs: Gp, addr: Mem)

impl StuminlhEmitter<Gp, Mem> for Assembler<'_>

fn stuminlh(&mut self, rs: Gp, addr: Mem)

impl SturEmitter<Gp, Mem> for Assembler<'_>

fn stur(&mut self, rs_or_rd: Gp, addr: Mem)

impl SturEmitter<Vec, Mem> for Assembler<'_>

fn stur(&mut self, rs_or_rd: Vec, addr: Mem)

impl SturbEmitter<Gp, Mem> for Assembler<'_>

fn sturb(&mut self, rs: Gp, addr: Mem)

impl SturhEmitter<Gp, Mem> for Assembler<'_>

fn sturh(&mut self, rs: Gp, addr: Mem)

impl StxpEmitter<Gp, Gp, Gp, Mem> for Assembler<'_>

fn stxp(&mut self, rd: Gp, rs: Gp, rs2: Gp, addr: Mem)

impl StxrEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stxr(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl StxrbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stxrb(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl StxrhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn stxrh(&mut self, rd: Gp, rs: Gp, addr: Mem)

impl Stz2gEmitter<Gp, Mem> for Assembler<'_>

fn stz2g(&mut self, rs: Gp, addr: Mem)

impl StzgEmitter<Gp, Mem> for Assembler<'_>

fn stzg(&mut self, rs: Gp, addr: Mem)

impl StzgmEmitter<Gp, Mem> for Assembler<'_>

fn stzgm(&mut self, rs: Gp, addr: Mem)

impl Sub4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn sub_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm)

impl Sub4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn sub_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm)

impl SubEmitter<Gp, Gp, Gp> for Assembler<'_>

fn sub(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl SubEmitter<Gp, Gp, Imm> for Assembler<'_>

fn sub(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl SubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sub(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl SubgEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn subg(&mut self, rd: Gp, rn: Gp, imm1: Imm, imm2: Imm)

impl Subhn2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn subhn2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SubhnEmitter<Vec, Vec, Vec> for Assembler<'_>

fn subhn(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl SubpEmitter<Gp, Gp, Gp> for Assembler<'_>

fn subp(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl SubpsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn subps(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Subs4Emitter<Gp, Gp, Gp, Imm> for Assembler<'_>

fn subs_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp, shift: Imm)

impl Subs4Emitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn subs_4(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm, shift: Imm)

impl SubsEmitter<Gp, Gp, Gp> for Assembler<'_>

fn subs(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl SubsEmitter<Gp, Gp, Imm> for Assembler<'_>

fn subs(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl SudotEmitter<Vec, Vec, Vec> for Assembler<'_>

fn sudot(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl SuqaddEmitter<Vec, Vec> for Assembler<'_>

fn suqadd(&mut self, operand_1: Vec, rn: Vec)

impl SvcEmitter<Imm> for Assembler<'_>

fn svc(&mut self, imm: Imm)

impl SwpEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swp(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpaEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpa(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpabEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpab(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpahEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpah(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpalEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpal(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpalbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpalb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpalhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpalh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwpbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwphEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swph(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwplEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swpl(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwplbEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swplb(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SwplhEmitter<Gp, Gp, Mem> for Assembler<'_>

fn swplh(&mut self, rs: Gp, rd: Gp, addr: Mem)

impl SxtbEmitter<Gp, Gp> for Assembler<'_>

fn sxtb(&mut self, rd: Gp, rn: Gp)

impl SxthEmitter<Gp, Gp> for Assembler<'_>

fn sxth(&mut self, rd: Gp, rn: Gp)

impl Sxtl2Emitter<Vec, Vec> for Assembler<'_>

fn sxtl2(&mut self, rd: Vec, rn: Vec)

impl SxtlEmitter<Vec, Vec> for Assembler<'_>

fn sxtl(&mut self, rd: Vec, rn: Vec)

impl SxtwEmitter<Gp, Gp> for Assembler<'_>

fn sxtw(&mut self, rd: Gp, rn: Gp)

impl Sys5Emitter<Imm, Imm, Imm, Imm, Gp> for Assembler<'_>

fn sys_5(&mut self, system_op1: Imm, cn: Imm, cm: Imm, system_op2: Imm, rt: Gp)

impl SysEmitter<Imm, Imm, Imm, Imm> for Assembler<'_>

fn sys(&mut self, system_op1: Imm, cn: Imm, cm: Imm, system_op2: Imm)

impl Tbl4Emitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbl_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec)

impl Tbl5Emitter<Vec, Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbl_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec)

impl Tbl6Emitter<Vec, Vec, Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbl_6(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec, rm4: Vec)

impl TblEmitter<Vec, Vec, Vec> for Assembler<'_>

fn tbl(&mut self, rd: Vec, rn_or_operand_2: Vec, rm: Vec)

impl TbnzEmitter<Gp, Imm, Imm> for Assembler<'_>

fn tbnz(&mut self, rt: Gp, imm: Imm, target: Imm)

impl TbnzEmitter<Gp, Imm, Label> for Assembler<'_>

fn tbnz(&mut self, rt: Gp, imm: Imm, target: Label)

impl TbnzEmitter<Gp, Imm, Sym> for Assembler<'_>

fn tbnz(&mut self, rt: Gp, imm: Imm, target: Sym)

impl Tbx4Emitter<Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbx_4(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec)

impl Tbx5Emitter<Vec, Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbx_5(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec)

impl Tbx6Emitter<Vec, Vec, Vec, Vec, Vec, Vec> for Assembler<'_>

fn tbx_6(&mut self, rd: Vec, rn: Vec, rm1: Vec, rm2: Vec, rm3: Vec, rm4: Vec)

impl TbxEmitter<Vec, Vec, Vec> for Assembler<'_>

fn tbx(&mut self, operand_1: Vec, rn_or_operand_2: Vec, rm: Vec)

impl TbzEmitter<Gp, Imm, Imm> for Assembler<'_>

fn tbz(&mut self, rt: Gp, imm: Imm, target: Imm)

impl TbzEmitter<Gp, Imm, Label> for Assembler<'_>

fn tbz(&mut self, rt: Gp, imm: Imm, target: Label)

impl TbzEmitter<Gp, Imm, Sym> for Assembler<'_>

fn tbz(&mut self, rt: Gp, imm: Imm, target: Sym)

impl TlbiEmitter<Imm, Gp> for Assembler<'_>

fn tlbi(&mut self, tlbi_op: Imm, rt: Gp)

impl Trn1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn trn1(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Trn2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn trn2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Tst3Emitter<Gp, Gp, Imm> for Assembler<'_>

fn tst_3(&mut self, rn: Gp, rm: Gp, shift: Imm)

impl TstEmitter<Gp, Gp> for Assembler<'_>

fn tst(&mut self, rn: Gp, rm_or_imm: Gp)

impl TstEmitter<Gp, Imm> for Assembler<'_>

fn tst(&mut self, rn: Gp, rm_or_imm: Imm)

impl UabaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uaba(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl Uabal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uabal2(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UabalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uabal(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UabdEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uabd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Uabdl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uabdl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UabdlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uabdl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UadalpEmitter<Vec, Vec> for Assembler<'_>

fn uadalp(&mut self, operand_1: Vec, rn: Vec)

impl Uaddl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uaddl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UaddlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uaddl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UaddlpEmitter<Vec, Vec> for Assembler<'_>

fn uaddlp(&mut self, rd: Vec, rn: Vec)

impl UaddlvEmitter<Vec, Vec> for Assembler<'_>

fn uaddlv(&mut self, rd: Vec, rn: Vec)

impl Uaddw2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uaddw2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UaddwEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uaddw(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UbfizEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn ubfiz(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl UbfmEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn ubfm(&mut self, rd: Gp, rn: Gp, imm: Imm, imm_2: Imm)

impl UbfxEmitter<Gp, Gp, Imm, Imm> for Assembler<'_>

fn ubfx(&mut self, rd: Gp, rn: Gp, lsb: Imm, width: Imm)

impl Ucvtf3Emitter<Vec, Gp, Imm> for Assembler<'_>

fn ucvtf_3(&mut self, rd: Vec, rn: Gp, fbits_or_bits: Imm)

impl Ucvtf3Emitter<Vec, Vec, Imm> for Assembler<'_>

fn ucvtf_3(&mut self, rd: Vec, rn: Vec, fbits_or_bits: Imm)

impl UcvtfEmitter<Vec, Gp> for Assembler<'_>

fn ucvtf(&mut self, rd: Vec, rn: Gp)

impl UcvtfEmitter<Vec, Vec> for Assembler<'_>

fn ucvtf(&mut self, rd: Vec, rn: Vec)

impl UdfEmitter<Imm> for Assembler<'_>

fn udf(&mut self, imm: Imm)

impl UdivEmitter<Gp, Gp, Gp> for Assembler<'_>

fn udiv(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl UdotEmitter<Vec, Vec, Vec> for Assembler<'_>

fn udot(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UhaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uhadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UhsubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uhsub(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmaddlEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn umaddl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl UmaxEmitter<Gp, Gp, Gp> for Assembler<'_>

fn umax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl UmaxEmitter<Gp, Gp, Imm> for Assembler<'_>

fn umax(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl UmaxEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umax(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl UmaxpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umaxp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmaxvEmitter<Vec, Vec> for Assembler<'_>

fn umaxv(&mut self, rd: Vec, rn: Vec)

impl UminEmitter<Gp, Gp, Gp> for Assembler<'_>

fn umin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Gp)

impl UminEmitter<Gp, Gp, Imm> for Assembler<'_>

fn umin(&mut self, rd: Gp, rn: Gp, rm_or_imm: Imm)

impl UminEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umin(&mut self, rd: Vec, rn: Vec, rm_or_imm: Vec)

impl UminpEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uminp(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UminvEmitter<Vec, Vec> for Assembler<'_>

fn uminv(&mut self, rd: Vec, rn: Vec)

impl Umlal2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn umlal2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmlalEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umlal(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Umlsl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn umlsl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmlslEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umlsl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmmlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn ummla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UmneglEmitter<Gp, Gp, Gp> for Assembler<'_>

fn umnegl(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl UmovEmitter<Gp, Vec> for Assembler<'_>

fn umov(&mut self, rd: Gp, rn: Vec)

impl UmsublEmitter<Gp, Gp, Gp, Gp> for Assembler<'_>

fn umsubl(&mut self, rd: Gp, rn: Gp, rm: Gp, operand_4: Gp)

impl UmulhEmitter<Gp, Gp, Gp> for Assembler<'_>

fn umulh(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl Umull2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn umull2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UmullEmitter<Gp, Gp, Gp> for Assembler<'_>

fn umull(&mut self, rd: Gp, rn: Gp, rm: Gp)

impl UmullEmitter<Vec, Vec, Vec> for Assembler<'_>

fn umull(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UqaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uqadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UqrshlEmitter<Vec, Vec, Imm> for Assembler<'_>

fn uqrshl(&mut self, rd: Vec, rn: Vec, rm: Imm)

impl UqrshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uqrshl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Uqrshrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn uqrshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl UqrshrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn uqrshrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UqshlEmitter<Vec, Vec, Imm> for Assembler<'_>

fn uqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Imm)

impl UqshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uqshl(&mut self, rd: Vec, rn: Vec, rm_or_shift: Vec)

impl Uqshrn2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn uqshrn2(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl UqshrnEmitter<Vec, Vec, Imm> for Assembler<'_>

fn uqshrn(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UqsubEmitter<Vec, Vec, Vec> for Assembler<'_>

fn uqsub(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Uqxtn2Emitter<Vec, Vec> for Assembler<'_>

fn uqxtn2(&mut self, operand_1: Vec, rn: Vec)

impl UqxtnEmitter<Vec, Vec> for Assembler<'_>

fn uqxtn(&mut self, rd: Vec, rn: Vec)

impl UrecpeEmitter<Vec, Vec> for Assembler<'_>

fn urecpe(&mut self, rd: Vec, rn: Vec)

impl UrhaddEmitter<Vec, Vec, Vec> for Assembler<'_>

fn urhadd(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UrshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn urshl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UrshrEmitter<Vec, Vec, Imm> for Assembler<'_>

fn urshr(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UrsqrteEmitter<Vec, Vec> for Assembler<'_>

fn ursqrte(&mut self, rd: Vec, rn: Vec)

impl UrsraEmitter<Vec, Vec, Imm> for Assembler<'_>

fn ursra(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl UsdotEmitter<Vec, Vec, Vec> for Assembler<'_>

fn usdot(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UshlEmitter<Vec, Vec, Vec> for Assembler<'_>

fn ushl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Ushll2Emitter<Vec, Vec, Imm> for Assembler<'_>

fn ushll2(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UshllEmitter<Vec, Vec, Imm> for Assembler<'_>

fn ushll(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UshrEmitter<Vec, Vec, Imm> for Assembler<'_>

fn ushr(&mut self, rd: Vec, rn: Vec, shift: Imm)

impl UsmmlaEmitter<Vec, Vec, Vec> for Assembler<'_>

fn usmmla(&mut self, operand_1: Vec, rn: Vec, rm: Vec)

impl UsqaddEmitter<Vec, Vec> for Assembler<'_>

fn usqadd(&mut self, operand_1: Vec, rn: Vec)

impl UsraEmitter<Vec, Vec, Imm> for Assembler<'_>

fn usra(&mut self, operand_1: Vec, rn: Vec, shift: Imm)

impl Usubl2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn usubl2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UsublEmitter<Vec, Vec, Vec> for Assembler<'_>

fn usubl(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Usubw2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn usubw2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UsubwEmitter<Vec, Vec, Vec> for Assembler<'_>

fn usubw(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl UxtbEmitter<Gp, Gp> for Assembler<'_>

fn uxtb(&mut self, rd: Gp, rn: Gp)

impl UxthEmitter<Gp, Gp> for Assembler<'_>

fn uxth(&mut self, rd: Gp, rn: Gp)

impl Uxtl2Emitter<Vec, Vec> for Assembler<'_>

fn uxtl2(&mut self, rd: Vec, rn: Vec)

impl UxtlEmitter<Vec, Vec> for Assembler<'_>

fn uxtl(&mut self, rd: Vec, rn: Vec)

impl Uzp1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uzp1(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Uzp2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn uzp2(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl WfeEmitter for Assembler<'_>

fn wfe(&mut self)

impl WfiEmitter for Assembler<'_>

fn wfi(&mut self)

impl XaflagEmitter for Assembler<'_>

fn xaflag(&mut self)

impl XarEmitter<Vec, Vec, Vec, Imm> for Assembler<'_>

fn xar(&mut self, rd: Vec, rn: Vec, rm: Vec, imm: Imm)

impl XpacdEmitter<Gp> for Assembler<'_>

fn xpacd(&mut self, rd: Gp)

impl XpaciEmitter<Gp> for Assembler<'_>

fn xpaci(&mut self, rd: Gp)

impl XpaclriEmitter for Assembler<'_>

fn xpaclri(&mut self)

impl Xtn2Emitter<Vec, Vec> for Assembler<'_>

fn xtn2(&mut self, operand_1: Vec, rn: Vec)

impl XtnEmitter<Vec, Vec> for Assembler<'_>

fn xtn(&mut self, rd: Vec, rn: Vec)

impl YieldEmitter for Assembler<'_>

fn yield(&mut self)

impl Zip1Emitter<Vec, Vec, Vec> for Assembler<'_>

fn zip1(&mut self, rd: Vec, rn: Vec, rm: Vec)

impl Zip2Emitter<Vec, Vec, Vec> for Assembler<'_>

fn zip2(&mut self, rd: Vec, rn: Vec, rm: Vec)