pub enum Reloc {
Show 24 variants
Abs4,
Abs8,
X86PCRel4,
X86CallPCRel4,
X86CallPLTRel4,
X86GOTPCRel4,
X86SecRel,
Arm32Call,
Arm64Call,
ElfX86_64TlsGd,
MachOX86_64Tlv,
MachOAarch64TlsAdrPage21,
MachOAarch64TlsAdrPageOff12,
Aarch64TlsDescAdrPage21,
Aarch64TlsDescLd64Lo12,
Aarch64TlsDescAddLo12,
Aarch64TlsDescCall,
Aarch64AdrGotPage21,
Aarch64Ld64GotLo12Nc,
RiscvAbs8,
RiscvCallPlt,
RiscvTlsGdHi20,
RiscvPCRelLo12I,
RiscvGotHi20,
}Expand description
Relocation kinds for every ISA
Variants§
Abs4
absolute 4-byte
Abs8
absolute 8-byte
X86PCRel4
x86 PC-relative 4-byte
X86CallPCRel4
x86 call to PC-relative 4-byte
X86CallPLTRel4
x86 call to PLT-relative 4-byte
X86GOTPCRel4
x86 GOT PC-relative 4-byte
X86SecRel
The 32-bit offset of the target from the beginning of its section.
Equivalent to IMAGE_REL_AMD64_SECREL.
See: PE Format
Arm32Call
Arm32 call target
Arm64Call
Arm64 call target. Encoded as bottom 26 bits of instruction. This value is sign-extended, multiplied by 4, and added to the PC of the call instruction to form the destination address.
ElfX86_64TlsGd
Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
MachOX86_64Tlv
Mach-O x86_64 32 bit signed PC relative offset to a __thread_vars entry.
MachOAarch64TlsAdrPage21
Mach-O Aarch64 TLS PC-relative distance to the page of the TLVP slot.
MachOAarch64TlsAdrPageOff12
Mach-O Aarch64 TLS Offset within page of TLVP slot.
Aarch64TlsDescAdrPage21
Aarch64 TLSDESC Adr Page21
This is equivalent to R_AARCH64_TLSDESC_ADR_PAGE21 in the aaelf64
Aarch64TlsDescLd64Lo12
Aarch64 TLSDESC Ld64 Lo12
This is equivalent to R_AARCH64_TLSDESC_LD64_LO12 in the aaelf64
Aarch64TlsDescAddLo12
Aarch64 TLSDESC Add Lo12
This is equivalent to R_AARCH64_TLSGD_ADD_LO12 in the aaelf64
Aarch64TlsDescCall
Aarch64 TLSDESC Call
This is equivalent to R_AARCH64_TLSDESC_CALL in the aaelf64
Aarch64AdrGotPage21
AArch64 GOT Page
Set the immediate value of an ADRP to bits 32:12 of X; check that –2^32 <= X < 2^32
This is equivalent to R_AARCH64_ADR_GOT_PAGE (311) in the aaelf64
Aarch64Ld64GotLo12Nc
AArch64 GOT Low bits
Set the LD/ST immediate field to bits 11:3 of X. No overflow check; check that X&7 = 0
This is equivalent to R_AARCH64_LD64_GOT_LO12_NC (312) in the aaelf64
RiscvAbs8
RISC-V Absolute address: 64-bit address.
RiscvCallPlt
RISC-V Call PLT: 32-bit PC-relative function call, macros call, tail (PIC)
Despite having PLT in the name, this relocation is also used for normal calls. The non-PLT version of this relocation has been deprecated.
This is the R_RISCV_CALL_PLT relocation from the RISC-V ELF psABI document.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#procedure-calls
RiscvTlsGdHi20
RISC-V TLS GD: High 20 bits of 32-bit PC-relative TLS GD GOT reference,
This is the R_RISCV_TLS_GD_HI20 relocation from the RISC-V ELF psABI document.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic
RiscvPCRelLo12I
Low 12 bits of a 32-bit PC-relative relocation (I-Type instruction)
This is the R_RISCV_PCREL_LO12_I relocation from the RISC-V ELF psABI document.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
RiscvGotHi20
High 20 bits of a 32-bit PC-relative GOT offset relocation
This is the R_RISCV_GOT_HI20 relocation from the RISC-V ELF psABI document.
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses