pub enum I {
Show 40 variants
LUI {
d: Reg,
im: i32,
},
AUIPC {
d: Reg,
im: i32,
},
JAL {
d: Reg,
im: i32,
},
JALR {
d: Reg,
s: Reg,
im: i16,
},
BEQ {
s1: Reg,
s2: Reg,
im: i16,
},
BNE {
s1: Reg,
s2: Reg,
im: i16,
},
BLT {
s1: Reg,
s2: Reg,
im: i16,
},
BGE {
s1: Reg,
s2: Reg,
im: i16,
},
BLTU {
s1: Reg,
s2: Reg,
im: i16,
},
BGEU {
s1: Reg,
s2: Reg,
im: i16,
},
LB {
d: Reg,
s: Reg,
im: i16,
},
LH {
d: Reg,
s: Reg,
im: i16,
},
LW {
d: Reg,
s: Reg,
im: i16,
},
LBU {
d: Reg,
s: Reg,
im: i16,
},
LHU {
d: Reg,
s: Reg,
im: i16,
},
SB {
s1: Reg,
s2: Reg,
im: i16,
},
SH {
s1: Reg,
s2: Reg,
im: i16,
},
SW {
s1: Reg,
s2: Reg,
im: i16,
},
ADDI {
d: Reg,
s: Reg,
im: i16,
},
SLTI {
d: Reg,
s: Reg,
im: i16,
},
SLTUI {
d: Reg,
s: Reg,
im: i16,
},
XORI {
d: Reg,
s: Reg,
im: i16,
},
ORI {
d: Reg,
s: Reg,
im: i16,
},
ANDI {
d: Reg,
s: Reg,
im: i16,
},
SLLI {
d: Reg,
s: Reg,
im: i8,
},
SRLI {
d: Reg,
s: Reg,
im: i8,
},
SRAI {
d: Reg,
s: Reg,
im: i8,
},
ADD {
d: Reg,
s1: Reg,
s2: Reg,
},
SUB {
d: Reg,
s1: Reg,
s2: Reg,
},
SLL {
d: Reg,
s1: Reg,
s2: Reg,
},
SLT {
d: Reg,
s1: Reg,
s2: Reg,
},
SLTU {
d: Reg,
s1: Reg,
s2: Reg,
},
XOR {
d: Reg,
s1: Reg,
s2: Reg,
},
SRL {
d: Reg,
s1: Reg,
s2: Reg,
},
SRA {
d: Reg,
s1: Reg,
s2: Reg,
},
OR {
d: Reg,
s1: Reg,
s2: Reg,
},
AND {
d: Reg,
s1: Reg,
s2: Reg,
},
ECALL {},
EBREAK {},
FENCE {
im: i16,
},
}
Expand description
An assembly instruction (im is limited to 12 bits)
Variants
LUI
U: Set upper 20 bits to immediate value
AUIPC
U: Add upper 20 bits to immediate value in program counter
JAL
UJ: Jump and Link Relative
JALR
I: Jump and Link, Register
BEQ
SB: 12-bit immediate offset Branch on Equal
BNE
SB: 12-bit immediate offset Branch on Not Equal
BLT
SB: 12-bit immediate offset Branch on Less Than
BGE
SB: 12-bit immediate offset Branch on Greater Than Or Equal To
BLTU
SB: 12-bit immediate offset Branch on Less Than (Unsigned)
BGEU
SB: 12-bit immediate offset Branch on Greater Than Or Equal To (Unsigned)
LB
I: Load Byte (R[d]: M[R[s] + im]
)
LH
I: Load Half-Word (R[d]: M[R[s] + im]
)
LW
I: Load Word (R[d]: M[R[s] + im]
)
LBU
I: Load Byte Unsigned (R[d]: M[R[s] + im]
)
LHU
I: Load Half Unsigned (R[d]: M[R[s] + im]
)
SB
S: Store Byte
SH
S: Store Half Word
SW
S: Store Word
ADDI
I: Add Immediate (R[d]: R[s] + im
)
SLTI
I: Set 1 on Less Than, 0 Otherwise Immediate
SLTUI
I: Set 1 on Less Than, 0 Otherwise Immediate Unsigned
XORI
I: Xor Immediate
ORI
I: Or Immediate
ANDI
I: And Immediate
SLLI
I: Logical Left Shift Immediate
SRLI
I: Logical Right Shift Immediate
SRAI
I: Arithmetic Shift Right Immediate (See SRA).
ADD
R: Add (R[d]: R[s1] + R[s2]
)
SUB
R: Subtract (R[d]: R[s1] - R[s2]
)
SLL
R: Logical Left Shift
SLT
R: Set 1 on Less Than, 0 Otherwise
SLTU
R: Set 1 on Less Than, 0 Otherwise Unsigned
XOR
R: Xor
SRL
R: Logical Right Shift
SRA
R: Arithmetic Shift Right (Sign Bit Copied Rather Than Filling In Zeros)
OR
R: Or
AND
R: And
ECALL
Fields
I: Invoke a system call (Registers defined by ABI, not hardware)
EBREAK
Fields
I: Debugger Breakpoint
FENCE
Fields
im: i16
I: Fence (Immediate Is Made Up Of Ordered High Order To Low Order Bits:)
- fm(4), PI(1), PO(1), PR(1), PW(1), SI(1), SO(1), SR(1), SW(1)
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcepub fn borrow_mut(&mut self) -> &mut T
pub fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more