Skip to main content

Register

Enum Register 

Source
pub enum Register {
Show 566 variants Rax, Rcx, Rdx, Rbx, Rsp, Rbp, Rsi, Rdi, R8, R9, R10, R11, R12, R13, R14, R15, Eax, Ecx, Edx, Ebx, Esp, Ebp, Esi, Edi, R8d, R9d, R10d, R11d, R12d, R13d, R14d, R15d, Ax, Cx, Dx, Bx, Sp, Bp, Si, Di, R8w, R9w, R10w, R11w, R12w, R13w, R14w, R15w, Al, Cl, Dl, Bl, Spl, Bpl, Sil, Dil, Ah, Ch, Dh, Bh, R8b, R9b, R10b, R11b, R12b, R13b, R14b, R15b, Rip, Eip, Cs, Ds, Es, Fs, Gs, Ss, Xmm0, Xmm1, Xmm2, Xmm3, Xmm4, Xmm5, Xmm6, Xmm7, Xmm8, Xmm9, Xmm10, Xmm11, Xmm12, Xmm13, Xmm14, Xmm15, Ymm0, Ymm1, Ymm2, Ymm3, Ymm4, Ymm5, Ymm6, Ymm7, Ymm8, Ymm9, Ymm10, Ymm11, Ymm12, Ymm13, Ymm14, Ymm15, Zmm0, Zmm1, Zmm2, Zmm3, Zmm4, Zmm5, Zmm6, Zmm7, Zmm8, Zmm9, Zmm10, Zmm11, Zmm12, Zmm13, Zmm14, Zmm15, Zmm16, Zmm17, Zmm18, Zmm19, Zmm20, Zmm21, Zmm22, Zmm23, Zmm24, Zmm25, Zmm26, Zmm27, Zmm28, Zmm29, Zmm30, Zmm31, K0, K1, K2, K3, K4, K5, K6, K7, ArmR0, ArmR1, ArmR2, ArmR3, ArmR4, ArmR5, ArmR6, ArmR7, ArmR8, ArmR9, ArmR10, ArmR11, ArmR12, ArmSp, ArmLr, ArmPc, ArmCpsr, A64X0, A64X1, A64X2, A64X3, A64X4, A64X5, A64X6, A64X7, A64X8, A64X9, A64X10, A64X11, A64X12, A64X13, A64X14, A64X15, A64X16, A64X17, A64X18, A64X19, A64X20, A64X21, A64X22, A64X23, A64X24, A64X25, A64X26, A64X27, A64X28, A64X29, A64X30, A64Sp, A64Xzr, A64W0, A64W1, A64W2, A64W3, A64W4, A64W5, A64W6, A64W7, A64W8, A64W9, A64W10, A64W11, A64W12, A64W13, A64W14, A64W15, A64W16, A64W17, A64W18, A64W19, A64W20, A64W21, A64W22, A64W23, A64W24, A64W25, A64W26, A64W27, A64W28, A64W29, A64W30, A64Wzr, A64V0, A64V1, A64V2, A64V3, A64V4, A64V5, A64V6, A64V7, A64V8, A64V9, A64V10, A64V11, A64V12, A64V13, A64V14, A64V15, A64V16, A64V17, A64V18, A64V19, A64V20, A64V21, A64V22, A64V23, A64V24, A64V25, A64V26, A64V27, A64V28, A64V29, A64V30, A64V31, A64Q0, A64Q1, A64Q2, A64Q3, A64Q4, A64Q5, A64Q6, A64Q7, A64Q8, A64Q9, A64Q10, A64Q11, A64Q12, A64Q13, A64Q14, A64Q15, A64Q16, A64Q17, A64Q18, A64Q19, A64Q20, A64Q21, A64Q22, A64Q23, A64Q24, A64Q25, A64Q26, A64Q27, A64Q28, A64Q29, A64Q30, A64Q31, A64D0, A64D1, A64D2, A64D3, A64D4, A64D5, A64D6, A64D7, A64D8, A64D9, A64D10, A64D11, A64D12, A64D13, A64D14, A64D15, A64D16, A64D17, A64D18, A64D19, A64D20, A64D21, A64D22, A64D23, A64D24, A64D25, A64D26, A64D27, A64D28, A64D29, A64D30, A64D31, A64S0, A64S1, A64S2, A64S3, A64S4, A64S5, A64S6, A64S7, A64S8, A64S9, A64S10, A64S11, A64S12, A64S13, A64S14, A64S15, A64S16, A64S17, A64S18, A64S19, A64S20, A64S21, A64S22, A64S23, A64S24, A64S25, A64S26, A64S27, A64S28, A64S29, A64S30, A64S31, A64H0, A64H1, A64H2, A64H3, A64H4, A64H5, A64H6, A64H7, A64H8, A64H9, A64H10, A64H11, A64H12, A64H13, A64H14, A64H15, A64H16, A64H17, A64H18, A64H19, A64H20, A64H21, A64H22, A64H23, A64H24, A64H25, A64H26, A64H27, A64H28, A64H29, A64H30, A64H31, A64B0, A64B1, A64B2, A64B3, A64B4, A64B5, A64B6, A64B7, A64B8, A64B9, A64B10, A64B11, A64B12, A64B13, A64B14, A64B15, A64B16, A64B17, A64B18, A64B19, A64B20, A64B21, A64B22, A64B23, A64B24, A64B25, A64B26, A64B27, A64B28, A64B29, A64B30, A64B31, A64Z0, A64Z1, A64Z2, A64Z3, A64Z4, A64Z5, A64Z6, A64Z7, A64Z8, A64Z9, A64Z10, A64Z11, A64Z12, A64Z13, A64Z14, A64Z15, A64Z16, A64Z17, A64Z18, A64Z19, A64Z20, A64Z21, A64Z22, A64Z23, A64Z24, A64Z25, A64Z26, A64Z27, A64Z28, A64Z29, A64Z30, A64Z31, A64P0, A64P1, A64P2, A64P3, A64P4, A64P5, A64P6, A64P7, A64P8, A64P9, A64P10, A64P11, A64P12, A64P13, A64P14, A64P15, RvX0, RvX1, RvX2, RvX3, RvX4, RvX5, RvX6, RvX7, RvX8, RvX9, RvX10, RvX11, RvX12, RvX13, RvX14, RvX15, RvX16, RvX17, RvX18, RvX19, RvX20, RvX21, RvX22, RvX23, RvX24, RvX25, RvX26, RvX27, RvX28, RvX29, RvX30, RvX31, RvF0, RvF1, RvF2, RvF3, RvF4, RvF5, RvF6, RvF7, RvF8, RvF9, RvF10, RvF11, RvF12, RvF13, RvF14, RvF15, RvF16, RvF17, RvF18, RvF19, RvF20, RvF21, RvF22, RvF23, RvF24, RvF25, RvF26, RvF27, RvF28, RvF29, RvF30, RvF31, RvV0, RvV1, RvV2, RvV3, RvV4, RvV5, RvV6, RvV7, RvV8, RvV9, RvV10, RvV11, RvV12, RvV13, RvV14, RvV15, RvV16, RvV17, RvV18, RvV19, RvV20, RvV21, RvV22, RvV23, RvV24, RvV25, RvV26, RvV27, RvV28, RvV29, RvV30, RvV31,
}
Expand description

x86/x64 register.

Covers all general-purpose, segment, control, and SSE registers for 16-bit through 64-bit modes. Each variant encodes its own size (see Register::size_bits) and register number (see Register::base_code).

Variants§

§

Rax

RAX — 64-bit accumulator.

§

Rcx

RCX — 64-bit counter.

§

Rdx

RDX — 64-bit data.

§

Rbx

RBX — 64-bit base.

§

Rsp

RSP — 64-bit stack pointer.

§

Rbp

RBP — 64-bit frame pointer.

§

Rsi

RSI — 64-bit source index.

§

Rdi

RDI — 64-bit destination index.

§

R8

R8–R15 — extended 64-bit registers (require REX prefix).

§

R9

Extended 64-bit register.

§

R10

Extended 64-bit register.

§

R11

Extended 64-bit register.

§

R12

Extended 64-bit register.

§

R13

Extended 64-bit register.

§

R14

Extended 64-bit register.

§

R15

Extended 64-bit register.

§

Eax

EAX — 32-bit accumulator.

§

Ecx

ECX — 32-bit counter.

§

Edx

EDX — 32-bit data.

§

Ebx

EBX — 32-bit base.

§

Esp

ESP — 32-bit stack pointer.

§

Ebp

EBP — 32-bit frame pointer.

§

Esi

ESI — 32-bit source index.

§

Edi

EDI — 32-bit destination index.

§

R8d

R8D–R15D — low 32 bits of extended registers.

§

R9d

Low 32 bits of R9.

§

R10d

Low 32 bits of R10.

§

R11d

Low 32 bits of R11.

§

R12d

Low 32 bits of R12.

§

R13d

Low 32 bits of R13.

§

R14d

Low 32 bits of R14.

§

R15d

Low 32 bits of R15.

§

Ax

AX — 16-bit accumulator.

§

Cx

CX — 16-bit counter.

§

Dx

DX — 16-bit data.

§

Bx

BX — 16-bit base.

§

Sp

SP — 16-bit stack pointer.

§

Bp

BP — 16-bit frame pointer.

§

Si

SI — 16-bit source index.

§

Di

DI — 16-bit destination index.

§

R8w

R8W–R15W — low 16 bits of extended registers.

§

R9w

Low 16 bits of R9.

§

R10w

Low 16 bits of R10.

§

R11w

Low 16 bits of R11.

§

R12w

Low 16 bits of R12.

§

R13w

Low 16 bits of R13.

§

R14w

Low 16 bits of R14.

§

R15w

Low 16 bits of R15.

§

Al

AL — low byte of RAX.

§

Cl

CL — low byte of RCX.

§

Dl

DL — low byte of RDX.

§

Bl

BL — low byte of RBX.

§

Spl

SPL — low byte of RSP (requires REX).

§

Bpl

BPL — low byte of RBP (requires REX).

§

Sil

SIL — low byte of RSI (requires REX).

§

Dil

DIL — low byte of RDI (requires REX).

§

Ah

AH — high byte of AX (incompatible with REX prefix).

§

Ch

CH — high byte of CX (incompatible with REX prefix).

§

Dh

DH — high byte of DX (incompatible with REX prefix).

§

Bh

BH — high byte of BX (incompatible with REX prefix).

§

R8b

R8B–R15B — low byte of extended registers.

§

R9b

Low byte of R9.

§

R10b

Low byte of R10.

§

R11b

Low byte of R11.

§

R12b

Low byte of R12.

§

R13b

Low byte of R13.

§

R14b

Low byte of R14.

§

R15b

Low byte of R15.

§

Rip

RIP — 64-bit instruction pointer (for RIP-relative addressing).

§

Eip

EIP — 32-bit instruction pointer.

§

Cs

CS — code segment.

§

Ds

DS — data segment.

§

Es

ES — extra segment.

§

Fs

FS — additional segment (used for TLS on x86-64 Linux).

§

Gs

GS — additional segment (used for TLS on x86-64 Windows/macOS).

§

Ss

SS — stack segment.

§

Xmm0

XMM0 — SSE register 0.

§

Xmm1

SSE register 1.

§

Xmm2

SSE register 2.

§

Xmm3

SSE register 3.

§

Xmm4

SSE register 4.

§

Xmm5

SSE register 5.

§

Xmm6

SSE register 6.

§

Xmm7

SSE register 7.

§

Xmm8

XMM8–XMM15 — extended SSE registers (require REX prefix).

§

Xmm9

Extended SSE register 9.

§

Xmm10

Extended SSE register 10.

§

Xmm11

Extended SSE register 11.

§

Xmm12

Extended SSE register 12.

§

Xmm13

Extended SSE register 13.

§

Xmm14

Extended SSE register 14.

§

Xmm15

Extended SSE register 15.

§

Ymm0

YMM0 — AVX register 0.

§

Ymm1

AVX register 1.

§

Ymm2

AVX register 2.

§

Ymm3

AVX register 3.

§

Ymm4

AVX register 4.

§

Ymm5

AVX register 5.

§

Ymm6

AVX register 6.

§

Ymm7

AVX register 7.

§

Ymm8

YMM8–YMM15 — extended AVX registers.

§

Ymm9

Extended AVX register 9.

§

Ymm10

Extended AVX register 10.

§

Ymm11

Extended AVX register 11.

§

Ymm12

Extended AVX register 12.

§

Ymm13

Extended AVX register 13.

§

Ymm14

Extended AVX register 14.

§

Ymm15

Extended AVX register 15.

§

Zmm0

ZMM0 — AVX-512 register 0.

§

Zmm1

AVX-512 register 1.

§

Zmm2

AVX-512 register 2.

§

Zmm3

AVX-512 register 3.

§

Zmm4

AVX-512 register 4.

§

Zmm5

AVX-512 register 5.

§

Zmm6

AVX-512 register 6.

§

Zmm7

AVX-512 register 7.

§

Zmm8

ZMM8–ZMM15 — extended by REX/VEX.

§

Zmm9

AVX-512 register 9.

§

Zmm10

AVX-512 register 10.

§

Zmm11

AVX-512 register 11.

§

Zmm12

AVX-512 register 12.

§

Zmm13

AVX-512 register 13.

§

Zmm14

AVX-512 register 14.

§

Zmm15

AVX-512 register 15.

§

Zmm16

ZMM16–ZMM31 — EVEX-only registers.

§

Zmm17

EVEX-only AVX-512 register 17.

§

Zmm18

EVEX-only AVX-512 register 18.

§

Zmm19

EVEX-only AVX-512 register 19.

§

Zmm20

EVEX-only AVX-512 register 20.

§

Zmm21

EVEX-only AVX-512 register 21.

§

Zmm22

EVEX-only AVX-512 register 22.

§

Zmm23

EVEX-only AVX-512 register 23.

§

Zmm24

EVEX-only AVX-512 register 24.

§

Zmm25

EVEX-only AVX-512 register 25.

§

Zmm26

EVEX-only AVX-512 register 26.

§

Zmm27

EVEX-only AVX-512 register 27.

§

Zmm28

EVEX-only AVX-512 register 28.

§

Zmm29

EVEX-only AVX-512 register 29.

§

Zmm30

EVEX-only AVX-512 register 30.

§

Zmm31

EVEX-only AVX-512 register 31.

§

K0

K0 — opmask register 0 (implicit, means “no mask”).

§

K1

K1 — opmask register 1.

§

K2

K2 — opmask register 2.

§

K3

K3 — opmask register 3.

§

K4

K4 — opmask register 4.

§

K5

K5 — opmask register 5.

§

K6

K6 — opmask register 6.

§

K7

K7 — opmask register 7.

§

ArmR0

ARM R0.

§

ArmR1

ARM R1.

§

ArmR2

ARM R2.

§

ArmR3

ARM R3.

§

ArmR4

ARM R4.

§

ArmR5

ARM R5.

§

ArmR6

ARM R6.

§

ArmR7

ARM R7.

§

ArmR8

ARM R8.

§

ArmR9

ARM R9.

§

ArmR10

ARM R10.

§

ArmR11

ARM R11 (FP by convention).

§

ArmR12

ARM R12 (IP — intra-procedure scratch).

§

ArmSp

ARM R13 / SP — stack pointer.

§

ArmLr

ARM R14 / LR — link register.

§

ArmPc

ARM R15 / PC — program counter.

§

ArmCpsr

ARM CPSR — current program status register.

§

A64X0

AArch64 X0.

§

A64X1

AArch64 X1.

§

A64X2

AArch64 X2.

§

A64X3

AArch64 X3.

§

A64X4

AArch64 X4.

§

A64X5

AArch64 X5.

§

A64X6

AArch64 X6.

§

A64X7

AArch64 X7.

§

A64X8

AArch64 X8.

§

A64X9

AArch64 X9.

§

A64X10

AArch64 X10.

§

A64X11

AArch64 X11.

§

A64X12

AArch64 X12.

§

A64X13

AArch64 X13.

§

A64X14

AArch64 X14.

§

A64X15

AArch64 X15.

§

A64X16

AArch64 X16.

§

A64X17

AArch64 X17.

§

A64X18

AArch64 X18.

§

A64X19

AArch64 X19.

§

A64X20

AArch64 X20.

§

A64X21

AArch64 X21.

§

A64X22

AArch64 X22.

§

A64X23

AArch64 X23.

§

A64X24

AArch64 X24.

§

A64X25

AArch64 X25.

§

A64X26

AArch64 X26.

§

A64X27

AArch64 X27.

§

A64X28

AArch64 X28.

§

A64X29

AArch64 X29 / FP — frame pointer.

§

A64X30

AArch64 X30 / LR — link register.

§

A64Sp

AArch64 SP — stack pointer (64-bit).

§

A64Xzr

AArch64 XZR — zero register (64-bit).

§

A64W0

AArch64 W0.

§

A64W1

AArch64 W1.

§

A64W2

AArch64 W2.

§

A64W3

AArch64 W3.

§

A64W4

AArch64 W4.

§

A64W5

AArch64 W5.

§

A64W6

AArch64 W6.

§

A64W7

AArch64 W7.

§

A64W8

AArch64 W8.

§

A64W9

AArch64 W9.

§

A64W10

AArch64 W10.

§

A64W11

AArch64 W11.

§

A64W12

AArch64 W12.

§

A64W13

AArch64 W13.

§

A64W14

AArch64 W14.

§

A64W15

AArch64 W15.

§

A64W16

AArch64 W16.

§

A64W17

AArch64 W17.

§

A64W18

AArch64 W18.

§

A64W19

AArch64 W19.

§

A64W20

AArch64 W20.

§

A64W21

AArch64 W21.

§

A64W22

AArch64 W22.

§

A64W23

AArch64 W23.

§

A64W24

AArch64 W24.

§

A64W25

AArch64 W25.

§

A64W26

AArch64 W26.

§

A64W27

AArch64 W27.

§

A64W28

AArch64 W28.

§

A64W29

AArch64 W29.

§

A64W30

AArch64 W30.

§

A64Wzr

AArch64 WZR — zero register (32-bit).

§

A64V0

AArch64 128-bit SIMD/FP register V0.

§

A64V1

AArch64 128-bit SIMD/FP register V1.

§

A64V2

AArch64 128-bit SIMD/FP register V2.

§

A64V3

AArch64 128-bit SIMD/FP register V3.

§

A64V4

AArch64 128-bit SIMD/FP register V4.

§

A64V5

AArch64 128-bit SIMD/FP register V5.

§

A64V6

AArch64 128-bit SIMD/FP register V6.

§

A64V7

AArch64 128-bit SIMD/FP register V7.

§

A64V8

AArch64 128-bit SIMD/FP register V8.

§

A64V9

AArch64 128-bit SIMD/FP register V9.

§

A64V10

AArch64 128-bit SIMD/FP register V10.

§

A64V11

AArch64 128-bit SIMD/FP register V11.

§

A64V12

AArch64 128-bit SIMD/FP register V12.

§

A64V13

AArch64 128-bit SIMD/FP register V13.

§

A64V14

AArch64 128-bit SIMD/FP register V14.

§

A64V15

AArch64 128-bit SIMD/FP register V15.

§

A64V16

AArch64 128-bit SIMD/FP register V16.

§

A64V17

AArch64 128-bit SIMD/FP register V17.

§

A64V18

AArch64 128-bit SIMD/FP register V18.

§

A64V19

AArch64 128-bit SIMD/FP register V19.

§

A64V20

AArch64 128-bit SIMD/FP register V20.

§

A64V21

AArch64 128-bit SIMD/FP register V21.

§

A64V22

AArch64 128-bit SIMD/FP register V22.

§

A64V23

AArch64 128-bit SIMD/FP register V23.

§

A64V24

AArch64 128-bit SIMD/FP register V24.

§

A64V25

AArch64 128-bit SIMD/FP register V25.

§

A64V26

AArch64 128-bit SIMD/FP register V26.

§

A64V27

AArch64 128-bit SIMD/FP register V27.

§

A64V28

AArch64 128-bit SIMD/FP register V28.

§

A64V29

AArch64 128-bit SIMD/FP register V29.

§

A64V30

AArch64 128-bit SIMD/FP register V30.

§

A64V31

AArch64 128-bit SIMD/FP register V31.

§

A64Q0

AArch64 128-bit scalar quad register Q0.

§

A64Q1

AArch64 128-bit scalar quad register Q1.

§

A64Q2

AArch64 128-bit scalar quad register Q2.

§

A64Q3

AArch64 128-bit scalar quad register Q3.

§

A64Q4

AArch64 128-bit scalar quad register Q4.

§

A64Q5

AArch64 128-bit scalar quad register Q5.

§

A64Q6

AArch64 128-bit scalar quad register Q6.

§

A64Q7

AArch64 128-bit scalar quad register Q7.

§

A64Q8

AArch64 128-bit scalar quad register Q8.

§

A64Q9

AArch64 128-bit scalar quad register Q9.

§

A64Q10

AArch64 128-bit scalar quad register Q10.

§

A64Q11

AArch64 128-bit scalar quad register Q11.

§

A64Q12

AArch64 128-bit scalar quad register Q12.

§

A64Q13

AArch64 128-bit scalar quad register Q13.

§

A64Q14

AArch64 128-bit scalar quad register Q14.

§

A64Q15

AArch64 128-bit scalar quad register Q15.

§

A64Q16

AArch64 128-bit scalar quad register Q16.

§

A64Q17

AArch64 128-bit scalar quad register Q17.

§

A64Q18

AArch64 128-bit scalar quad register Q18.

§

A64Q19

AArch64 128-bit scalar quad register Q19.

§

A64Q20

AArch64 128-bit scalar quad register Q20.

§

A64Q21

AArch64 128-bit scalar quad register Q21.

§

A64Q22

AArch64 128-bit scalar quad register Q22.

§

A64Q23

AArch64 128-bit scalar quad register Q23.

§

A64Q24

AArch64 128-bit scalar quad register Q24.

§

A64Q25

AArch64 128-bit scalar quad register Q25.

§

A64Q26

AArch64 128-bit scalar quad register Q26.

§

A64Q27

AArch64 128-bit scalar quad register Q27.

§

A64Q28

AArch64 128-bit scalar quad register Q28.

§

A64Q29

AArch64 128-bit scalar quad register Q29.

§

A64Q30

AArch64 128-bit scalar quad register Q30.

§

A64Q31

AArch64 128-bit scalar quad register Q31.

§

A64D0

AArch64 64-bit scalar double register D0.

§

A64D1

AArch64 64-bit scalar double register D1.

§

A64D2

AArch64 64-bit scalar double register D2.

§

A64D3

AArch64 64-bit scalar double register D3.

§

A64D4

AArch64 64-bit scalar double register D4.

§

A64D5

AArch64 64-bit scalar double register D5.

§

A64D6

AArch64 64-bit scalar double register D6.

§

A64D7

AArch64 64-bit scalar double register D7.

§

A64D8

AArch64 64-bit scalar double register D8.

§

A64D9

AArch64 64-bit scalar double register D9.

§

A64D10

AArch64 64-bit scalar double register D10.

§

A64D11

AArch64 64-bit scalar double register D11.

§

A64D12

AArch64 64-bit scalar double register D12.

§

A64D13

AArch64 64-bit scalar double register D13.

§

A64D14

AArch64 64-bit scalar double register D14.

§

A64D15

AArch64 64-bit scalar double register D15.

§

A64D16

AArch64 64-bit scalar double register D16.

§

A64D17

AArch64 64-bit scalar double register D17.

§

A64D18

AArch64 64-bit scalar double register D18.

§

A64D19

AArch64 64-bit scalar double register D19.

§

A64D20

AArch64 64-bit scalar double register D20.

§

A64D21

AArch64 64-bit scalar double register D21.

§

A64D22

AArch64 64-bit scalar double register D22.

§

A64D23

AArch64 64-bit scalar double register D23.

§

A64D24

AArch64 64-bit scalar double register D24.

§

A64D25

AArch64 64-bit scalar double register D25.

§

A64D26

AArch64 64-bit scalar double register D26.

§

A64D27

AArch64 64-bit scalar double register D27.

§

A64D28

AArch64 64-bit scalar double register D28.

§

A64D29

AArch64 64-bit scalar double register D29.

§

A64D30

AArch64 64-bit scalar double register D30.

§

A64D31

AArch64 64-bit scalar double register D31.

§

A64S0

AArch64 32-bit scalar single register S0.

§

A64S1

AArch64 32-bit scalar single register S1.

§

A64S2

AArch64 32-bit scalar single register S2.

§

A64S3

AArch64 32-bit scalar single register S3.

§

A64S4

AArch64 32-bit scalar single register S4.

§

A64S5

AArch64 32-bit scalar single register S5.

§

A64S6

AArch64 32-bit scalar single register S6.

§

A64S7

AArch64 32-bit scalar single register S7.

§

A64S8

AArch64 32-bit scalar single register S8.

§

A64S9

AArch64 32-bit scalar single register S9.

§

A64S10

AArch64 32-bit scalar single register S10.

§

A64S11

AArch64 32-bit scalar single register S11.

§

A64S12

AArch64 32-bit scalar single register S12.

§

A64S13

AArch64 32-bit scalar single register S13.

§

A64S14

AArch64 32-bit scalar single register S14.

§

A64S15

AArch64 32-bit scalar single register S15.

§

A64S16

AArch64 32-bit scalar single register S16.

§

A64S17

AArch64 32-bit scalar single register S17.

§

A64S18

AArch64 32-bit scalar single register S18.

§

A64S19

AArch64 32-bit scalar single register S19.

§

A64S20

AArch64 32-bit scalar single register S20.

§

A64S21

AArch64 32-bit scalar single register S21.

§

A64S22

AArch64 32-bit scalar single register S22.

§

A64S23

AArch64 32-bit scalar single register S23.

§

A64S24

AArch64 32-bit scalar single register S24.

§

A64S25

AArch64 32-bit scalar single register S25.

§

A64S26

AArch64 32-bit scalar single register S26.

§

A64S27

AArch64 32-bit scalar single register S27.

§

A64S28

AArch64 32-bit scalar single register S28.

§

A64S29

AArch64 32-bit scalar single register S29.

§

A64S30

AArch64 32-bit scalar single register S30.

§

A64S31

AArch64 32-bit scalar single register S31.

§

A64H0

AArch64 16-bit scalar half register H0.

§

A64H1

AArch64 16-bit scalar half register H1.

§

A64H2

AArch64 16-bit scalar half register H2.

§

A64H3

AArch64 16-bit scalar half register H3.

§

A64H4

AArch64 16-bit scalar half register H4.

§

A64H5

AArch64 16-bit scalar half register H5.

§

A64H6

AArch64 16-bit scalar half register H6.

§

A64H7

AArch64 16-bit scalar half register H7.

§

A64H8

AArch64 16-bit scalar half register H8.

§

A64H9

AArch64 16-bit scalar half register H9.

§

A64H10

AArch64 16-bit scalar half register H10.

§

A64H11

AArch64 16-bit scalar half register H11.

§

A64H12

AArch64 16-bit scalar half register H12.

§

A64H13

AArch64 16-bit scalar half register H13.

§

A64H14

AArch64 16-bit scalar half register H14.

§

A64H15

AArch64 16-bit scalar half register H15.

§

A64H16

AArch64 16-bit scalar half register H16.

§

A64H17

AArch64 16-bit scalar half register H17.

§

A64H18

AArch64 16-bit scalar half register H18.

§

A64H19

AArch64 16-bit scalar half register H19.

§

A64H20

AArch64 16-bit scalar half register H20.

§

A64H21

AArch64 16-bit scalar half register H21.

§

A64H22

AArch64 16-bit scalar half register H22.

§

A64H23

AArch64 16-bit scalar half register H23.

§

A64H24

AArch64 16-bit scalar half register H24.

§

A64H25

AArch64 16-bit scalar half register H25.

§

A64H26

AArch64 16-bit scalar half register H26.

§

A64H27

AArch64 16-bit scalar half register H27.

§

A64H28

AArch64 16-bit scalar half register H28.

§

A64H29

AArch64 16-bit scalar half register H29.

§

A64H30

AArch64 16-bit scalar half register H30.

§

A64H31

AArch64 16-bit scalar half register H31.

§

A64B0

AArch64 8-bit scalar byte register B0.

§

A64B1

AArch64 8-bit scalar byte register B1.

§

A64B2

AArch64 8-bit scalar byte register B2.

§

A64B3

AArch64 8-bit scalar byte register B3.

§

A64B4

AArch64 8-bit scalar byte register B4.

§

A64B5

AArch64 8-bit scalar byte register B5.

§

A64B6

AArch64 8-bit scalar byte register B6.

§

A64B7

AArch64 8-bit scalar byte register B7.

§

A64B8

AArch64 8-bit scalar byte register B8.

§

A64B9

AArch64 8-bit scalar byte register B9.

§

A64B10

AArch64 8-bit scalar byte register B10.

§

A64B11

AArch64 8-bit scalar byte register B11.

§

A64B12

AArch64 8-bit scalar byte register B12.

§

A64B13

AArch64 8-bit scalar byte register B13.

§

A64B14

AArch64 8-bit scalar byte register B14.

§

A64B15

AArch64 8-bit scalar byte register B15.

§

A64B16

AArch64 8-bit scalar byte register B16.

§

A64B17

AArch64 8-bit scalar byte register B17.

§

A64B18

AArch64 8-bit scalar byte register B18.

§

A64B19

AArch64 8-bit scalar byte register B19.

§

A64B20

AArch64 8-bit scalar byte register B20.

§

A64B21

AArch64 8-bit scalar byte register B21.

§

A64B22

AArch64 8-bit scalar byte register B22.

§

A64B23

AArch64 8-bit scalar byte register B23.

§

A64B24

AArch64 8-bit scalar byte register B24.

§

A64B25

AArch64 8-bit scalar byte register B25.

§

A64B26

AArch64 8-bit scalar byte register B26.

§

A64B27

AArch64 8-bit scalar byte register B27.

§

A64B28

AArch64 8-bit scalar byte register B28.

§

A64B29

AArch64 8-bit scalar byte register B29.

§

A64B30

AArch64 8-bit scalar byte register B30.

§

A64B31

AArch64 8-bit scalar byte register B31.

§

A64Z0

AArch64 SVE scalable vector register Z0.

§

A64Z1

AArch64 SVE scalable vector register Z1.

§

A64Z2

AArch64 SVE scalable vector register Z2.

§

A64Z3

AArch64 SVE scalable vector register Z3.

§

A64Z4

AArch64 SVE scalable vector register Z4.

§

A64Z5

AArch64 SVE scalable vector register Z5.

§

A64Z6

AArch64 SVE scalable vector register Z6.

§

A64Z7

AArch64 SVE scalable vector register Z7.

§

A64Z8

AArch64 SVE scalable vector register Z8.

§

A64Z9

AArch64 SVE scalable vector register Z9.

§

A64Z10

AArch64 SVE scalable vector register Z10.

§

A64Z11

AArch64 SVE scalable vector register Z11.

§

A64Z12

AArch64 SVE scalable vector register Z12.

§

A64Z13

AArch64 SVE scalable vector register Z13.

§

A64Z14

AArch64 SVE scalable vector register Z14.

§

A64Z15

AArch64 SVE scalable vector register Z15.

§

A64Z16

AArch64 SVE scalable vector register Z16.

§

A64Z17

AArch64 SVE scalable vector register Z17.

§

A64Z18

AArch64 SVE scalable vector register Z18.

§

A64Z19

AArch64 SVE scalable vector register Z19.

§

A64Z20

AArch64 SVE scalable vector register Z20.

§

A64Z21

AArch64 SVE scalable vector register Z21.

§

A64Z22

AArch64 SVE scalable vector register Z22.

§

A64Z23

AArch64 SVE scalable vector register Z23.

§

A64Z24

AArch64 SVE scalable vector register Z24.

§

A64Z25

AArch64 SVE scalable vector register Z25.

§

A64Z26

AArch64 SVE scalable vector register Z26.

§

A64Z27

AArch64 SVE scalable vector register Z27.

§

A64Z28

AArch64 SVE scalable vector register Z28.

§

A64Z29

AArch64 SVE scalable vector register Z29.

§

A64Z30

AArch64 SVE scalable vector register Z30.

§

A64Z31

AArch64 SVE scalable vector register Z31.

§

A64P0

AArch64 SVE predicate register P0.

§

A64P1

AArch64 SVE predicate register P1.

§

A64P2

AArch64 SVE predicate register P2.

§

A64P3

AArch64 SVE predicate register P3.

§

A64P4

AArch64 SVE predicate register P4.

§

A64P5

AArch64 SVE predicate register P5.

§

A64P6

AArch64 SVE predicate register P6.

§

A64P7

AArch64 SVE predicate register P7.

§

A64P8

AArch64 SVE predicate register P8.

§

A64P9

AArch64 SVE predicate register P9.

§

A64P10

AArch64 SVE predicate register P10.

§

A64P11

AArch64 SVE predicate register P11.

§

A64P12

AArch64 SVE predicate register P12.

§

A64P13

AArch64 SVE predicate register P13.

§

A64P14

AArch64 SVE predicate register P14.

§

A64P15

AArch64 SVE predicate register P15.

§

RvX0

RISC-V x0 / zero — hardwired zero.

§

RvX1

RISC-V x1 / ra — return address.

§

RvX2

RISC-V x2 / sp — stack pointer.

§

RvX3

RISC-V x3 / gp — global pointer.

§

RvX4

RISC-V x4 / tp — thread pointer.

§

RvX5

RISC-V x5 / t0 — temporary.

§

RvX6

RISC-V x6 / t1 — temporary.

§

RvX7

RISC-V x7 / t2 — temporary.

§

RvX8

RISC-V x8 / s0 / fp — saved / frame pointer.

§

RvX9

RISC-V x9 / s1 — saved register.

§

RvX10

RISC-V x10 / a0 — argument / return value.

§

RvX11

RISC-V x11 / a1 — argument / return value.

§

RvX12

RISC-V x12 / a2 — argument.

§

RvX13

RISC-V x13 / a3 — argument.

§

RvX14

RISC-V x14 / a4 — argument.

§

RvX15

RISC-V x15 / a5 — argument.

§

RvX16

RISC-V x16 / a6 — argument.

§

RvX17

RISC-V x17 / a7 — argument.

§

RvX18

RISC-V x18 / s2 — saved register.

§

RvX19

RISC-V x19 / s3 — saved register.

§

RvX20

RISC-V x20 / s4 — saved register.

§

RvX21

RISC-V x21 / s5 — saved register.

§

RvX22

RISC-V x22 / s6 — saved register.

§

RvX23

RISC-V x23 / s7 — saved register.

§

RvX24

RISC-V x24 / s8 — saved register.

§

RvX25

RISC-V x25 / s9 — saved register.

§

RvX26

RISC-V x26 / s10 — saved register.

§

RvX27

RISC-V x27 / s11 — saved register.

§

RvX28

RISC-V x28 / t3 — temporary.

§

RvX29

RISC-V x29 / t4 — temporary.

§

RvX30

RISC-V x30 / t5 — temporary.

§

RvX31

RISC-V x31 / t6 — temporary.

§

RvF0

RISC-V f0 / ft0 — FP temporary.

§

RvF1

RISC-V f1 / ft1 — FP temporary.

§

RvF2

RISC-V f2 / ft2 — FP temporary.

§

RvF3

RISC-V f3 / ft3 — FP temporary.

§

RvF4

RISC-V f4 / ft4 — FP temporary.

§

RvF5

RISC-V f5 / ft5 — FP temporary.

§

RvF6

RISC-V f6 / ft6 — FP temporary.

§

RvF7

RISC-V f7 / ft7 — FP temporary.

§

RvF8

RISC-V f8 / fs0 — FP saved register.

§

RvF9

RISC-V f9 / fs1 — FP saved register.

§

RvF10

RISC-V f10 / fa0 — FP argument/return value.

§

RvF11

RISC-V f11 / fa1 — FP argument/return value.

§

RvF12

RISC-V f12 / fa2 — FP argument.

§

RvF13

RISC-V f13 / fa3 — FP argument.

§

RvF14

RISC-V f14 / fa4 — FP argument.

§

RvF15

RISC-V f15 / fa5 — FP argument.

§

RvF16

RISC-V f16 / fa6 — FP argument.

§

RvF17

RISC-V f17 / fa7 — FP argument.

§

RvF18

RISC-V f18 / fs2 — FP saved register.

§

RvF19

RISC-V f19 / fs3 — FP saved register.

§

RvF20

RISC-V f20 / fs4 — FP saved register.

§

RvF21

RISC-V f21 / fs5 — FP saved register.

§

RvF22

RISC-V f22 / fs6 — FP saved register.

§

RvF23

RISC-V f23 / fs7 — FP saved register.

§

RvF24

RISC-V f24 / fs8 — FP saved register.

§

RvF25

RISC-V f25 / fs9 — FP saved register.

§

RvF26

RISC-V f26 / fs10 — FP saved register.

§

RvF27

RISC-V f27 / fs11 — FP saved register.

§

RvF28

RISC-V f28 / ft8 — FP temporary.

§

RvF29

RISC-V f29 / ft9 — FP temporary.

§

RvF30

RISC-V f30 / ft10 — FP temporary.

§

RvF31

RISC-V f31 / ft11 — FP temporary.

§

RvV0

RISC-V vector register v0 (also used as mask).

§

RvV1

RISC-V vector register v1.

§

RvV2

RISC-V vector register v2.

§

RvV3

RISC-V vector register v3.

§

RvV4

RISC-V vector register v4.

§

RvV5

RISC-V vector register v5.

§

RvV6

RISC-V vector register v6.

§

RvV7

RISC-V vector register v7.

§

RvV8

RISC-V vector register v8.

§

RvV9

RISC-V vector register v9.

§

RvV10

RISC-V vector register v10.

§

RvV11

RISC-V vector register v11.

§

RvV12

RISC-V vector register v12.

§

RvV13

RISC-V vector register v13.

§

RvV14

RISC-V vector register v14.

§

RvV15

RISC-V vector register v15.

§

RvV16

RISC-V vector register v16.

§

RvV17

RISC-V vector register v17.

§

RvV18

RISC-V vector register v18.

§

RvV19

RISC-V vector register v19.

§

RvV20

RISC-V vector register v20.

§

RvV21

RISC-V vector register v21.

§

RvV22

RISC-V vector register v22.

§

RvV23

RISC-V vector register v23.

§

RvV24

RISC-V vector register v24.

§

RvV25

RISC-V vector register v25.

§

RvV26

RISC-V vector register v26.

§

RvV27

RISC-V vector register v27.

§

RvV28

RISC-V vector register v28.

§

RvV29

RISC-V vector register v29.

§

RvV30

RISC-V vector register v30.

§

RvV31

RISC-V vector register v31.

Implementations§

Source§

impl Register

Source

pub fn base_code(self) -> u8

The 3-bit register encoding (bits 0-2 of the register number).

Source

pub fn is_extended(self) -> bool

Whether this is an extended register (R8–R15, Xmm8–Xmm15, Ymm8–Ymm15, Zmm8–Zmm15, Zmm24–Zmm31) requiring REX/VEX.R or REX/VEX.B (bit 3 of the register index).

Source

pub fn is_evex_extended(self) -> bool

Whether this register requires EVEX (ZMM16–ZMM31). These need the EVEX.R’ and/or EVEX.V’ bits.

Source

pub fn size_bits(self) -> u16

Size of the register in bits.

Source

pub fn requires_rex_for_byte(self) -> bool

Whether this register requires a REX prefix to be addressable as an 8-bit register. SPL, BPL, SIL, DIL need REX (even if REX.{W,R,X,B} are all 0).

Source

pub fn is_high_byte(self) -> bool

Whether this is a high-byte register (AH, CH, DH, BH). These cannot be used with REX prefix.

Source

pub fn is_xmm(self) -> bool

Whether this is an XMM (SSE) register.

Source

pub fn is_ymm(self) -> bool

Whether this is a YMM (AVX) register.

Source

pub fn is_zmm(self) -> bool

Whether this is a ZMM (AVX-512) register.

Source

pub fn is_opmask(self) -> bool

Whether this is an opmask register (K0–K7).

Source

pub fn is_vector(self) -> bool

Whether this is any vector register (XMM, YMM, or ZMM).

Source

pub fn to_32bit(self) -> Option<Register>

Return the 32-bit counterpart of this register, if applicable.

For 64-bit GP registers (RAX, RCX, …, R15), returns the corresponding 32-bit register. For registers that are already 32-bit, returns them unchanged. Returns None for 8-bit, 16-bit, segment, and vector registers.

Source

pub fn is_arm(self) -> bool

Whether this is an ARM32 register.

Source

pub fn arm_reg_num(self) -> u8

ARM32 4-bit register number (0–15).

Source

pub fn is_aarch64(self) -> bool

Whether this is an AArch64 register.

Source

pub fn a64_reg_num(self) -> u8

AArch64 5-bit register number (0–31, where 31 = SP or ZR depending on context).

Source

pub fn is_a64_vector(self) -> bool

Whether this is an AArch64 vector register (V0–V31).

Only V registers accept arrangement specifiers (e.g., V0.4S).

Source

pub fn is_a64_simd_fp(self) -> bool

Whether this is an AArch64 SIMD/FP register (V, Q, D, S, H, or B).

Source

pub fn a64_simd_fp_bits(self) -> u32

Returns the SIMD/FP register bit width (128 for V/Q, 64 for D, 32 for S, 16 for H, 8 for B).

Source

pub fn is_a64_64bit(self) -> bool

Whether this is a 64-bit AArch64 X register (vs 32-bit W register).

Source

pub fn is_riscv(self) -> bool

Whether this is a RISC-V integer register.

Source

pub fn rv_reg_num(self) -> u8

RISC-V 5-bit register number (0–31).

Source

pub fn is_riscv_fp(self) -> bool

Whether this is a RISC-V floating-point register (f0–f31).

Source

pub fn rv_fp_reg_num(self) -> u8

RISC-V FP 5-bit register number (0–31).

Source

pub fn is_a64_sve_z(self) -> bool

Whether this is an AArch64 SVE scalable vector register (Z0–Z31).

Source

pub fn is_a64_sve_p(self) -> bool

Whether this is an AArch64 SVE predicate register (P0–P15).

Source

pub fn a64_p_num(self) -> u8

AArch64 SVE predicate register number (0–15).

Source

pub fn is_riscv_vec(self) -> bool

Whether this is a RISC-V vector register (v0–v31).

Source

pub fn rv_vec_num(self) -> u8

RISC-V vector register number (0–31).

Trait Implementations§

Source§

impl Clone for Register

Source§

fn clone(&self) -> Register

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
Source§

impl Debug for Register

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
Source§

impl Display for Register

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
Source§

impl Hash for Register

Source§

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher. Read more
1.3.0 · Source§

fn hash_slice<H>(data: &[Self], state: &mut H)
where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher. Read more
Source§

impl PartialEq for Register

Source§

fn eq(&self, other: &Register) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
Source§

impl Copy for Register

Source§

impl Eq for Register

Source§

impl StructuralPartialEq for Register

Auto Trait Implementations§

Blanket Implementations§

Source§

impl<T> Any for T
where T: 'static + ?Sized,

Source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
Source§

impl<T> Borrow<T> for T
where T: ?Sized,

Source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
Source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

Source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
Source§

impl<T> CloneToUninit for T
where T: Clone,

Source§

unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
Source§

impl<T> From<T> for T

Source§

fn from(t: T) -> T

Returns the argument unchanged.

Source§

impl<T, U> Into<U> for T
where U: From<T>,

Source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

Source§

impl<T> ToOwned for T
where T: Clone,

Source§

type Owned = T

The resulting type after obtaining ownership.
Source§

fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
Source§

fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
Source§

impl<T> ToString for T
where T: Display + ?Sized,

Source§

fn to_string(&self) -> String

Converts the given value to a String. Read more
Source§

impl<T, U> TryFrom<U> for T
where U: Into<T>,

Source§

type Error = Infallible

The type returned in the event of a conversion error.
Source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
Source§

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

Source§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
Source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.