Enum RelocKind 

pub enum RelocKind {
    X86Relative,
    Absolute,
    ArmBranch24,
    ArmLdrLit,
    ArmAdr,
    ThumbBranch8,
    ThumbBranch11,
    ThumbBl,
    ThumbBranchW,
    ThumbCondBranchW,
    ThumbLdrLit8,
    Aarch64Jump26,
    Aarch64Branch19,
    Aarch64Branch14,
    Aarch64LdrLit19,
    Aarch64Adr21,
    Aarch64Adrp,
    Aarch64AdrpAddPair,
    RvJal20,
    RvBranch12,
    RvAuipc20,
    RvCBranch8,
    RvCJump11,
}

How the linker should patch the relocation target into the instruction.

Variants

X86Relative

x86 RIP-relative: raw i8/i32 displacement written at offset. trailing_bytes accounts for any immediate after the disp field.

Absolute

Absolute address written as raw LE bytes (1/2/4/8).

ArmBranch24

ARM32 B/BL: PC-relative offset >> 2 in bits 23:0 of the 32-bit word.

ArmLdrLit

ARM32 LDR literal (PC-relative): 12-bit offset in bits 11:0, U-bit in bit 23.

ArmAdr

ARM32 ADR (data-processing immediate): 8-bit value with 4-bit rotation in bits 11:0, ADD/SUB opcode in bits 24:21, U-sense via opcode (ADD=0x4, SUB=0x2).

ThumbBranch8

Thumb-2 conditional branch (16-bit): 8-bit signed offset >> 1 in bits 7:0. Range: ±256 bytes from PC+4.

ThumbBranch11

Thumb unconditional branch (16-bit): 11-bit signed offset >> 1 in bits 10:0. Range: ±2 KB from PC+4.

ThumbBl

Thumb-2 BL (32-bit): 25-bit offset across two halfwords. Range: ±16 MB.

ThumbBranchW

Thumb-2 B.W (32-bit wide unconditional branch): 24-bit offset. Range: ±16 MB.

ThumbCondBranchW

Thumb-2 B.cond.W (32-bit wide conditional branch): 20-bit offset. Range: ±1 MB.

ThumbLdrLit8

Thumb LDR Rt, [PC, #imm8×4]: 8-bit word-aligned PC-relative literal load. Range: 0–1020 bytes forward only. PC = (instr_addr + 4) & ~3.

Aarch64Jump26

AArch64 B/BL: PC-relative offset >> 2 in bits 25:0 of the 32-bit word.

Aarch64Branch19

AArch64 B.cond / CBZ / CBNZ: PC-relative offset >> 2 in bits 23:5.

Aarch64Branch14

AArch64 TBZ / TBNZ: PC-relative offset >> 2 in bits 18:5 (14-bit imm).

Aarch64LdrLit19

AArch64 LDR (literal): PC-relative offset >> 2 in bits 23:5.

Aarch64Adr21

AArch64 ADR: PC-relative offset with immhi (bits 23:5) and immlo (bits 30:29).

Aarch64Adrp

AArch64 ADRP: page-relative offset with immhi/immlo, target &= ~0xFFF.

Aarch64AdrpAddPair

AArch64 ADRP+ADD pair (8 bytes): ADR relaxation long form. The first word is ADRP (patched with page offset), the second word is ADD (patched with lo12 = target & 0xFFF).

RvJal20

RISC-V JAL: PC-relative offset in J-type immediate (bits 31:12), ±1MB range.

RvBranch12

RISC-V B-type branch: PC-relative offset in B-type immediate (bits 31:7), ±4KB range.

RvAuipc20

RISC-V AUIPC: upper 20 bits of PC-relative offset (bits 31:12).

RvCBranch8

RISC-V C-extension CB-type branch: 9-bit signed PC-relative offset (±256 B).

RvCJump11

RISC-V C-extension CJ-type jump: 12-bit signed PC-relative offset (±2 KB).

Trait Implementations

impl Clone for RelocKind

fn clone(&self) -> RelocKind

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RelocKind

impl Debug for RelocKind

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for RelocKind

impl PartialEq for RelocKind

fn eq(&self, other: &RelocKind) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for RelocKind