Struct VgicCore 

pub struct VgicCore { /* private fields */ }

The single canonical virtual interrupt-controller state owner for one VM.

Implementations

impl VgicCore

pub fn new( config: ArmVgicConfig, backend: Arc<dyn GicV3Backend>, ) -> VgicResult<Self>

Creates a VGIC without a guest-memory ITS capability.

pub fn new_with_guest_memory( config: ArmVgicConfig, backend: Arc<dyn GicV3Backend>, guest_memory: Option<Arc<dyn GuestMemory>>, ) -> VgicResult<Self>

Creates a VGIC with checked guest-memory access for an optional ITS.

pub const fn config(&self) -> &ArmVgicConfig

Returns the immutable configuration used for construction and firmware.

pub const fn id(&self) -> InterruptControllerId

Returns the VM-local controller identifier.

pub const fn controller(&self) -> &VgicController

Returns the underlying canonical controller for architecture frontends.

pub fn read_v2_distributor( &self, vcpu: GicVcpuId, offset: u64, width: AccessWidth, ) -> VgicResult<u64>

Reads the configured GICv2 Distributor frontend.

pub fn write_v2_distributor( &self, vcpu: GicVcpuId, offset: u64, width: AccessWidth, value: u64, ) -> VgicResult

Writes the configured GICv2 Distributor frontend.

pub fn read_v2_cpu_interface( &self, vcpu: GicVcpuId, offset: u64, width: AccessWidth, ) -> VgicResult<u64>

Reads the configured GICv2 CPU-interface frontend.

pub fn write_v2_cpu_interface( &self, vcpu: GicVcpuId, offset: u64, width: AccessWidth, value: u64, ) -> VgicResult

Writes the configured GICv2 CPU-interface frontend.

pub fn attach_vcpu( &self, vcpu: usize, wake: Arc<dyn GicV3VcpuWake>, ) -> VgicResult<GicV3VcpuBinding>

Attaches one configured vCPU.

pub fn bind_assigned_spis(&self) -> VgicResult

Installs every physical SPI fixed by the immutable configuration.

pub fn unbind_assigned_spis(&self) -> VgicResult

Releases every quiescent physical SPI fixed by the configuration.

The method attempts every binding so one backend failure does not leak unrelated host resources. The first failure is returned after the remaining releases have been attempted.

pub fn teardown_assigned_spis(&self) -> VgicResult

Retires and releases every assigned SPI while tearing down a stopped VM.

All bindings are attempted so one backend failure does not retain unrelated host resources. Failed bindings keep their controller claim and may be retried without deactivating an already retired delivery.

pub fn forward_physical_spi(&self, host_irq: HostIrqId) -> VgicResult

Forwards one acknowledged identity-backed host SPI.

pub fn inject( &self, vcpu: usize, intid: u32, trigger: InterruptTrigger, ) -> VgicResult

Injects one private or shared interrupt through canonical state.

Trait Implementations

impl Debug for VgicCore

fn fmt(&self, formatter: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl MessageInterruptController for VgicCore

fn id(&self) -> InterruptControllerId

Returns the controller identifier used by the VM device registry.

fn msi_endpoint( &self, its: ItsId, device: MsiDeviceId, event: MsiEventId, lpi: EndpointLpiId, ) -> IrqResult<MsiEndpoint>

Opens one planned message endpoint.

impl VirtualInterruptController for VgicCore

fn id(&self) -> InterruptControllerId

Returns the controller identifier used by the VM device registry.

fn wired_input( &self, input: ControllerInputId, trigger: InterruptTrigger, ) -> IrqResult<WiredIrqInput>

Opens one controller input using the planned trigger semantics.