Trait ComputeBackend

Source

pub trait ComputeBackend: Send + Sync {
Show 20 methods    // Required methods
    fn name(&self) -> &'static str;
    fn device_type(&self) -> DeviceType;
    fn preferred_order(&self) -> MemoryOrder;
    fn gemm<T: Scalar>(
        &self,
        desc: GemmDescriptor<'_, T>,
    ) -> Result<(), BackendError>;
    fn transpose<T: Scalar>(
        &self,
        desc: TransposeDescriptor<'_, T>,
    ) -> Result<(), BackendError>;

    // Provided methods
    fn is_available(&self) -> bool { ... }
    fn svd<T: Scalar>(
        &self,
        _desc: SvdDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn qr<T: Scalar>(
        &self,
        _desc: QrDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn lq<T: Scalar>(
        &self,
        _desc: LqDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn eigh<T: Scalar>(
        &self,
        _desc: EighDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn eig<T: Scalar>(
        &self,
        _desc: EigDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn solve<T: Scalar>(
        &self,
        _desc: SolveDescriptor<'_, T>,
    ) -> Result<(), BackendError> { ... }
    fn par_for_svd(&self, _m: usize, _n: usize) -> ExecPolicy { ... }
    fn par_for_qr(&self, _m: usize, _n: usize) -> ExecPolicy { ... }
    fn par_for_lq(&self, _m: usize, _n: usize) -> ExecPolicy { ... }
    fn par_for_eigh(&self, _n: usize) -> ExecPolicy { ... }
    fn par_for_eig(&self, _n: usize) -> ExecPolicy { ... }
    fn par_for_gemm(&self, _m: usize, _n: usize, _k: usize) -> ExecPolicy { ... }
    fn par_for_solve(&self, _n: usize, _nrhs: usize) -> ExecPolicy { ... }
    fn par_for_transpose(&self, _shape: &[usize]) -> ExecPolicy { ... }
}

Expand description

Pluggable compute backend trait

Required Methods§

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fn name(&self) -> &'static str

Backend name

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fn device_type(&self) -> DeviceType

Device type

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fn preferred_order(&self) -> MemoryOrder

Preferred memory order for this backend’s data layout.

Descriptor data (input/output slices) is expected in this order. The linalg layer converts tensors to this order before constructing descriptors.

This is an implementor-facing contract, not a user entry point: backend implementors must report the layout their kernels assume so the linalg / algorithm layers can normalize to it. End users never call it — the public Tensor surface hides memory layout entirely.

Source