#[repr(C)]pub enum hv_feature_reg_t {
Show 14 variants
ID_AA64DFR0_EL1 = 0,
ID_AA64DFR1_EL1 = 1,
ID_AA64ISAR0_EL1 = 2,
ID_AA64ISAR1_EL1 = 3,
ID_AA64MMFR0_EL1 = 4,
ID_AA64MMFR1_EL1 = 5,
ID_AA64MMFR2_EL1 = 6,
ID_AA64PFR0_EL1 = 7,
ID_AA64PFR1_EL1 = 8,
CTR_EL0 = 9,
CLIDR_EL1 = 10,
DCZID_EL0 = 11,
ID_AA64SMFR0_EL1 = 12,
ID_AA64ZFR0_EL1 = 13,
}Expand description
The type that defines feature registers.
Variants§
ID_AA64DFR0_EL1 = 0
The value that identifies debug feature register 0, EL1 (DFR0_EL1).
ID_AA64DFR1_EL1 = 1
The value that identifies debug feature register 1, EL1 (DFR1_EL1).
ID_AA64ISAR0_EL1 = 2
The value that identifies instruction set attribute register 0, EL1 (ISAR0_EL1).
ID_AA64ISAR1_EL1 = 3
The value that identifies instruction set attribute register 1, EL1 (ISAR_EL1).
ID_AA64MMFR0_EL1 = 4
The value that identifies memory model feature register 0, EL1(MMFR0_EL1).
ID_AA64MMFR1_EL1 = 5
The value that identifies memory model feature register 1, EL1 (MMFR1_EL1).
ID_AA64MMFR2_EL1 = 6
The value that identifies memory model feature register 2, EL1 (MMFR2_EL1).
ID_AA64PFR0_EL1 = 7
The value that identifies processor feature register 0, EL1 (PFR0_EL1).
ID_AA64PFR1_EL1 = 8
The value that identifies processor feature register 1, EL1 (PFR1_EL1).
CTR_EL0 = 9
The value that describes Cache Type Register, EL0.
CLIDR_EL1 = 10
The value that describes Cache Level ID Register, EL1.
DCZID_EL0 = 11
The values that describes Data Cache Zero ID Register, EL0.
ID_AA64SMFR0_EL1 = 12
The value that describes Scalable Matrix Extension (SME) Feature ID Register 0.
ID_AA64ZFR0_EL1 = 13
The value that describes Scalable Vector Extension instruction (SVE) Feature ID register 0.
Trait Implementations§
Source§impl Clone for hv_feature_reg_t
impl Clone for hv_feature_reg_t
Source§fn clone(&self) -> hv_feature_reg_t
fn clone(&self) -> hv_feature_reg_t
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more