Enum applevisor_sys::hv_simd_fp_reg_t
source · #[repr(C)]
pub enum hv_simd_fp_reg_t {
Show 32 variants
HV_SIMD_FP_REG_Q0,
HV_SIMD_FP_REG_Q1,
HV_SIMD_FP_REG_Q2,
HV_SIMD_FP_REG_Q3,
HV_SIMD_FP_REG_Q4,
HV_SIMD_FP_REG_Q5,
HV_SIMD_FP_REG_Q6,
HV_SIMD_FP_REG_Q7,
HV_SIMD_FP_REG_Q8,
HV_SIMD_FP_REG_Q9,
HV_SIMD_FP_REG_Q10,
HV_SIMD_FP_REG_Q11,
HV_SIMD_FP_REG_Q12,
HV_SIMD_FP_REG_Q13,
HV_SIMD_FP_REG_Q14,
HV_SIMD_FP_REG_Q15,
HV_SIMD_FP_REG_Q16,
HV_SIMD_FP_REG_Q17,
HV_SIMD_FP_REG_Q18,
HV_SIMD_FP_REG_Q19,
HV_SIMD_FP_REG_Q20,
HV_SIMD_FP_REG_Q21,
HV_SIMD_FP_REG_Q22,
HV_SIMD_FP_REG_Q23,
HV_SIMD_FP_REG_Q24,
HV_SIMD_FP_REG_Q25,
HV_SIMD_FP_REG_Q26,
HV_SIMD_FP_REG_Q27,
HV_SIMD_FP_REG_Q28,
HV_SIMD_FP_REG_Q29,
HV_SIMD_FP_REG_Q30,
HV_SIMD_FP_REG_Q31,
}Expand description
The type that defines SIMD and floating-point registers.
Variants
HV_SIMD_FP_REG_Q0
The value representing SIMD register Q0.
HV_SIMD_FP_REG_Q1
The value representing SIMD register Q1.
HV_SIMD_FP_REG_Q2
The value representing SIMD register Q2.
HV_SIMD_FP_REG_Q3
The value representing SIMD register Q3.
HV_SIMD_FP_REG_Q4
The value representing SIMD register Q4.
HV_SIMD_FP_REG_Q5
The value representing SIMD register Q5.
HV_SIMD_FP_REG_Q6
The value representing SIMD register Q6.
HV_SIMD_FP_REG_Q7
The value representing SIMD register Q7.
HV_SIMD_FP_REG_Q8
The value representing SIMD register Q8.
HV_SIMD_FP_REG_Q9
The value representing SIMD register Q9.
HV_SIMD_FP_REG_Q10
The value representing SIMD register Q10.
HV_SIMD_FP_REG_Q11
The value representing SIMD register Q11.
HV_SIMD_FP_REG_Q12
The value representing SIMD register Q12.
HV_SIMD_FP_REG_Q13
The value representing SIMD register Q13.
HV_SIMD_FP_REG_Q14
The value representing SIMD register Q14.
HV_SIMD_FP_REG_Q15
The value representing SIMD register Q15.
HV_SIMD_FP_REG_Q16
The value representing SIMD register Q16.
HV_SIMD_FP_REG_Q17
The value representing SIMD register Q17.
HV_SIMD_FP_REG_Q18
The value representing SIMD register Q18.
HV_SIMD_FP_REG_Q19
The value representing SIMD register Q19.
HV_SIMD_FP_REG_Q20
The value representing SIMD register Q20.
HV_SIMD_FP_REG_Q21
The value representing SIMD register Q21.
HV_SIMD_FP_REG_Q22
The value representing SIMD register Q22.
HV_SIMD_FP_REG_Q23
The value representing SIMD register Q23.
HV_SIMD_FP_REG_Q24
The value representing SIMD register Q24.
HV_SIMD_FP_REG_Q25
The value representing SIMD register Q25.
HV_SIMD_FP_REG_Q26
The value representing SIMD register Q26.
HV_SIMD_FP_REG_Q27
The value representing SIMD register Q27.
HV_SIMD_FP_REG_Q28
The value representing SIMD register Q28.
HV_SIMD_FP_REG_Q29
The value representing SIMD register Q29.
HV_SIMD_FP_REG_Q30
The value representing SIMD register Q30.
HV_SIMD_FP_REG_Q31
The value representing SIMD register Q31.
Trait Implementations
sourceimpl Clone for hv_simd_fp_reg_t
impl Clone for hv_simd_fp_reg_t
sourcefn clone(&self) -> hv_simd_fp_reg_t
fn clone(&self) -> hv_simd_fp_reg_t
1.0.0 · sourcefn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moresourceimpl Debug for hv_simd_fp_reg_t
impl Debug for hv_simd_fp_reg_t
sourceimpl Hash for hv_simd_fp_reg_t
impl Hash for hv_simd_fp_reg_t
sourceimpl Ord for hv_simd_fp_reg_t
impl Ord for hv_simd_fp_reg_t
sourcefn cmp(&self, other: &hv_simd_fp_reg_t) -> Ordering
fn cmp(&self, other: &hv_simd_fp_reg_t) -> Ordering
1.21.0 · sourcefn max(self, other: Self) -> Selfwhere
Self: Sized,
fn max(self, other: Self) -> Selfwhere
Self: Sized,
1.21.0 · sourcefn min(self, other: Self) -> Selfwhere
Self: Sized,
fn min(self, other: Self) -> Selfwhere
Self: Sized,
1.50.0 · sourcefn clamp(self, min: Self, max: Self) -> Selfwhere
Self: Sized + PartialOrd<Self>,
fn clamp(self, min: Self, max: Self) -> Selfwhere
Self: Sized + PartialOrd<Self>,
sourceimpl PartialEq<hv_simd_fp_reg_t> for hv_simd_fp_reg_t
impl PartialEq<hv_simd_fp_reg_t> for hv_simd_fp_reg_t
sourcefn eq(&self, other: &hv_simd_fp_reg_t) -> bool
fn eq(&self, other: &hv_simd_fp_reg_t) -> bool
sourceimpl PartialOrd<hv_simd_fp_reg_t> for hv_simd_fp_reg_t
impl PartialOrd<hv_simd_fp_reg_t> for hv_simd_fp_reg_t
sourcefn partial_cmp(&self, other: &hv_simd_fp_reg_t) -> Option<Ordering>
fn partial_cmp(&self, other: &hv_simd_fp_reg_t) -> Option<Ordering>
1.0.0 · sourcefn le(&self, other: &Rhs) -> bool
fn le(&self, other: &Rhs) -> bool
self and other) and is used by the <=
operator. Read more