[−][src]Struct ambiq_apollo3p_pac::mspi0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctrl: CTRL,
    pub cfg: CFG,
    pub addr: ADDR,
    pub instr: INSTR,
    pub txfifo: TXFIFO,
    pub rxfifo: RXFIFO,
    pub txentries: TXENTRIES,
    pub rxentries: RXENTRIES,
    pub threshold: THRESHOLD,
    pub mspicfg: MSPICFG,
    pub mspiddr: MSPIDDR,
    pub padcfg: PADCFG,
    pub padouten: PADOUTEN,
    pub padoveren: PADOVEREN,
    pub padover: PADOVER,
    pub flash: FLASH,
    pub xipinstr: XIPINSTR,
    pub scrambling: SCRAMBLING,
    pub inten: INTEN,
    pub intstat: INTSTAT,
    pub intclr: INTCLR,
    pub intset: INTSET,
    pub dmacfg: DMACFG,
    pub dmastat: DMASTAT,
    pub dmatargaddr: DMATARGADDR,
    pub dmadevaddr: DMADEVADDR,
    pub dmatotcount: DMATOTCOUNT,
    pub dmabcount: DMABCOUNT,
    pub dmathresh: DMATHRESH,
    pub dmaboundary: DMABOUNDARY,
    pub cqcfg: CQCFG,
    pub cqaddr: CQADDR,
    pub cqstat: CQSTAT,
    pub cqflags: CQFLAGS,
    pub cqsetclear: CQSETCLEAR,
    pub cqpause: CQPAUSE,
    pub cqcuridx: CQCURIDX,
    pub cqendidx: CQENDIDX,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - MSPI PIO Transfer Control/Status

cfg: CFG

0x04 - MSPI Transfer Configuration

addr: ADDR

0x08 - MSPI Transfer Address

instr: INSTR

0x0c - MSPI Transfer Instruction

txfifo: TXFIFO

0x10 - TX Data FIFO

rxfifo: RXFIFO

0x14 - RX Data FIFO

txentries: TXENTRIES

0x18 - TX FIFO Entries

rxentries: RXENTRIES

0x1c - RX FIFO Entries

threshold: THRESHOLD

0x20 - TX/RX FIFO Threshold Levels

mspicfg: MSPICFG

0x100 - MSPI Module Configuration

mspiddr: MSPIDDR

0x104 - MSPI Module DDR Configuration Bits

padcfg: PADCFG

0x110 - MSPI Output Pad Configuration

padouten: PADOUTEN

0x114 - MSPI Output Enable Pad Configuration

padoveren: PADOVEREN

0x118 - MSPI Output Pad Override

padover: PADOVER

0x11c - MSPI Output Pad Override Value

flash: FLASH

0x120 - Configuration for XIP/DMA support of SPI flash modules.

xipinstr: XIPINSTR

0x124 - Configuration for XIP/DMA support of SPI flash modules.

scrambling: SCRAMBLING

0x128 - External Flash Scrambling Controls

inten: INTEN

0x200 - MSPI Master Interrupts: Enable

intstat: INTSTAT

0x204 - MSPI Master Interrupts: Status

intclr: INTCLR

0x208 - MSPI Master Interrupts: Clear

intset: INTSET

0x20c - MSPI Master Interrupts: Set

dmacfg: DMACFG

0x250 - DMA Configuration

dmastat: DMASTAT

0x254 - DMA Status

dmatargaddr: DMATARGADDR

0x258 - DMA Target Address

dmadevaddr: DMADEVADDR

0x25c - DMA Device Address

dmatotcount: DMATOTCOUNT

0x260 - DMA Total Transfer Count

dmabcount: DMABCOUNT

0x264 - DMA BYTE Transfer Count

dmathresh: DMATHRESH

0x268 - DMA Transmit Trigger Threshold

dmaboundary: DMABOUNDARY

0x26c - DMA Transfer Boundary

cqcfg: CQCFG

0x2a0 - Command Queue Configuration

cqaddr: CQADDR

0x2a8 - CQ Target Read Address

cqstat: CQSTAT

0x2ac - Command Queue Status

cqflags: CQFLAGS

0x2b0 - Command Queue Flags

cqsetclear: CQSETCLEAR

0x2b4 - Command Queue Flag Set/Clear

cqpause: CQPAUSE

0x2b8 - Command Queue Pause Mask

cqcuridx: CQCURIDX

0x2c0 - Command Queue Current Index

cqendidx: CQENDIDX

0x2c4 - Command Queue End Index

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