Module ambiq_apollo3p_pac::mspi0

Multi-bit SPI Master

Modules

addr	MSPI Transfer Address
cfg	MSPI Transfer Configuration
cqaddr	CQ Target Read Address
cqcfg	Command Queue Configuration
cqcuridx	Command Queue Current Index
cqendidx	Command Queue End Index
cqflags	Command Queue Flags
cqpause	Command Queue Pause Mask
cqsetclear	Command Queue Flag Set/Clear
cqstat	Command Queue Status
ctrl	MSPI PIO Transfer Control/Status
dmabcount	DMA BYTE Transfer Count
dmaboundary	DMA Transfer Boundary
dmacfg	DMA Configuration
dmadevaddr	DMA Device Address
dmastat	DMA Status
dmatargaddr	DMA Target Address
dmathresh	DMA Transmit Trigger Threshold
dmatotcount	DMA Total Transfer Count
flash	Configuration for XIP/DMA support of SPI flash modules.
instr	MSPI Transfer Instruction
intclr	MSPI Master Interrupts: Clear
inten	MSPI Master Interrupts: Enable
intset	MSPI Master Interrupts: Set
intstat	MSPI Master Interrupts: Status
mspicfg	MSPI Module Configuration
mspiddr	MSPI Module DDR Configuration Bits
padcfg	MSPI Output Pad Configuration
padouten	MSPI Output Enable Pad Configuration
padover	MSPI Output Pad Override Value
padoveren	MSPI Output Pad Override
rxentries	RX FIFO Entries
rxfifo	RX Data FIFO
scrambling	External Flash Scrambling Controls
threshold	TX/RX FIFO Threshold Levels
txentries	TX FIFO Entries
txfifo	TX Data FIFO
xipinstr	Configuration for XIP/DMA support of SPI flash modules.

Structs

RegisterBlock

Register block

Type Definitions

ADDR	MSPI Transfer Address
CFG	MSPI Transfer Configuration
CQADDR	CQ Target Read Address
CQCFG	Command Queue Configuration
CQCURIDX	Command Queue Current Index
CQENDIDX	Command Queue End Index
CQFLAGS	Command Queue Flags
CQPAUSE	Command Queue Pause Mask
CQSETCLEAR	Command Queue Flag Set/Clear
CQSTAT	Command Queue Status
CTRL	MSPI PIO Transfer Control/Status
DMABCOUNT	DMA BYTE Transfer Count
DMABOUNDARY	DMA Transfer Boundary
DMACFG	DMA Configuration
DMADEVADDR	DMA Device Address
DMASTAT	DMA Status
DMATARGADDR	DMA Target Address
DMATHRESH	DMA Transmit Trigger Threshold
DMATOTCOUNT	DMA Total Transfer Count
FLASH	Configuration for XIP/DMA support of SPI flash modules.
INSTR	MSPI Transfer Instruction
INTCLR	MSPI Master Interrupts: Clear
INTEN	MSPI Master Interrupts: Enable
INTSET	MSPI Master Interrupts: Set
INTSTAT	MSPI Master Interrupts: Status
MSPICFG	MSPI Module Configuration
MSPIDDR	MSPI Module DDR Configuration Bits
PADCFG	MSPI Output Pad Configuration
PADOUTEN	MSPI Output Enable Pad Configuration
PADOVER	MSPI Output Pad Override Value
PADOVEREN	MSPI Output Pad Override
RXENTRIES	RX FIFO Entries
RXFIFO	RX Data FIFO
SCRAMBLING	External Flash Scrambling Controls
THRESHOLD	TX/RX FIFO Threshold Levels
TXENTRIES	TX FIFO Entries
TXFIFO	TX Data FIFO
XIPINSTR	Configuration for XIP/DMA support of SPI flash modules.