Struct W 

pub struct W { /* private fields */ }

Value to write to the register

Implementations

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn flash1_slm_enable(&mut self) -> _FLASH1_SLM_ENABLEW<'_>

Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.

pub fn flash1_slm_disable(&mut self) -> _FLASH1_SLM_DISABLEW<'_>

Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it).

pub fn flash1_slm_status(&mut self) -> _FLASH1_SLM_STATUSW<'_>

Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode.

pub fn flash0_slm_enable(&mut self) -> _FLASH0_SLM_ENABLEW<'_>

Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.

pub fn flash0_slm_disable(&mut self) -> _FLASH0_SLM_DISABLEW<'_>

Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it).

pub fn flash0_slm_status(&mut self) -> _FLASH0_SLM_STATUSW<'_>

Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode.

pub fn cache_ready(&mut self) -> _CACHE_READYW<'_>

Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)

pub fn reset_stat(&mut self) -> _RESET_STATW<'_>

Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.

pub fn invalidate(&mut self) -> _INVALIDATEW<'_>

Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents.