Struct R 

pub struct R { /* private fields */ }

Value read from the register

Implementations

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn flash1_slm_enable(&self) -> FLASH1_SLM_ENABLER

Bit 10 - Enable Flash Sleep Mode. Write to 1 to put flash 1 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.

pub fn flash1_slm_disable(&self) -> FLASH1_SLM_DISABLER

Bit 9 - Disable Flash Sleep Mode. Write 1 to wake flash1 from sleep mode (reading the array will also automatically wake it).

pub fn flash1_slm_status(&self) -> FLASH1_SLM_STATUSR

Bit 8 - Flash Sleep Mode Status. 1 indicates that flash1 is in sleep mode, 0 indicates flash1 is in normal mode.

pub fn flash0_slm_enable(&self) -> FLASH0_SLM_ENABLER

Bit 6 - Enable Flash Sleep Mode. Write to 1 to put flash 0 into sleep mode. NOTE: there is a 5us latency after waking flash until the first access will be returned.

pub fn flash0_slm_disable(&self) -> FLASH0_SLM_DISABLER

Bit 5 - Disable Flash Sleep Mode. Write 1 to wake flash0 from sleep mode (reading the array will also automatically wake it).

pub fn flash0_slm_status(&self) -> FLASH0_SLM_STATUSR

Bit 4 - Flash Sleep Mode Status. 1 indicates that flash0 is in sleep mode, 0 indicates flash0 is in normal mode.

pub fn cache_ready(&self) -> CACHE_READYR

Bit 2 - Cache Ready Status (enabled and not processing an invalidate operation)

pub fn reset_stat(&self) -> RESET_STATR

Bit 1 - Reset Cache Statistics. When written to a 1, the cache monitor counters will be cleared. The monitor counters can be reset only when the CACHECFG.ENABLE_MONITOR bit is set.

pub fn invalidate(&self) -> INVALIDATER

Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents.