Struct ambiq_apollo3_pac::mspi::inten::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn screrr(&self) -> SCRERRR

Bit 12 - Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

pub fn cqerr(&self) -> CQERRR

Bit 11 - Command Queue Error Interrupt

pub fn cqpaused(&self) -> CQPAUSEDR

Bit 10 - Command Queue is Paused.

pub fn cqupd(&self) -> CQUPDR

Bit 9 - Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

pub fn cqcmp(&self) -> CQCMPR

Bit 8 - Command Queue Complete Interrupt

pub fn derr(&self) -> DERRR

Bit 7 - DMA Error Interrupt

pub fn dcmp(&self) -> DCMPR

Bit 6 - DMA Complete Interrupt

pub fn rxf(&self) -> RXFR

Bit 5 - Receive FIFO full

pub fn rxo(&self) -> RXOR

Bit 4 - Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

pub fn rxu(&self) -> RXUR

Bit 3 - Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

pub fn txo(&self) -> TXOR

Bit 2 - Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

pub fn txe(&self) -> TXER

Bit 1 - Transmit FIFO empty.

pub fn cmdcmp(&self) -> CMDCMPR

Bit 0 - Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signalled simultaneously