[−][src]Module ambiq_apollo3_pac::mspi
Multibit SPI Master
Modules
| addr | MSPI Transfer Address Register |
| cfg | MSPI Transfer Configuration Register |
| cqaddr | CQ Target Read Address Register |
| cqcfg | Command Queue Configuration Register |
| cqcuridx | Command Queue Current Index |
| cqendidx | Command Queue End Index |
| cqflags | Command Queue Flag Register |
| cqpause | Command Queue Pause Mask Register |
| cqsetclear | Command Queue Flag Set/Clear Register |
| cqstat | Command Queue Status Register |
| ctrl | MSPI PIO Transfer Control/Status Register |
| dmabcount | DMA BYTE Transfer Count |
| dmacfg | DMA Configuration Register |
| dmadevaddr | DMA Device Address Register |
| dmastat | DMA Status Register |
| dmatargaddr | DMA Target Address Register |
| dmathresh | DMA Transmit Trigger Threshhold |
| dmatotcount | DMA Total Transfer Count |
| flash | Configuration for XIP/DMA support of SPI flash modules. |
| instr | MSPI Transfer Instruction |
| intclr | MSPI Master Interrupts: Clear |
| inten | MSPI Master Interrupts: Enable |
| intset | MSPI Master Interrupts: Set |
| intstat | MSPI Master Interrupts: Status |
| mspicfg | MSPI Module Configuration |
| padcfg | MSPI Output Pad Configuration |
| padouten | MSPI Output Enable Pad Configuration |
| rxentries | RX FIFO Entries |
| rxfifo | RX Data FIFO |
| scrambling | External Flash Scrambling Controls |
| threshold | TX/RX FIFO Threshhold Levels |
| txentries | TX FIFO Entries |
| txfifo | TX Data FIFO |
Structs
| ADDR | MSPI Transfer Address Register |
| CFG | MSPI Transfer Configuration Register |
| CQADDR | CQ Target Read Address Register |
| CQCFG | Command Queue Configuration Register |
| CQCURIDX | Command Queue Current Index |
| CQENDIDX | Command Queue End Index |
| CQFLAGS | Command Queue Flag Register |
| CQPAUSE | Command Queue Pause Mask Register |
| CQSETCLEAR | Command Queue Flag Set/Clear Register |
| CQSTAT | Command Queue Status Register |
| CTRL | MSPI PIO Transfer Control/Status Register |
| DMABCOUNT | DMA BYTE Transfer Count |
| DMACFG | DMA Configuration Register |
| DMADEVADDR | DMA Device Address Register |
| DMASTAT | DMA Status Register |
| DMATARGADDR | DMA Target Address Register |
| DMATHRESH | DMA Transmit Trigger Threshhold |
| DMATOTCOUNT | DMA Total Transfer Count |
| FLASH | Configuration for XIP/DMA support of SPI flash modules. |
| INSTR | MSPI Transfer Instruction |
| INTCLR | MSPI Master Interrupts: Clear |
| INTEN | MSPI Master Interrupts: Enable |
| INTSET | MSPI Master Interrupts: Set |
| INTSTAT | MSPI Master Interrupts: Status |
| MSPICFG | MSPI Module Configuration |
| PADCFG | MSPI Output Pad Configuration |
| PADOUTEN | MSPI Output Enable Pad Configuration |
| RXENTRIES | RX FIFO Entries |
| RXFIFO | RX Data FIFO |
| RegisterBlock | Register block |
| SCRAMBLING | External Flash Scrambling Controls |
| THRESHOLD | TX/RX FIFO Threshhold Levels |
| TXENTRIES | TX FIFO Entries |
| TXFIFO | TX Data FIFO |