[−][src]Struct ambiq_apollo3_pac::iom0::RegisterBlock

#[repr(C)]

pub struct RegisterBlock {
    pub fifo: FIFO,
    pub fifoptr: FIFOPTR,
    pub fifothr: FIFOTHR,
    pub fifopop: FIFOPOP,
    pub fifopush: FIFOPUSH,
    pub fifoctrl: FIFOCTRL,
    pub fifoloc: FIFOLOC,
    pub inten: INTEN,
    pub intstat: INTSTAT,
    pub intclr: INTCLR,
    pub intset: INTSET,
    pub clkcfg: CLKCFG,
    pub submodctrl: SUBMODCTRL,
    pub cmd: CMD,
    pub dcx: DCX,
    pub offsethi: OFFSETHI,
    pub cmdstat: CMDSTAT,
    pub dmatrigen: DMATRIGEN,
    pub dmatrigstat: DMATRIGSTAT,
    pub dmacfg: DMACFG,
    pub dmatotcount: DMATOTCOUNT,
    pub dmatargaddr: DMATARGADDR,
    pub dmastat: DMASTAT,
    pub cqcfg: CQCFG,
    pub cqaddr: CQADDR,
    pub cqstat: CQSTAT,
    pub cqflags: CQFLAGS,
    pub cqsetclear: CQSETCLEAR,
    pub cqpauseen: CQPAUSEEN,
    pub cqcuridx: CQCURIDX,
    pub cqendidx: CQENDIDX,
    pub status: STATUS,
    pub mspicfg: MSPICFG,
    pub mi2ccfg: MI2CCFG,
    pub devcfg: DEVCFG,
    pub iomdbg: IOMDBG,
    // some fields omitted
}

Register block

Fields

fifo: FIFO

0x00 - FIFO Access Port

fifoptr: FIFOPTR

0x100 - FIFO size and remaining slots open values

fifothr: FIFOTHR

0x104 - FIFO Threshold Configuration

fifopop: FIFOPOP

0x108 - FIFO POP register

fifopush: FIFOPUSH

0x10c - FIFO PUSH register

fifoctrl: FIFOCTRL

0x110 - FIFO Control Register

fifoloc: FIFOLOC

0x114 - FIFO Pointers

inten: INTEN

0x200 - IO Master Interrupts: Enable

intstat: INTSTAT

0x204 - IO Master Interrupts: Status

intclr: INTCLR

0x208 - IO Master Interrupts: Clear

intset: INTSET

0x20c - IO Master Interrupts: Set

clkcfg: CLKCFG

0x210 - I/O Clock Configuration

submodctrl: SUBMODCTRL

0x214 - Submodule control

cmd: CMD

0x218 - Command and offset Register

dcx: DCX

0x21c - DCX Control Register

offsethi: OFFSETHI

0x220 - High order 2 bytes of 3 byte offset for IO transaction

cmdstat: CMDSTAT

0x224 - Command status

dmatrigen: DMATRIGEN

0x240 - DMA Trigger Enable Register

dmatrigstat: DMATRIGSTAT

0x244 - DMA Trigger Status Register

dmacfg: DMACFG

0x280 - DMA Configuration Register

dmatotcount: DMATOTCOUNT

0x288 - DMA Total Transfer Count

dmatargaddr: DMATARGADDR

0x28c - DMA Target Address Register

dmastat: DMASTAT

0x290 - DMA Status Register

cqcfg: CQCFG

0x294 - Command Queue Configuration Register

cqaddr: CQADDR

0x298 - CQ Target Read Address Register

cqstat: CQSTAT

0x29c - Command Queue Status Register

cqflags: CQFLAGS

0x2a0 - Command Queue Flag Register

cqsetclear: CQSETCLEAR

0x2a4 - Command Queue Flag Set/Clear Register

cqpauseen: CQPAUSEEN

0x2a8 - Command Queue Pause Enable Register

cqcuridx: CQCURIDX

0x2ac - IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue

cqendidx: CQENDIDX

0x2b0 - IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue

status: STATUS

0x2b4 - IOM Module Status Register

mspicfg: MSPICFG

0x300 - SPI module master configuration

mi2ccfg: MI2CCFG

0x400 - I2C Master configuration

devcfg: DEVCFG

0x404 - I2C Device Configuration register

iomdbg: IOMDBG

0x410 - IOM Debug Register

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