[−][src]Module ambiq_apollo3_pac::iom0
IO Peripheral Master
Modules
clkcfg | I/O Clock Configuration |
cmd | Command and offset Register |
cmdstat | Command status |
cqaddr | CQ Target Read Address Register |
cqcfg | Command Queue Configuration Register |
cqcuridx | IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
cqendidx | IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
cqflags | Command Queue Flag Register |
cqpauseen | Command Queue Pause Enable Register |
cqsetclear | Command Queue Flag Set/Clear Register |
cqstat | Command Queue Status Register |
dcx | DCX Control Register |
devcfg | I2C Device Configuration register |
dmacfg | DMA Configuration Register |
dmastat | DMA Status Register |
dmatargaddr | DMA Target Address Register |
dmatotcount | DMA Total Transfer Count |
dmatrigen | DMA Trigger Enable Register |
dmatrigstat | DMA Trigger Status Register |
fifo | FIFO Access Port |
fifoctrl | FIFO Control Register |
fifoloc | FIFO Pointers |
fifopop | FIFO POP register |
fifoptr | FIFO size and remaining slots open values |
fifopush | FIFO PUSH register |
fifothr | FIFO Threshold Configuration |
intclr | IO Master Interrupts: Clear |
inten | IO Master Interrupts: Enable |
intset | IO Master Interrupts: Set |
intstat | IO Master Interrupts: Status |
iomdbg | IOM Debug Register |
mi2ccfg | I2C Master configuration |
mspicfg | SPI module master configuration |
offsethi | High order 2 bytes of 3 byte offset for IO transaction |
status | IOM Module Status Register |
submodctrl | Submodule control |
Structs
CLKCFG | I/O Clock Configuration |
CMD | Command and offset Register |
CMDSTAT | Command status |
CQADDR | CQ Target Read Address Register |
CQCFG | Command Queue Configuration Register |
CQCURIDX | IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
CQENDIDX | IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
CQFLAGS | Command Queue Flag Register |
CQPAUSEEN | Command Queue Pause Enable Register |
CQSETCLEAR | Command Queue Flag Set/Clear Register |
CQSTAT | Command Queue Status Register |
DCX | DCX Control Register |
DEVCFG | I2C Device Configuration register |
DMACFG | DMA Configuration Register |
DMASTAT | DMA Status Register |
DMATARGADDR | DMA Target Address Register |
DMATOTCOUNT | DMA Total Transfer Count |
DMATRIGEN | DMA Trigger Enable Register |
DMATRIGSTAT | DMA Trigger Status Register |
FIFO | FIFO Access Port |
FIFOCTRL | FIFO Control Register |
FIFOLOC | FIFO Pointers |
FIFOPOP | FIFO POP register |
FIFOPTR | FIFO size and remaining slots open values |
FIFOPUSH | FIFO PUSH register |
FIFOTHR | FIFO Threshold Configuration |
INTCLR | IO Master Interrupts: Clear |
INTEN | IO Master Interrupts: Enable |
INTSET | IO Master Interrupts: Set |
INTSTAT | IO Master Interrupts: Status |
IOMDBG | IOM Debug Register |
MI2CCFG | I2C Master configuration |
MSPICFG | SPI module master configuration |
OFFSETHI | High order 2 bytes of 3 byte offset for IO transaction |
RegisterBlock | Register block |
STATUS | IOM Module Status Register |
SUBMODCTRL | Submodule control |