Struct ambiq_apollo3_pac::iom0::intset::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn cqerr(&mut self) -> _CQERRW

Bit 14 - Error during command queue operations

pub fn cqupd(&mut self) -> _CQUPDW

Bit 13 - CQ write operation performed a register write with the register address bit 0 set to 1. The low address bits in the CQ address fields are unused and bit 0 can be used to trigger an interrupt to indicate when this register write is performed by the CQ operation.

pub fn cqpaused(&mut self) -> _CQPAUSEDW

Bit 12 - Command queue is paused due to an active event enabled in the PAUSEEN register. The interrupt is posted when the event is enabled within the PAUSEEN register, the mask is active in the CQIRQMASK field and the event occurs.

pub fn derr(&mut self) -> _DERRW

Bit 11 - DMA Error encountered during the processing of the DMA command. The DMA error could occur when the memory access specified in the DMA operation is not available or incorrectly specified.

pub fn dcmp(&mut self) -> _DCMPW

Bit 10 - DMA Complete. Processing of the DMA operation has completed and the DMA submodule is returned into the idle state

pub fn arb(&mut self) -> _ARBW

Bit 9 - Arbitration loss interrupt. Asserted when arbitration is enabled and has been lost to another master on the bus.

pub fn stop(&mut self) -> _STOPW

Bit 8 - STOP command interrupt. Asserted when another master on the bus has signaled a STOP command.

pub fn start(&mut self) -> _STARTW

Bit 7 - START command interrupt. Asserted when another master on the bus has signaled a START command.

pub fn icmd(&mut self) -> _ICMDW

Bit 6 - illegal command interrupt. Asserted when a command is written when an active command is in progress.

pub fn iacc(&mut self) -> _IACCW

Bit 5 - illegal FIFO access interrupt. Asserted when there is a overflow or underflow event

pub fn nak(&mut self) -> _NAKW

Bit 4 - I2C NAK interrupt. Asserted when an unexpected NAK has been received on the I2C bus.

pub fn fovfl(&mut self) -> _FOVFLW

Bit 3 - Write FIFO Overflow interrupt. This occurs when software tries to write to a full fifo. The current operation does not stop.

pub fn fundfl(&mut self) -> _FUNDFLW

Bit 2 - Read FIFO Underflow interrupt. This occurs when software tries to pop from an empty fifo.

pub fn thr(&mut self) -> _THRW

Bit 1 - FIFO Threshold interrupt. For write operations, asserted when the number of free bytes in the write FIFO equals or exceeds the WTHR field. For read operations, asserted when the number of valid bytes in the read FIFO equals of exceeds the value set in the RTHR field.

pub fn cmdcmp(&mut self) -> _CMDCMPW

Bit 0 - Command Complete interrupt. Asserted when the current operation has completed. For repeated commands, this will only be asserted when the final repeated command is completed.