Enum ambiq_apollo3_pac::iom0::clkcfg::FSELR

pub enum FSELR {
    MIN_PWR,
    HFRC,
    HFRC_DIV2,
    HFRC_DIV4,
    HFRC_DIV8,
    HFRC_DIV16,
    HFRC_DIV32,
    HFRC_DIV64,
}

Possible values of the field FSEL

Variants

MIN_PWR

Selects the minimum power clock. This setting should be used whenever the IOM is not active. value.

HFRC

Selects the HFRC as the input clock. value.

HFRC_DIV2

Selects the HFRC / 2 as the input clock. value.

HFRC_DIV4

Selects the HFRC / 4 as the input clock. value.

HFRC_DIV8

Selects the HFRC / 8 as the input clock. value.

HFRC_DIV16

Selects the HFRC / 16 as the input clock. value.

HFRC_DIV32

Selects the HFRC / 32 as the input clock. value.

HFRC_DIV64

Selects the HFRC / 64 as the input clock. value.

Methods

impl FSELR

pub fn bits(&self) -> u8

Value of the field as raw bits

pub fn is_min_pwr(&self) -> bool

Checks if the value of the field is MIN_PWR

pub fn is_hfrc(&self) -> bool

Checks if the value of the field is HFRC

pub fn is_hfrc_div2(&self) -> bool

Checks if the value of the field is HFRC_DIV2

pub fn is_hfrc_div4(&self) -> bool

Checks if the value of the field is HFRC_DIV4

pub fn is_hfrc_div8(&self) -> bool

Checks if the value of the field is HFRC_DIV8

pub fn is_hfrc_div16(&self) -> bool

Checks if the value of the field is HFRC_DIV16

pub fn is_hfrc_div32(&self) -> bool

Checks if the value of the field is HFRC_DIV32

pub fn is_hfrc_div64(&self) -> bool

Checks if the value of the field is HFRC_DIV64

Trait Implementations

impl Copy for FSELR

impl Debug for FSELR

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl PartialEq<FSELR> for FSELR

fn eq(&self, other: &FSELR) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Clone for FSELR

fn clone(&self) -> FSELR

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.