[−][src]Struct ambiq_apollo2_pac::mcuctrl::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub chip_info: CHIP_INFO,
    pub chipid0: CHIPID0,
    pub chipid1: CHIPID1,
    pub chiprev: CHIPREV,
    pub vendorid: VENDORID,
    pub debugger: DEBUGGER,
    pub buck: BUCK,
    pub buck3: BUCK3,
    pub ldoreg1: LDOREG1,
    pub ldoreg3: LDOREG3,
    pub bodporctrl: BODPORCTRL,
    pub adcpwrdly: ADCPWRDLY,
    pub adccal: ADCCAL,
    pub adcbattload: ADCBATTLOAD,
    pub bucktrim: BUCKTRIM,
    pub xtalgenctrl: XTALGENCTRL,
    pub bootloaderlow: BOOTLOADERLOW,
    pub shadowvalid: SHADOWVALID,
    pub icodefaultaddr: ICODEFAULTADDR,
    pub dcodefaultaddr: DCODEFAULTADDR,
    pub sysfaultaddr: SYSFAULTADDR,
    pub faultstatus: FAULTSTATUS,
    pub faultcaptureen: FAULTCAPTUREEN,
    pub dbgr1: DBGR1,
    pub dbgr2: DBGR2,
    pub pmuenable: PMUENABLE,
    pub tpiuctrl: TPIUCTRL,
    // some fields omitted
}

Register block

Fields

chip_info: CHIP_INFO

0x00 - Chip Information Register

chipid0: CHIPID0

0x04 - Unique Chip ID 0

chipid1: CHIPID1

0x08 - Unique Chip ID 1

chiprev: CHIPREV

0x0c - Chip Revision

vendorid: VENDORID

0x10 - Unique Vendor ID

debugger: DEBUGGER

0x14 - Debugger Access Control

buck: BUCK

0x60 - Analog Buck Control

buck3: BUCK3

0x68 - Buck control reg 3

ldoreg1: LDOREG1

0x80 - Analog LDO Reg 1

ldoreg3: LDOREG3

0x88 - LDO Control Register 3

bodporctrl: BODPORCTRL

0x100 - BOD and PDR control Register

adcpwrdly: ADCPWRDLY

0x104 - ADC Power Up Delay Control

adccal: ADCCAL

0x10c - ADC Calibration Control

adcbattload: ADCBATTLOAD

0x110 - ADC Battery Load Enable

bucktrim: BUCKTRIM

0x114 - Trim settings for Core and Mem buck modules

xtalgenctrl: XTALGENCTRL

0x124 - XTAL Oscillator General Control

bootloaderlow: BOOTLOADERLOW

0x1a0 - Determines whether the bootloader code is visible at address 0x00000000

shadowvalid: SHADOWVALID

0x1a4 - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

icodefaultaddr: ICODEFAULTADDR

0x1c0 - ICODE bus address which was present when a bus fault occurred.

dcodefaultaddr: DCODEFAULTADDR

0x1c4 - DCODE bus address which was present when a bus fault occurred.

sysfaultaddr: SYSFAULTADDR

0x1c8 - System bus address which was present when a bus fault occurred.

faultstatus: FAULTSTATUS

0x1cc - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

faultcaptureen: FAULTCAPTUREEN

0x1d0 - Enable the fault capture registers

dbgr1: DBGR1

0x200 - Read-only debug register 1

dbgr2: DBGR2

0x204 - Read-only debug register 2

pmuenable: PMUENABLE

0x220 - Control bit to enable/disable the PMU

tpiuctrl: TPIUCTRL

0x250 - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

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