[−][src]Module ambiq_apollo2_pac::mcuctrl
MCU Miscellaneous Control Logic
Modules
| adcbattload | ADC Battery Load Enable |
| adccal | ADC Calibration Control |
| adcpwrdly | ADC Power Up Delay Control |
| bodporctrl | BOD and PDR control Register |
| bootloaderlow | Determines whether the bootloader code is visible at address 0x00000000 |
| buck | Analog Buck Control |
| buck3 | Buck control reg 3 |
| bucktrim | Trim settings for Core and Mem buck modules |
| chip_info | Chip Information Register |
| chipid0 | Unique Chip ID 0 |
| chipid1 | Unique Chip ID 1 |
| chiprev | Chip Revision |
| dbgr1 | Read-only debug register 1 |
| dbgr2 | Read-only debug register 2 |
| dcodefaultaddr | DCODE bus address which was present when a bus fault occurred. |
| debugger | Debugger Access Control |
| faultcaptureen | Enable the fault capture registers |
| faultstatus | Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. |
| icodefaultaddr | ICODE bus address which was present when a bus fault occurred. |
| ldoreg1 | Analog LDO Reg 1 |
| ldoreg3 | LDO Control Register 3 |
| pmuenable | Control bit to enable/disable the PMU |
| shadowvalid | Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space. |
| sysfaultaddr | System bus address which was present when a bus fault occurred. |
| tpiuctrl | TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. |
| vendorid | Unique Vendor ID |
| xtalgenctrl | XTAL Oscillator General Control |
Structs
| RegisterBlock | Register block |
Type Definitions
| ADCBATTLOAD | ADC Battery Load Enable |
| ADCCAL | ADC Calibration Control |
| ADCPWRDLY | ADC Power Up Delay Control |
| BODPORCTRL | BOD and PDR control Register |
| BOOTLOADERLOW | Determines whether the bootloader code is visible at address 0x00000000 |
| BUCK | Analog Buck Control |
| BUCK3 | Buck control reg 3 |
| BUCKTRIM | Trim settings for Core and Mem buck modules |
| CHIPID0 | Unique Chip ID 0 |
| CHIPID1 | Unique Chip ID 1 |
| CHIPREV | Chip Revision |
| CHIP_INFO | Chip Information Register |
| DBGR1 | Read-only debug register 1 |
| DBGR2 | Read-only debug register 2 |
| DCODEFAULTADDR | DCODE bus address which was present when a bus fault occurred. |
| DEBUGGER | Debugger Access Control |
| FAULTCAPTUREEN | Enable the fault capture registers |
| FAULTSTATUS | Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register. |
| ICODEFAULTADDR | ICODE bus address which was present when a bus fault occurred. |
| LDOREG1 | Analog LDO Reg 1 |
| LDOREG3 | LDO Control Register 3 |
| PMUENABLE | Control bit to enable/disable the PMU |
| SHADOWVALID | Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space. |
| SYSFAULTADDR | System bus address which was present when a bus fault occurred. |
| TPIUCTRL | TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface. |
| VENDORID | Unique Vendor ID |
| XTALGENCTRL | XTAL Oscillator General Control |