[][src]Type Definition ambiq_apollo1_pac::wdt::cfg::R

type R = R<u32, CFG>;

Reader of register CFG

Methods

impl R[src]

pub fn intval(&self) -> INTVAL_R[src]

Bits 16:23 - This bitfield is the compare value for counter bits 7:0 to generate a watchdog interrupt.

pub fn resval(&self) -> RESVAL_R[src]

Bits 8:15 - This bitfield is the compare value for counter bits 7:0 to generate a watchdog reset.

pub fn resen(&self) -> RESEN_R[src]

Bit 2 - This bitfield enables the WDT reset.

pub fn inten(&self) -> INTEN_R[src]

Bit 1 - This bitfield enables the WDT interrupt. Note : This bit must be set before the interrupt status bit will reflect a watchdog timer expiration. The IER interrupt register must also be enabled for a WDT interrupt to be sent to the NVIC.

pub fn wdten(&self) -> WDTEN_R[src]

Bit 0 - This bitfield enables the WDT.