[][src]Type Definition ambiq_apollo1_pac::uart::cr::W

type W = W<u32, CR>;

Writer for register CR

Methods

impl W[src]

pub fn ctsen(&mut self) -> CTSEN_W[src]

Bit 15 - This bit enables CTS hardware flow control.

pub fn rtsen(&mut self) -> RTSEN_W[src]

Bit 14 - This bit enables RTS hardware flow control.

pub fn out2(&mut self) -> OUT2_W[src]

Bit 13 - This bit holds modem Out2.

pub fn out1(&mut self) -> OUT1_W[src]

Bit 12 - This bit holds modem Out1.

pub fn rts(&mut self) -> RTS_W[src]

Bit 11 - This bit enables request to send.

pub fn dtr(&mut self) -> DTR_W[src]

Bit 10 - This bit enables data transmit ready.

pub fn rxe(&mut self) -> RXE_W[src]

Bit 9 - This bit is the receive enable.

pub fn txe(&mut self) -> TXE_W[src]

Bit 8 - This bit is the transmit enable.

pub fn lbe(&mut self) -> LBE_W[src]

Bit 7 - This bit is the loopback enable.

pub fn clksel(&mut self) -> CLKSEL_W[src]

Bits 4:6 - This bitfield is the UART clock select.

pub fn clken(&mut self) -> CLKEN_W[src]

Bit 3 - This bit is the UART clock enable.

pub fn sirlp(&mut self) -> SIRLP_W[src]

Bit 2 - This bit is the SIR low power select.

pub fn siren(&mut self) -> SIREN_W[src]

Bit 1 - This bit is the SIR ENDEC enable.

pub fn uarten(&mut self) -> UARTEN_W[src]

Bit 0 - This bit is the UART enable.