[−][src]Module ambiq_apollo1_pac::ctimer
Counter/Timer
Modules
cmpra0 | Counter/Timer A0 Compare Registers |
cmpra1 | Counter/Timer A1 Compare Registers |
cmpra2 | Counter/Timer A2 Compare Registers |
cmpra3 | Counter/Timer A3 Compare Registers |
cmprb0 | Counter/Timer B0 Compare Registers |
cmprb1 | Counter/Timer B1 Compare Registers |
cmprb2 | Counter/Timer B2 Compare Registers |
cmprb3 | Counter/Timer B3 Compare Registers |
ctrl0 | Counter/Timer Control |
ctrl1 | Counter/Timer Control |
ctrl2 | Counter/Timer Control |
ctrl3 | Counter/Timer Control |
intclr | Counter/Timer Interrupts: Clear |
inten | Counter/Timer Interrupts: Enable |
intset | Counter/Timer Interrupts: Set |
intstat | Counter/Timer Interrupts: Status |
tmr0 | Counter/Timer Register |
tmr1 | Counter/Timer Register |
tmr2 | Counter/Timer Register |
tmr3 | Counter/Timer Register |
Structs
RegisterBlock | Register block |
Type Definitions
CMPRA0 | Counter/Timer A0 Compare Registers |
CMPRA1 | Counter/Timer A1 Compare Registers |
CMPRA2 | Counter/Timer A2 Compare Registers |
CMPRA3 | Counter/Timer A3 Compare Registers |
CMPRB0 | Counter/Timer B0 Compare Registers |
CMPRB1 | Counter/Timer B1 Compare Registers |
CMPRB2 | Counter/Timer B2 Compare Registers |
CMPRB3 | Counter/Timer B3 Compare Registers |
CTRL0 | Counter/Timer Control |
CTRL1 | Counter/Timer Control |
CTRL2 | Counter/Timer Control |
CTRL3 | Counter/Timer Control |
INTCLR | Counter/Timer Interrupts: Clear |
INTEN | Counter/Timer Interrupts: Enable |
INTSET | Counter/Timer Interrupts: Set |
INTSTAT | Counter/Timer Interrupts: Status |
TMR0 | Counter/Timer Register |
TMR1 | Counter/Timer Register |
TMR2 | Counter/Timer Register |
TMR3 | Counter/Timer Register |