[−][src]Module ambiq_apollo1_pac::ctimer::ctrl0

Counter/Timer Control

Structs

CTLINK0_W	Write proxy for field `CTLINK0`
TMRA0PE_W	Write proxy for field `TMRA0PE`
TMRA0IE_W	Write proxy for field `TMRA0IE`
TMRA0FN_W	Write proxy for field `TMRA0FN`
TMRA0EN_W	Write proxy for field `TMRA0EN`
TMRA0POL_W	Write proxy for field `TMRA0POL`
TMRA0CLR_W	Write proxy for field `TMRA0CLR`
TMRA0CLK_W	Write proxy for field `TMRA0CLK`
TMRB0PE_W	Write proxy for field `TMRB0PE`
TMRB0IE_W	Write proxy for field `TMRB0IE`
TMRB0FN_W	Write proxy for field `TMRB0FN`
TMRB0EN_W	Write proxy for field `TMRB0EN`
TMRB0POL_W	Write proxy for field `TMRB0POL`
TMRB0CLR_W	Write proxy for field `TMRB0CLR`
TMRB0CLK_W	Write proxy for field `TMRB0CLK`

CTLINK0_A	Counter/Timer A0/B0 Link bit.
TMRA0PE_A	Counter/Timer A0 Output Enable bit.
TMRA0IE_A	Counter/Timer A0 Interrupt Enable bit.
TMRA0FN_A	Counter/Timer A0 Function Select.
TMRA0EN_A	Counter/Timer A0 Enable bit.
TMRA0POL_A	Counter/Timer A0 output polarity.
TMRA0CLR_A	Counter/Timer A0 Clear bit.
TMRA0CLK_A	Counter/Timer A0 Clock Select.
TMRB0PE_A	Counter/Timer B0 Output Enable bit.
TMRB0IE_A	Counter/Timer B0 Interrupt Enable bit.
TMRB0FN_A	Counter/Timer B0 Function Select.
TMRB0EN_A	Counter/Timer B0 Enable bit.
TMRB0POL_A	Counter/Timer B0 output polarity.
TMRB0CLR_A	Counter/Timer B0 Clear bit.
TMRB0CLK_A	Counter/Timer B0 Clock Select.